TsiChungLiew | a1436a8 | 2007-08-16 13:20:50 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. |
| 3 | * Hayden Fraser (Hayden.Fraser@freescale.com) |
| 4 | * |
Wolfgang Denk | 3765b3e | 2013-10-07 13:07:26 +0200 | [diff] [blame] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
TsiChungLiew | a1436a8 | 2007-08-16 13:20:50 -0500 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #ifndef _M5253EVBE_H |
| 9 | #define _M5253EVBE_H |
| 10 | |
TsiChungLiew | a1436a8 | 2007-08-16 13:20:50 -0500 | [diff] [blame] | 11 | #define CONFIG_M5253EVBE /* define board type */ |
| 12 | |
| 13 | #define CONFIG_MCFTMR |
| 14 | |
| 15 | #define CONFIG_MCFUART |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 16 | #define CONFIG_SYS_UART_PORT (0) |
TsiChung Liew | 80ba61f | 2008-08-06 14:17:09 -0500 | [diff] [blame] | 17 | #define CONFIG_BAUDRATE 115200 |
TsiChungLiew | a1436a8 | 2007-08-16 13:20:50 -0500 | [diff] [blame] | 18 | |
| 19 | #undef CONFIG_WATCHDOG /* disable watchdog */ |
| 20 | |
| 21 | #define CONFIG_BOOTDELAY 5 |
| 22 | |
| 23 | /* Configuration for environment |
| 24 | * Environment is embedded in u-boot in the second sector of the flash |
| 25 | */ |
| 26 | #ifndef CONFIG_MONITOR_IS_IN_RAM |
Jean-Christophe PLAGNIOL-VILLARD | 0e8d158 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 27 | #define CONFIG_ENV_OFFSET 0x4000 |
| 28 | #define CONFIG_ENV_SECT_SIZE 0x2000 |
Jean-Christophe PLAGNIOL-VILLARD | 5a1aceb | 2008-09-10 22:48:04 +0200 | [diff] [blame] | 29 | #define CONFIG_ENV_IS_IN_FLASH 1 |
TsiChungLiew | a1436a8 | 2007-08-16 13:20:50 -0500 | [diff] [blame] | 30 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0e8d158 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 31 | #define CONFIG_ENV_ADDR 0xffe04000 |
| 32 | #define CONFIG_ENV_SECT_SIZE 0x2000 |
Jean-Christophe PLAGNIOL-VILLARD | 5a1aceb | 2008-09-10 22:48:04 +0200 | [diff] [blame] | 33 | #define CONFIG_ENV_IS_IN_FLASH 1 |
TsiChungLiew | a1436a8 | 2007-08-16 13:20:50 -0500 | [diff] [blame] | 34 | #endif |
| 35 | |
angelo@sysam.it | 5296cb1 | 2015-03-29 22:54:16 +0200 | [diff] [blame] | 36 | #define LDS_BOARD_TEXT \ |
| 37 | . = DEFINED(env_offset) ? env_offset : .; \ |
| 38 | common/env_embedded.o (.text) |
| 39 | |
| 40 | |
TsiChungLiew | a1436a8 | 2007-08-16 13:20:50 -0500 | [diff] [blame] | 41 | /* |
| 42 | * BOOTP options |
| 43 | */ |
| 44 | #undef CONFIG_BOOTP_BOOTFILESIZE |
| 45 | #undef CONFIG_BOOTP_BOOTPATH |
| 46 | #undef CONFIG_BOOTP_GATEWAY |
| 47 | #undef CONFIG_BOOTP_HOSTNAME |
| 48 | |
| 49 | /* |
| 50 | * Command line configuration. |
| 51 | */ |
| 52 | #include <config_cmd_default.h> |
TsiChung Liew | dd9f054 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 53 | #define CONFIG_CMD_CACHE |
TsiChungLiew | a1436a8 | 2007-08-16 13:20:50 -0500 | [diff] [blame] | 54 | #define CONFIG_CMD_LOADB |
| 55 | #define CONFIG_CMD_LOADS |
| 56 | #define CONFIG_CMD_EXT2 |
| 57 | #define CONFIG_CMD_FAT |
| 58 | #define CONFIG_CMD_IDE |
| 59 | #define CONFIG_CMD_MEMORY |
| 60 | #define CONFIG_CMD_MISC |
| 61 | |
| 62 | /* ATA */ |
| 63 | #define CONFIG_DOS_PARTITION |
| 64 | #define CONFIG_MAC_PARTITION |
| 65 | #define CONFIG_IDE_RESET 1 |
| 66 | #define CONFIG_IDE_PREINIT 1 |
| 67 | #define CONFIG_ATAPI |
| 68 | #undef CONFIG_LBA48 |
| 69 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 70 | #define CONFIG_SYS_IDE_MAXBUS 1 |
| 71 | #define CONFIG_SYS_IDE_MAXDEVICE 2 |
TsiChungLiew | a1436a8 | 2007-08-16 13:20:50 -0500 | [diff] [blame] | 72 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 73 | #define CONFIG_SYS_ATA_BASE_ADDR (CONFIG_SYS_MBAR2 + 0x800) |
| 74 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0 |
TsiChungLiew | a1436a8 | 2007-08-16 13:20:50 -0500 | [diff] [blame] | 75 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 76 | #define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */ |
| 77 | #define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ |
| 78 | #define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ |
| 79 | #define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ |
TsiChungLiew | a1436a8 | 2007-08-16 13:20:50 -0500 | [diff] [blame] | 80 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 81 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
TsiChungLiew | a1436a8 | 2007-08-16 13:20:50 -0500 | [diff] [blame] | 82 | |
| 83 | #if defined(CONFIG_CMD_KGDB) |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 84 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
TsiChungLiew | a1436a8 | 2007-08-16 13:20:50 -0500 | [diff] [blame] | 85 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 86 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
TsiChungLiew | a1436a8 | 2007-08-16 13:20:50 -0500 | [diff] [blame] | 87 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 88 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
| 89 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
| 90 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
TsiChungLiew | a1436a8 | 2007-08-16 13:20:50 -0500 | [diff] [blame] | 91 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 92 | #define CONFIG_SYS_LOAD_ADDR 0x00100000 |
TsiChungLiew | a1436a8 | 2007-08-16 13:20:50 -0500 | [diff] [blame] | 93 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 94 | #define CONFIG_SYS_MEMTEST_START 0x400 |
| 95 | #define CONFIG_SYS_MEMTEST_END 0x380000 |
TsiChungLiew | a1436a8 | 2007-08-16 13:20:50 -0500 | [diff] [blame] | 96 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 97 | #undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ |
| 98 | #define CONFIG_SYS_FAST_CLK |
| 99 | #ifdef CONFIG_SYS_FAST_CLK |
| 100 | # define CONFIG_SYS_PLLCR 0x1243E054 |
| 101 | # define CONFIG_SYS_CLK 140000000 |
TsiChungLiew | a1436a8 | 2007-08-16 13:20:50 -0500 | [diff] [blame] | 102 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 103 | # define CONFIG_SYS_PLLCR 0x135a4140 |
| 104 | # define CONFIG_SYS_CLK 70000000 |
TsiChungLiew | a1436a8 | 2007-08-16 13:20:50 -0500 | [diff] [blame] | 105 | #endif |
| 106 | |
| 107 | /* |
| 108 | * Low Level Configuration Settings |
| 109 | * (address mappings, register initial values, etc.) |
| 110 | * You should know what you are doing if you make changes here. |
| 111 | */ |
| 112 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 113 | #define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ |
| 114 | #define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */ |
TsiChungLiew | a1436a8 | 2007-08-16 13:20:50 -0500 | [diff] [blame] | 115 | |
| 116 | /* |
| 117 | * Definitions for initial stack pointer and data area (in DPRAM) |
| 118 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 119 | #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 |
Wolfgang Denk | 553f098 | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 120 | #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ |
Wolfgang Denk | 25ddd1f | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 121 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 122 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
TsiChungLiew | a1436a8 | 2007-08-16 13:20:50 -0500 | [diff] [blame] | 123 | |
| 124 | /* |
| 125 | * Start addresses for the final memory configuration |
| 126 | * (Set up by the startup code) |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 127 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
TsiChungLiew | a1436a8 | 2007-08-16 13:20:50 -0500 | [diff] [blame] | 128 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 129 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
| 130 | #define CONFIG_SYS_SDRAM_SIZE 8 /* SDRAM size in MB */ |
TsiChungLiew | a1436a8 | 2007-08-16 13:20:50 -0500 | [diff] [blame] | 131 | |
| 132 | #ifdef CONFIG_MONITOR_IS_IN_RAM |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 133 | #define CONFIG_SYS_MONITOR_BASE 0x20000 |
TsiChungLiew | a1436a8 | 2007-08-16 13:20:50 -0500 | [diff] [blame] | 134 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 135 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) |
TsiChungLiew | a1436a8 | 2007-08-16 13:20:50 -0500 | [diff] [blame] | 136 | #endif |
| 137 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 138 | #define CONFIG_SYS_MONITOR_LEN 0x40000 |
| 139 | #define CONFIG_SYS_MALLOC_LEN (256 << 10) |
| 140 | #define CONFIG_SYS_BOOTPARAMS_LEN (64*1024) |
TsiChungLiew | a1436a8 | 2007-08-16 13:20:50 -0500 | [diff] [blame] | 141 | |
| 142 | /* |
| 143 | * For booting Linux, the board info and command line data |
| 144 | * have to be in the first 8 MB of memory, since this is |
| 145 | * the maximum mapped by the Linux kernel during initialization ?? |
| 146 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 147 | #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) |
TsiChung Liew | d6e4baf | 2009-01-27 12:57:47 +0000 | [diff] [blame] | 148 | #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) |
TsiChungLiew | a1436a8 | 2007-08-16 13:20:50 -0500 | [diff] [blame] | 149 | |
| 150 | /* FLASH organization */ |
TsiChung Liew | 012522f | 2008-10-21 10:03:07 +0000 | [diff] [blame] | 151 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 152 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
| 153 | #define CONFIG_SYS_MAX_FLASH_SECT 35 /* max number of sectors on one chip */ |
| 154 | #define CONFIG_SYS_FLASH_ERASE_TOUT 1000 |
TsiChungLiew | a1436a8 | 2007-08-16 13:20:50 -0500 | [diff] [blame] | 155 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 156 | #define CONFIG_SYS_FLASH_CFI 1 |
Jean-Christophe PLAGNIOL-VILLARD | 00b1883 | 2008-08-13 01:40:42 +0200 | [diff] [blame] | 157 | #define CONFIG_FLASH_CFI_DRIVER 1 |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 158 | #define CONFIG_SYS_FLASH_SIZE 0x200000 |
| 159 | #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT |
TsiChungLiew | a1436a8 | 2007-08-16 13:20:50 -0500 | [diff] [blame] | 160 | |
| 161 | /* Cache Configuration */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 162 | #define CONFIG_SYS_CACHELINE_SIZE 16 |
TsiChungLiew | a1436a8 | 2007-08-16 13:20:50 -0500 | [diff] [blame] | 163 | |
TsiChung Liew | dd9f054 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 164 | #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
Wolfgang Denk | 553f098 | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 165 | CONFIG_SYS_INIT_RAM_SIZE - 8) |
TsiChung Liew | dd9f054 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 166 | #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
Wolfgang Denk | 553f098 | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 167 | CONFIG_SYS_INIT_RAM_SIZE - 4) |
TsiChung Liew | dd9f054 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 168 | #define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM) |
| 169 | #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \ |
| 170 | CF_ADDRMASK(2) | \ |
| 171 | CF_ACR_EN | CF_ACR_SM_ALL) |
| 172 | #define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \ |
| 173 | CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ |
| 174 | CF_ACR_EN | CF_ACR_SM_ALL) |
| 175 | #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ |
| 176 | CF_CACR_DBWE) |
| 177 | |
TsiChungLiew | a1436a8 | 2007-08-16 13:20:50 -0500 | [diff] [blame] | 178 | /* Port configuration */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 179 | #define CONFIG_SYS_FECI2C 0xF0 |
TsiChungLiew | a1436a8 | 2007-08-16 13:20:50 -0500 | [diff] [blame] | 180 | |
TsiChung Liew | 012522f | 2008-10-21 10:03:07 +0000 | [diff] [blame] | 181 | #define CONFIG_SYS_CS0_BASE 0xFFE00000 |
| 182 | #define CONFIG_SYS_CS0_MASK 0x001F0021 |
| 183 | #define CONFIG_SYS_CS0_CTRL 0x00001D80 |
TsiChungLiew | a1436a8 | 2007-08-16 13:20:50 -0500 | [diff] [blame] | 184 | |
| 185 | /*----------------------------------------------------------------------- |
| 186 | * Port configuration |
| 187 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 188 | #define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ |
| 189 | #define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */ |
| 190 | #define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */ |
| 191 | #define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */ |
| 192 | #define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */ |
| 193 | #define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ |
| 194 | #define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */ |
TsiChungLiew | a1436a8 | 2007-08-16 13:20:50 -0500 | [diff] [blame] | 195 | |
| 196 | #endif /* _M5253EVB_H */ |