Simon Glass | ff3e077 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2014 Google, Inc |
| 3 | * Written by Simon Glass <sjg@chromium.org> |
| 4 | * |
| 5 | * SPDX-License-Identifier: GPL-2.0+ |
| 6 | */ |
| 7 | |
| 8 | #include <common.h> |
| 9 | #include <dm.h> |
| 10 | #include <errno.h> |
| 11 | #include <fdtdec.h> |
| 12 | #include <inttypes.h> |
| 13 | #include <pci.h> |
Simon Glass | 21d1fe7 | 2015-11-29 13:18:03 -0700 | [diff] [blame] | 14 | #include <asm/io.h> |
Simon Glass | ff3e077 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 15 | #include <dm/lists.h> |
| 16 | #include <dm/root.h> |
| 17 | #include <dm/device-internal.h> |
Bin Meng | 348b744 | 2015-08-20 06:40:23 -0700 | [diff] [blame] | 18 | #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP) |
| 19 | #include <asm/fsp/fsp_support.h> |
| 20 | #endif |
Simon Glass | 5e23b8b | 2015-11-29 13:17:49 -0700 | [diff] [blame] | 21 | #include "pci_internal.h" |
Simon Glass | ff3e077 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 22 | |
| 23 | DECLARE_GLOBAL_DATA_PTR; |
| 24 | |
Simon Glass | a6eb93b | 2016-01-18 20:19:14 -0700 | [diff] [blame] | 25 | int pci_get_bus(int busnum, struct udevice **busp) |
Simon Glass | 983c6ba2 | 2015-08-31 18:55:35 -0600 | [diff] [blame] | 26 | { |
| 27 | int ret; |
| 28 | |
| 29 | ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp); |
| 30 | |
| 31 | /* Since buses may not be numbered yet try a little harder with bus 0 */ |
| 32 | if (ret == -ENODEV) { |
Simon Glass | 3f603cb | 2016-02-11 13:23:26 -0700 | [diff] [blame] | 33 | ret = uclass_first_device_err(UCLASS_PCI, busp); |
Simon Glass | 983c6ba2 | 2015-08-31 18:55:35 -0600 | [diff] [blame] | 34 | if (ret) |
| 35 | return ret; |
Simon Glass | 983c6ba2 | 2015-08-31 18:55:35 -0600 | [diff] [blame] | 36 | ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp); |
| 37 | } |
| 38 | |
| 39 | return ret; |
| 40 | } |
| 41 | |
Simon Glass | 9f60fb0 | 2015-11-19 20:27:00 -0700 | [diff] [blame] | 42 | struct udevice *pci_get_controller(struct udevice *dev) |
| 43 | { |
| 44 | while (device_is_on_pci_bus(dev)) |
| 45 | dev = dev->parent; |
| 46 | |
| 47 | return dev; |
| 48 | } |
| 49 | |
Simon Glass | 21ccce1 | 2015-11-29 13:17:47 -0700 | [diff] [blame] | 50 | pci_dev_t dm_pci_get_bdf(struct udevice *dev) |
Simon Glass | 4b515e4 | 2015-07-06 16:47:46 -0600 | [diff] [blame] | 51 | { |
| 52 | struct pci_child_platdata *pplat = dev_get_parent_platdata(dev); |
| 53 | struct udevice *bus = dev->parent; |
| 54 | |
| 55 | return PCI_ADD_BUS(bus->seq, pplat->devfn); |
| 56 | } |
| 57 | |
Simon Glass | ff3e077 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 58 | /** |
| 59 | * pci_get_bus_max() - returns the bus number of the last active bus |
| 60 | * |
| 61 | * @return last bus number, or -1 if no active buses |
| 62 | */ |
| 63 | static int pci_get_bus_max(void) |
| 64 | { |
| 65 | struct udevice *bus; |
| 66 | struct uclass *uc; |
| 67 | int ret = -1; |
| 68 | |
| 69 | ret = uclass_get(UCLASS_PCI, &uc); |
| 70 | uclass_foreach_dev(bus, uc) { |
| 71 | if (bus->seq > ret) |
| 72 | ret = bus->seq; |
| 73 | } |
| 74 | |
| 75 | debug("%s: ret=%d\n", __func__, ret); |
| 76 | |
| 77 | return ret; |
| 78 | } |
| 79 | |
| 80 | int pci_last_busno(void) |
| 81 | { |
Bin Meng | 069155c | 2015-10-01 00:36:01 -0700 | [diff] [blame] | 82 | return pci_get_bus_max(); |
Simon Glass | ff3e077 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 83 | } |
| 84 | |
| 85 | int pci_get_ff(enum pci_size_t size) |
| 86 | { |
| 87 | switch (size) { |
| 88 | case PCI_SIZE_8: |
| 89 | return 0xff; |
| 90 | case PCI_SIZE_16: |
| 91 | return 0xffff; |
| 92 | default: |
| 93 | return 0xffffffff; |
| 94 | } |
| 95 | } |
| 96 | |
| 97 | int pci_bus_find_devfn(struct udevice *bus, pci_dev_t find_devfn, |
| 98 | struct udevice **devp) |
| 99 | { |
| 100 | struct udevice *dev; |
| 101 | |
| 102 | for (device_find_first_child(bus, &dev); |
| 103 | dev; |
| 104 | device_find_next_child(&dev)) { |
| 105 | struct pci_child_platdata *pplat; |
| 106 | |
| 107 | pplat = dev_get_parent_platdata(dev); |
| 108 | if (pplat && pplat->devfn == find_devfn) { |
| 109 | *devp = dev; |
| 110 | return 0; |
| 111 | } |
| 112 | } |
| 113 | |
| 114 | return -ENODEV; |
| 115 | } |
| 116 | |
Simon Glass | f3f1fae | 2015-11-29 13:17:48 -0700 | [diff] [blame] | 117 | int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp) |
Simon Glass | ff3e077 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 118 | { |
| 119 | struct udevice *bus; |
| 120 | int ret; |
| 121 | |
Simon Glass | 983c6ba2 | 2015-08-31 18:55:35 -0600 | [diff] [blame] | 122 | ret = pci_get_bus(PCI_BUS(bdf), &bus); |
Simon Glass | ff3e077 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 123 | if (ret) |
| 124 | return ret; |
| 125 | return pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), devp); |
| 126 | } |
| 127 | |
| 128 | static int pci_device_matches_ids(struct udevice *dev, |
| 129 | struct pci_device_id *ids) |
| 130 | { |
| 131 | struct pci_child_platdata *pplat; |
| 132 | int i; |
| 133 | |
| 134 | pplat = dev_get_parent_platdata(dev); |
| 135 | if (!pplat) |
| 136 | return -EINVAL; |
| 137 | for (i = 0; ids[i].vendor != 0; i++) { |
| 138 | if (pplat->vendor == ids[i].vendor && |
| 139 | pplat->device == ids[i].device) |
| 140 | return i; |
| 141 | } |
| 142 | |
| 143 | return -EINVAL; |
| 144 | } |
| 145 | |
| 146 | int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids, |
| 147 | int *indexp, struct udevice **devp) |
| 148 | { |
| 149 | struct udevice *dev; |
| 150 | |
| 151 | /* Scan all devices on this bus */ |
| 152 | for (device_find_first_child(bus, &dev); |
| 153 | dev; |
| 154 | device_find_next_child(&dev)) { |
| 155 | if (pci_device_matches_ids(dev, ids) >= 0) { |
| 156 | if ((*indexp)-- <= 0) { |
| 157 | *devp = dev; |
| 158 | return 0; |
| 159 | } |
| 160 | } |
| 161 | } |
| 162 | |
| 163 | return -ENODEV; |
| 164 | } |
| 165 | |
| 166 | int pci_find_device_id(struct pci_device_id *ids, int index, |
| 167 | struct udevice **devp) |
| 168 | { |
| 169 | struct udevice *bus; |
| 170 | |
| 171 | /* Scan all known buses */ |
| 172 | for (uclass_first_device(UCLASS_PCI, &bus); |
| 173 | bus; |
| 174 | uclass_next_device(&bus)) { |
| 175 | if (!pci_bus_find_devices(bus, ids, &index, devp)) |
| 176 | return 0; |
| 177 | } |
| 178 | *devp = NULL; |
| 179 | |
| 180 | return -ENODEV; |
| 181 | } |
| 182 | |
Simon Glass | 5c0bf64 | 2015-11-29 13:17:50 -0700 | [diff] [blame] | 183 | static int dm_pci_bus_find_device(struct udevice *bus, unsigned int vendor, |
| 184 | unsigned int device, int *indexp, |
| 185 | struct udevice **devp) |
| 186 | { |
| 187 | struct pci_child_platdata *pplat; |
| 188 | struct udevice *dev; |
| 189 | |
| 190 | for (device_find_first_child(bus, &dev); |
| 191 | dev; |
| 192 | device_find_next_child(&dev)) { |
| 193 | pplat = dev_get_parent_platdata(dev); |
| 194 | if (pplat->vendor == vendor && pplat->device == device) { |
| 195 | if (!(*indexp)--) { |
| 196 | *devp = dev; |
| 197 | return 0; |
| 198 | } |
| 199 | } |
| 200 | } |
| 201 | |
| 202 | return -ENODEV; |
| 203 | } |
| 204 | |
| 205 | int dm_pci_find_device(unsigned int vendor, unsigned int device, int index, |
| 206 | struct udevice **devp) |
| 207 | { |
| 208 | struct udevice *bus; |
| 209 | |
| 210 | /* Scan all known buses */ |
| 211 | for (uclass_first_device(UCLASS_PCI, &bus); |
| 212 | bus; |
| 213 | uclass_next_device(&bus)) { |
| 214 | if (!dm_pci_bus_find_device(bus, vendor, device, &index, devp)) |
| 215 | return device_probe(*devp); |
| 216 | } |
| 217 | *devp = NULL; |
| 218 | |
| 219 | return -ENODEV; |
| 220 | } |
| 221 | |
Simon Glass | a0eb835 | 2015-11-29 13:17:52 -0700 | [diff] [blame] | 222 | int dm_pci_find_class(uint find_class, int index, struct udevice **devp) |
| 223 | { |
| 224 | struct udevice *dev; |
| 225 | |
| 226 | /* Scan all known buses */ |
| 227 | for (pci_find_first_device(&dev); |
| 228 | dev; |
| 229 | pci_find_next_device(&dev)) { |
| 230 | struct pci_child_platdata *pplat = dev_get_parent_platdata(dev); |
| 231 | |
| 232 | if (pplat->class == find_class && !index--) { |
| 233 | *devp = dev; |
| 234 | return device_probe(*devp); |
| 235 | } |
| 236 | } |
| 237 | *devp = NULL; |
| 238 | |
| 239 | return -ENODEV; |
| 240 | } |
| 241 | |
Simon Glass | ff3e077 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 242 | int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset, |
| 243 | unsigned long value, enum pci_size_t size) |
| 244 | { |
| 245 | struct dm_pci_ops *ops; |
| 246 | |
| 247 | ops = pci_get_ops(bus); |
| 248 | if (!ops->write_config) |
| 249 | return -ENOSYS; |
| 250 | return ops->write_config(bus, bdf, offset, value, size); |
| 251 | } |
| 252 | |
Simon Glass | 319dba1 | 2016-03-06 19:27:52 -0700 | [diff] [blame^] | 253 | int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset, |
| 254 | u32 clr, u32 set) |
| 255 | { |
| 256 | ulong val; |
| 257 | int ret; |
| 258 | |
| 259 | ret = pci_bus_read_config(bus, bdf, offset, &val, PCI_SIZE_32); |
| 260 | if (ret) |
| 261 | return ret; |
| 262 | val &= ~clr; |
| 263 | val |= set; |
| 264 | |
| 265 | return pci_bus_write_config(bus, bdf, offset, val, PCI_SIZE_32); |
| 266 | } |
| 267 | |
Simon Glass | ff3e077 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 268 | int pci_write_config(pci_dev_t bdf, int offset, unsigned long value, |
| 269 | enum pci_size_t size) |
| 270 | { |
| 271 | struct udevice *bus; |
| 272 | int ret; |
| 273 | |
Simon Glass | 983c6ba2 | 2015-08-31 18:55:35 -0600 | [diff] [blame] | 274 | ret = pci_get_bus(PCI_BUS(bdf), &bus); |
Simon Glass | ff3e077 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 275 | if (ret) |
| 276 | return ret; |
| 277 | |
Bin Meng | 4d8615c | 2015-07-19 00:20:04 +0800 | [diff] [blame] | 278 | return pci_bus_write_config(bus, bdf, offset, value, size); |
Simon Glass | ff3e077 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 279 | } |
| 280 | |
Simon Glass | 66afb4e | 2015-08-10 07:05:03 -0600 | [diff] [blame] | 281 | int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value, |
| 282 | enum pci_size_t size) |
| 283 | { |
| 284 | struct udevice *bus; |
| 285 | |
Bin Meng | 1e0f226 | 2015-09-11 03:24:34 -0700 | [diff] [blame] | 286 | for (bus = dev; device_is_on_pci_bus(bus);) |
Simon Glass | 66afb4e | 2015-08-10 07:05:03 -0600 | [diff] [blame] | 287 | bus = bus->parent; |
Simon Glass | 21ccce1 | 2015-11-29 13:17:47 -0700 | [diff] [blame] | 288 | return pci_bus_write_config(bus, dm_pci_get_bdf(dev), offset, value, |
| 289 | size); |
Simon Glass | 66afb4e | 2015-08-10 07:05:03 -0600 | [diff] [blame] | 290 | } |
| 291 | |
| 292 | |
Simon Glass | ff3e077 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 293 | int pci_write_config32(pci_dev_t bdf, int offset, u32 value) |
| 294 | { |
| 295 | return pci_write_config(bdf, offset, value, PCI_SIZE_32); |
| 296 | } |
| 297 | |
| 298 | int pci_write_config16(pci_dev_t bdf, int offset, u16 value) |
| 299 | { |
| 300 | return pci_write_config(bdf, offset, value, PCI_SIZE_16); |
| 301 | } |
| 302 | |
| 303 | int pci_write_config8(pci_dev_t bdf, int offset, u8 value) |
| 304 | { |
| 305 | return pci_write_config(bdf, offset, value, PCI_SIZE_8); |
| 306 | } |
| 307 | |
Simon Glass | 66afb4e | 2015-08-10 07:05:03 -0600 | [diff] [blame] | 308 | int dm_pci_write_config8(struct udevice *dev, int offset, u8 value) |
| 309 | { |
| 310 | return dm_pci_write_config(dev, offset, value, PCI_SIZE_8); |
| 311 | } |
| 312 | |
| 313 | int dm_pci_write_config16(struct udevice *dev, int offset, u16 value) |
| 314 | { |
| 315 | return dm_pci_write_config(dev, offset, value, PCI_SIZE_16); |
| 316 | } |
| 317 | |
| 318 | int dm_pci_write_config32(struct udevice *dev, int offset, u32 value) |
| 319 | { |
| 320 | return dm_pci_write_config(dev, offset, value, PCI_SIZE_32); |
| 321 | } |
| 322 | |
Simon Glass | ff3e077 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 323 | int pci_bus_read_config(struct udevice *bus, pci_dev_t bdf, int offset, |
| 324 | unsigned long *valuep, enum pci_size_t size) |
| 325 | { |
| 326 | struct dm_pci_ops *ops; |
| 327 | |
| 328 | ops = pci_get_ops(bus); |
| 329 | if (!ops->read_config) |
| 330 | return -ENOSYS; |
| 331 | return ops->read_config(bus, bdf, offset, valuep, size); |
| 332 | } |
| 333 | |
| 334 | int pci_read_config(pci_dev_t bdf, int offset, unsigned long *valuep, |
| 335 | enum pci_size_t size) |
| 336 | { |
| 337 | struct udevice *bus; |
| 338 | int ret; |
| 339 | |
Simon Glass | 983c6ba2 | 2015-08-31 18:55:35 -0600 | [diff] [blame] | 340 | ret = pci_get_bus(PCI_BUS(bdf), &bus); |
Simon Glass | ff3e077 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 341 | if (ret) |
| 342 | return ret; |
| 343 | |
Bin Meng | 4d8615c | 2015-07-19 00:20:04 +0800 | [diff] [blame] | 344 | return pci_bus_read_config(bus, bdf, offset, valuep, size); |
Simon Glass | ff3e077 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 345 | } |
| 346 | |
Simon Glass | 66afb4e | 2015-08-10 07:05:03 -0600 | [diff] [blame] | 347 | int dm_pci_read_config(struct udevice *dev, int offset, unsigned long *valuep, |
| 348 | enum pci_size_t size) |
| 349 | { |
| 350 | struct udevice *bus; |
| 351 | |
Bin Meng | 1e0f226 | 2015-09-11 03:24:34 -0700 | [diff] [blame] | 352 | for (bus = dev; device_is_on_pci_bus(bus);) |
Simon Glass | 66afb4e | 2015-08-10 07:05:03 -0600 | [diff] [blame] | 353 | bus = bus->parent; |
Simon Glass | 21ccce1 | 2015-11-29 13:17:47 -0700 | [diff] [blame] | 354 | return pci_bus_read_config(bus, dm_pci_get_bdf(dev), offset, valuep, |
Simon Glass | 66afb4e | 2015-08-10 07:05:03 -0600 | [diff] [blame] | 355 | size); |
| 356 | } |
| 357 | |
Simon Glass | ff3e077 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 358 | int pci_read_config32(pci_dev_t bdf, int offset, u32 *valuep) |
| 359 | { |
| 360 | unsigned long value; |
| 361 | int ret; |
| 362 | |
| 363 | ret = pci_read_config(bdf, offset, &value, PCI_SIZE_32); |
| 364 | if (ret) |
| 365 | return ret; |
| 366 | *valuep = value; |
| 367 | |
| 368 | return 0; |
| 369 | } |
| 370 | |
| 371 | int pci_read_config16(pci_dev_t bdf, int offset, u16 *valuep) |
| 372 | { |
| 373 | unsigned long value; |
| 374 | int ret; |
| 375 | |
| 376 | ret = pci_read_config(bdf, offset, &value, PCI_SIZE_16); |
| 377 | if (ret) |
| 378 | return ret; |
| 379 | *valuep = value; |
| 380 | |
| 381 | return 0; |
| 382 | } |
| 383 | |
| 384 | int pci_read_config8(pci_dev_t bdf, int offset, u8 *valuep) |
| 385 | { |
| 386 | unsigned long value; |
| 387 | int ret; |
| 388 | |
| 389 | ret = pci_read_config(bdf, offset, &value, PCI_SIZE_8); |
| 390 | if (ret) |
| 391 | return ret; |
| 392 | *valuep = value; |
| 393 | |
| 394 | return 0; |
| 395 | } |
| 396 | |
Simon Glass | 66afb4e | 2015-08-10 07:05:03 -0600 | [diff] [blame] | 397 | int dm_pci_read_config8(struct udevice *dev, int offset, u8 *valuep) |
| 398 | { |
| 399 | unsigned long value; |
| 400 | int ret; |
| 401 | |
| 402 | ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_8); |
| 403 | if (ret) |
| 404 | return ret; |
| 405 | *valuep = value; |
| 406 | |
| 407 | return 0; |
| 408 | } |
| 409 | |
| 410 | int dm_pci_read_config16(struct udevice *dev, int offset, u16 *valuep) |
| 411 | { |
| 412 | unsigned long value; |
| 413 | int ret; |
| 414 | |
| 415 | ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_16); |
| 416 | if (ret) |
| 417 | return ret; |
| 418 | *valuep = value; |
| 419 | |
| 420 | return 0; |
| 421 | } |
| 422 | |
| 423 | int dm_pci_read_config32(struct udevice *dev, int offset, u32 *valuep) |
| 424 | { |
| 425 | unsigned long value; |
| 426 | int ret; |
| 427 | |
| 428 | ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_32); |
| 429 | if (ret) |
| 430 | return ret; |
| 431 | *valuep = value; |
| 432 | |
| 433 | return 0; |
| 434 | } |
| 435 | |
Simon Glass | 319dba1 | 2016-03-06 19:27:52 -0700 | [diff] [blame^] | 436 | int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set) |
| 437 | { |
| 438 | u8 val; |
| 439 | int ret; |
| 440 | |
| 441 | ret = dm_pci_read_config8(dev, offset, &val); |
| 442 | if (ret) |
| 443 | return ret; |
| 444 | val &= ~clr; |
| 445 | val |= set; |
| 446 | |
| 447 | return dm_pci_write_config8(dev, offset, val); |
| 448 | } |
| 449 | |
| 450 | int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set) |
| 451 | { |
| 452 | u16 val; |
| 453 | int ret; |
| 454 | |
| 455 | ret = dm_pci_read_config16(dev, offset, &val); |
| 456 | if (ret) |
| 457 | return ret; |
| 458 | val &= ~clr; |
| 459 | val |= set; |
| 460 | |
| 461 | return dm_pci_write_config16(dev, offset, val); |
| 462 | } |
| 463 | |
| 464 | int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set) |
| 465 | { |
| 466 | u32 val; |
| 467 | int ret; |
| 468 | |
| 469 | ret = dm_pci_read_config32(dev, offset, &val); |
| 470 | if (ret) |
| 471 | return ret; |
| 472 | val &= ~clr; |
| 473 | val |= set; |
| 474 | |
| 475 | return dm_pci_write_config32(dev, offset, val); |
| 476 | } |
| 477 | |
Bin Meng | bbbcb52 | 2015-10-01 00:36:02 -0700 | [diff] [blame] | 478 | static void set_vga_bridge_bits(struct udevice *dev) |
| 479 | { |
| 480 | struct udevice *parent = dev->parent; |
| 481 | u16 bc; |
| 482 | |
| 483 | while (parent->seq != 0) { |
| 484 | dm_pci_read_config16(parent, PCI_BRIDGE_CONTROL, &bc); |
| 485 | bc |= PCI_BRIDGE_CTL_VGA; |
| 486 | dm_pci_write_config16(parent, PCI_BRIDGE_CONTROL, bc); |
| 487 | parent = parent->parent; |
| 488 | } |
| 489 | } |
| 490 | |
Simon Glass | ff3e077 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 491 | int pci_auto_config_devices(struct udevice *bus) |
| 492 | { |
| 493 | struct pci_controller *hose = bus->uclass_priv; |
Bin Meng | bbbcb52 | 2015-10-01 00:36:02 -0700 | [diff] [blame] | 494 | struct pci_child_platdata *pplat; |
Simon Glass | ff3e077 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 495 | unsigned int sub_bus; |
| 496 | struct udevice *dev; |
| 497 | int ret; |
| 498 | |
| 499 | sub_bus = bus->seq; |
| 500 | debug("%s: start\n", __func__); |
| 501 | pciauto_config_init(hose); |
| 502 | for (ret = device_find_first_child(bus, &dev); |
| 503 | !ret && dev; |
| 504 | ret = device_find_next_child(&dev)) { |
Simon Glass | ff3e077 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 505 | unsigned int max_bus; |
Simon Glass | 4d21455 | 2015-09-08 17:52:47 -0600 | [diff] [blame] | 506 | int ret; |
Simon Glass | ff3e077 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 507 | |
Simon Glass | ff3e077 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 508 | debug("%s: device %s\n", __func__, dev->name); |
Simon Glass | 5e23b8b | 2015-11-29 13:17:49 -0700 | [diff] [blame] | 509 | ret = dm_pciauto_config_device(dev); |
Simon Glass | 4d21455 | 2015-09-08 17:52:47 -0600 | [diff] [blame] | 510 | if (ret < 0) |
| 511 | return ret; |
| 512 | max_bus = ret; |
Simon Glass | ff3e077 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 513 | sub_bus = max(sub_bus, max_bus); |
Bin Meng | bbbcb52 | 2015-10-01 00:36:02 -0700 | [diff] [blame] | 514 | |
| 515 | pplat = dev_get_parent_platdata(dev); |
| 516 | if (pplat->class == (PCI_CLASS_DISPLAY_VGA << 8)) |
| 517 | set_vga_bridge_bits(dev); |
Simon Glass | ff3e077 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 518 | } |
| 519 | debug("%s: done\n", __func__); |
| 520 | |
| 521 | return sub_bus; |
| 522 | } |
| 523 | |
Simon Glass | 5e23b8b | 2015-11-29 13:17:49 -0700 | [diff] [blame] | 524 | int dm_pci_hose_probe_bus(struct udevice *bus) |
Simon Glass | ff3e077 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 525 | { |
Simon Glass | ff3e077 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 526 | int sub_bus; |
| 527 | int ret; |
| 528 | |
| 529 | debug("%s\n", __func__); |
Simon Glass | ff3e077 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 530 | |
| 531 | sub_bus = pci_get_bus_max() + 1; |
| 532 | debug("%s: bus = %d/%s\n", __func__, sub_bus, bus->name); |
Simon Glass | 5e23b8b | 2015-11-29 13:17:49 -0700 | [diff] [blame] | 533 | dm_pciauto_prescan_setup_bridge(bus, sub_bus); |
Simon Glass | ff3e077 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 534 | |
| 535 | ret = device_probe(bus); |
| 536 | if (ret) { |
Simon Glass | 3129ace | 2015-09-08 17:52:48 -0600 | [diff] [blame] | 537 | debug("%s: Cannot probe bus %s: %d\n", __func__, bus->name, |
Simon Glass | ff3e077 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 538 | ret); |
| 539 | return ret; |
| 540 | } |
| 541 | if (sub_bus != bus->seq) { |
| 542 | printf("%s: Internal error, bus '%s' got seq %d, expected %d\n", |
| 543 | __func__, bus->name, bus->seq, sub_bus); |
| 544 | return -EPIPE; |
| 545 | } |
| 546 | sub_bus = pci_get_bus_max(); |
Simon Glass | 5e23b8b | 2015-11-29 13:17:49 -0700 | [diff] [blame] | 547 | dm_pciauto_postscan_setup_bridge(bus, sub_bus); |
Simon Glass | ff3e077 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 548 | |
| 549 | return sub_bus; |
| 550 | } |
| 551 | |
Simon Glass | aba9296 | 2015-07-06 16:47:44 -0600 | [diff] [blame] | 552 | /** |
| 553 | * pci_match_one_device - Tell if a PCI device structure has a matching |
| 554 | * PCI device id structure |
| 555 | * @id: single PCI device id structure to match |
| 556 | * @dev: the PCI device structure to match against |
| 557 | * |
| 558 | * Returns the matching pci_device_id structure or %NULL if there is no match. |
| 559 | */ |
| 560 | static bool pci_match_one_id(const struct pci_device_id *id, |
| 561 | const struct pci_device_id *find) |
| 562 | { |
| 563 | if ((id->vendor == PCI_ANY_ID || id->vendor == find->vendor) && |
| 564 | (id->device == PCI_ANY_ID || id->device == find->device) && |
| 565 | (id->subvendor == PCI_ANY_ID || id->subvendor == find->subvendor) && |
| 566 | (id->subdevice == PCI_ANY_ID || id->subdevice == find->subdevice) && |
| 567 | !((id->class ^ find->class) & id->class_mask)) |
| 568 | return true; |
| 569 | |
| 570 | return false; |
| 571 | } |
| 572 | |
| 573 | /** |
| 574 | * pci_find_and_bind_driver() - Find and bind the right PCI driver |
| 575 | * |
| 576 | * This only looks at certain fields in the descriptor. |
Simon Glass | 5dbcf3a | 2015-09-08 17:52:49 -0600 | [diff] [blame] | 577 | * |
| 578 | * @parent: Parent bus |
| 579 | * @find_id: Specification of the driver to find |
| 580 | * @bdf: Bus/device/function addreess - see PCI_BDF() |
| 581 | * @devp: Returns a pointer to the device created |
| 582 | * @return 0 if OK, -EPERM if the device is not needed before relocation and |
| 583 | * therefore was not created, other -ve value on error |
Simon Glass | aba9296 | 2015-07-06 16:47:44 -0600 | [diff] [blame] | 584 | */ |
| 585 | static int pci_find_and_bind_driver(struct udevice *parent, |
Simon Glass | 5dbcf3a | 2015-09-08 17:52:49 -0600 | [diff] [blame] | 586 | struct pci_device_id *find_id, |
| 587 | pci_dev_t bdf, struct udevice **devp) |
Simon Glass | aba9296 | 2015-07-06 16:47:44 -0600 | [diff] [blame] | 588 | { |
| 589 | struct pci_driver_entry *start, *entry; |
| 590 | const char *drv; |
| 591 | int n_ents; |
| 592 | int ret; |
| 593 | char name[30], *str; |
Bin Meng | 08fc7b8 | 2015-08-20 06:40:17 -0700 | [diff] [blame] | 594 | bool bridge; |
Simon Glass | aba9296 | 2015-07-06 16:47:44 -0600 | [diff] [blame] | 595 | |
| 596 | *devp = NULL; |
| 597 | |
| 598 | debug("%s: Searching for driver: vendor=%x, device=%x\n", __func__, |
| 599 | find_id->vendor, find_id->device); |
| 600 | start = ll_entry_start(struct pci_driver_entry, pci_driver_entry); |
| 601 | n_ents = ll_entry_count(struct pci_driver_entry, pci_driver_entry); |
| 602 | for (entry = start; entry != start + n_ents; entry++) { |
| 603 | const struct pci_device_id *id; |
| 604 | struct udevice *dev; |
| 605 | const struct driver *drv; |
| 606 | |
| 607 | for (id = entry->match; |
| 608 | id->vendor || id->subvendor || id->class_mask; |
| 609 | id++) { |
| 610 | if (!pci_match_one_id(id, find_id)) |
| 611 | continue; |
| 612 | |
| 613 | drv = entry->driver; |
Bin Meng | 08fc7b8 | 2015-08-20 06:40:17 -0700 | [diff] [blame] | 614 | |
| 615 | /* |
| 616 | * In the pre-relocation phase, we only bind devices |
| 617 | * whose driver has the DM_FLAG_PRE_RELOC set, to save |
| 618 | * precious memory space as on some platforms as that |
| 619 | * space is pretty limited (ie: using Cache As RAM). |
| 620 | */ |
| 621 | if (!(gd->flags & GD_FLG_RELOC) && |
| 622 | !(drv->flags & DM_FLAG_PRE_RELOC)) |
Simon Glass | 5dbcf3a | 2015-09-08 17:52:49 -0600 | [diff] [blame] | 623 | return -EPERM; |
Bin Meng | 08fc7b8 | 2015-08-20 06:40:17 -0700 | [diff] [blame] | 624 | |
Simon Glass | aba9296 | 2015-07-06 16:47:44 -0600 | [diff] [blame] | 625 | /* |
| 626 | * We could pass the descriptor to the driver as |
| 627 | * platdata (instead of NULL) and allow its bind() |
| 628 | * method to return -ENOENT if it doesn't support this |
| 629 | * device. That way we could continue the search to |
| 630 | * find another driver. For now this doesn't seem |
| 631 | * necesssary, so just bind the first match. |
| 632 | */ |
| 633 | ret = device_bind(parent, drv, drv->name, NULL, -1, |
| 634 | &dev); |
| 635 | if (ret) |
| 636 | goto error; |
| 637 | debug("%s: Match found: %s\n", __func__, drv->name); |
| 638 | dev->driver_data = find_id->driver_data; |
| 639 | *devp = dev; |
| 640 | return 0; |
| 641 | } |
| 642 | } |
| 643 | |
Bin Meng | 08fc7b8 | 2015-08-20 06:40:17 -0700 | [diff] [blame] | 644 | bridge = (find_id->class >> 8) == PCI_CLASS_BRIDGE_PCI; |
| 645 | /* |
| 646 | * In the pre-relocation phase, we only bind bridge devices to save |
| 647 | * precious memory space as on some platforms as that space is pretty |
| 648 | * limited (ie: using Cache As RAM). |
| 649 | */ |
| 650 | if (!(gd->flags & GD_FLG_RELOC) && !bridge) |
Simon Glass | 5dbcf3a | 2015-09-08 17:52:49 -0600 | [diff] [blame] | 651 | return -EPERM; |
Bin Meng | 08fc7b8 | 2015-08-20 06:40:17 -0700 | [diff] [blame] | 652 | |
Simon Glass | aba9296 | 2015-07-06 16:47:44 -0600 | [diff] [blame] | 653 | /* Bind a generic driver so that the device can be used */ |
Bin Meng | 4d8615c | 2015-07-19 00:20:04 +0800 | [diff] [blame] | 654 | sprintf(name, "pci_%x:%x.%x", parent->seq, PCI_DEV(bdf), |
| 655 | PCI_FUNC(bdf)); |
Simon Glass | aba9296 | 2015-07-06 16:47:44 -0600 | [diff] [blame] | 656 | str = strdup(name); |
| 657 | if (!str) |
| 658 | return -ENOMEM; |
Bin Meng | 08fc7b8 | 2015-08-20 06:40:17 -0700 | [diff] [blame] | 659 | drv = bridge ? "pci_bridge_drv" : "pci_generic_drv"; |
| 660 | |
Simon Glass | aba9296 | 2015-07-06 16:47:44 -0600 | [diff] [blame] | 661 | ret = device_bind_driver(parent, drv, str, devp); |
| 662 | if (ret) { |
Simon Glass | 3129ace | 2015-09-08 17:52:48 -0600 | [diff] [blame] | 663 | debug("%s: Failed to bind generic driver: %d\n", __func__, ret); |
Simon Glass | aba9296 | 2015-07-06 16:47:44 -0600 | [diff] [blame] | 664 | return ret; |
| 665 | } |
| 666 | debug("%s: No match found: bound generic driver instead\n", __func__); |
| 667 | |
| 668 | return 0; |
| 669 | |
| 670 | error: |
| 671 | debug("%s: No match found: error %d\n", __func__, ret); |
| 672 | return ret; |
| 673 | } |
| 674 | |
Simon Glass | ff3e077 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 675 | int pci_bind_bus_devices(struct udevice *bus) |
| 676 | { |
| 677 | ulong vendor, device; |
| 678 | ulong header_type; |
Bin Meng | 4d8615c | 2015-07-19 00:20:04 +0800 | [diff] [blame] | 679 | pci_dev_t bdf, end; |
Simon Glass | ff3e077 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 680 | bool found_multi; |
| 681 | int ret; |
| 682 | |
| 683 | found_multi = false; |
Bin Meng | 4d8615c | 2015-07-19 00:20:04 +0800 | [diff] [blame] | 684 | end = PCI_BDF(bus->seq, PCI_MAX_PCI_DEVICES - 1, |
| 685 | PCI_MAX_PCI_FUNCTIONS - 1); |
| 686 | for (bdf = PCI_BDF(bus->seq, 0, 0); bdf < end; |
| 687 | bdf += PCI_BDF(0, 0, 1)) { |
Simon Glass | ff3e077 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 688 | struct pci_child_platdata *pplat; |
| 689 | struct udevice *dev; |
| 690 | ulong class; |
| 691 | |
Bin Meng | 4d8615c | 2015-07-19 00:20:04 +0800 | [diff] [blame] | 692 | if (PCI_FUNC(bdf) && !found_multi) |
Simon Glass | ff3e077 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 693 | continue; |
| 694 | /* Check only the first access, we don't expect problems */ |
Bin Meng | 4d8615c | 2015-07-19 00:20:04 +0800 | [diff] [blame] | 695 | ret = pci_bus_read_config(bus, bdf, PCI_HEADER_TYPE, |
Simon Glass | ff3e077 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 696 | &header_type, PCI_SIZE_8); |
| 697 | if (ret) |
| 698 | goto error; |
Bin Meng | 4d8615c | 2015-07-19 00:20:04 +0800 | [diff] [blame] | 699 | pci_bus_read_config(bus, bdf, PCI_VENDOR_ID, &vendor, |
Simon Glass | ff3e077 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 700 | PCI_SIZE_16); |
| 701 | if (vendor == 0xffff || vendor == 0x0000) |
| 702 | continue; |
| 703 | |
Bin Meng | 4d8615c | 2015-07-19 00:20:04 +0800 | [diff] [blame] | 704 | if (!PCI_FUNC(bdf)) |
Simon Glass | ff3e077 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 705 | found_multi = header_type & 0x80; |
| 706 | |
| 707 | debug("%s: bus %d/%s: found device %x, function %d\n", __func__, |
Bin Meng | 4d8615c | 2015-07-19 00:20:04 +0800 | [diff] [blame] | 708 | bus->seq, bus->name, PCI_DEV(bdf), PCI_FUNC(bdf)); |
| 709 | pci_bus_read_config(bus, bdf, PCI_DEVICE_ID, &device, |
Simon Glass | ff3e077 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 710 | PCI_SIZE_16); |
Bin Meng | 4d8615c | 2015-07-19 00:20:04 +0800 | [diff] [blame] | 711 | pci_bus_read_config(bus, bdf, PCI_CLASS_REVISION, &class, |
Simon Glass | aba9296 | 2015-07-06 16:47:44 -0600 | [diff] [blame] | 712 | PCI_SIZE_32); |
| 713 | class >>= 8; |
Simon Glass | ff3e077 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 714 | |
| 715 | /* Find this device in the device tree */ |
Bin Meng | 4d8615c | 2015-07-19 00:20:04 +0800 | [diff] [blame] | 716 | ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), &dev); |
Simon Glass | ff3e077 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 717 | |
Simon Glass | 8bd4252 | 2015-11-29 13:18:09 -0700 | [diff] [blame] | 718 | /* If nothing in the device tree, bind a device */ |
Simon Glass | ff3e077 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 719 | if (ret == -ENODEV) { |
Simon Glass | aba9296 | 2015-07-06 16:47:44 -0600 | [diff] [blame] | 720 | struct pci_device_id find_id; |
| 721 | ulong val; |
Simon Glass | ff3e077 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 722 | |
Simon Glass | aba9296 | 2015-07-06 16:47:44 -0600 | [diff] [blame] | 723 | memset(&find_id, '\0', sizeof(find_id)); |
| 724 | find_id.vendor = vendor; |
| 725 | find_id.device = device; |
| 726 | find_id.class = class; |
| 727 | if ((header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL) { |
Bin Meng | 4d8615c | 2015-07-19 00:20:04 +0800 | [diff] [blame] | 728 | pci_bus_read_config(bus, bdf, |
Simon Glass | aba9296 | 2015-07-06 16:47:44 -0600 | [diff] [blame] | 729 | PCI_SUBSYSTEM_VENDOR_ID, |
| 730 | &val, PCI_SIZE_32); |
| 731 | find_id.subvendor = val & 0xffff; |
| 732 | find_id.subdevice = val >> 16; |
| 733 | } |
Bin Meng | 4d8615c | 2015-07-19 00:20:04 +0800 | [diff] [blame] | 734 | ret = pci_find_and_bind_driver(bus, &find_id, bdf, |
Simon Glass | aba9296 | 2015-07-06 16:47:44 -0600 | [diff] [blame] | 735 | &dev); |
Simon Glass | ff3e077 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 736 | } |
Simon Glass | 5dbcf3a | 2015-09-08 17:52:49 -0600 | [diff] [blame] | 737 | if (ret == -EPERM) |
| 738 | continue; |
| 739 | else if (ret) |
Simon Glass | ff3e077 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 740 | return ret; |
| 741 | |
| 742 | /* Update the platform data */ |
Simon Glass | 5dbcf3a | 2015-09-08 17:52:49 -0600 | [diff] [blame] | 743 | pplat = dev_get_parent_platdata(dev); |
| 744 | pplat->devfn = PCI_MASK_BUS(bdf); |
| 745 | pplat->vendor = vendor; |
| 746 | pplat->device = device; |
| 747 | pplat->class = class; |
Simon Glass | ff3e077 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 748 | } |
| 749 | |
| 750 | return 0; |
| 751 | error: |
| 752 | printf("Cannot read bus configuration: %d\n", ret); |
| 753 | |
| 754 | return ret; |
| 755 | } |
| 756 | |
| 757 | static int pci_uclass_post_bind(struct udevice *bus) |
| 758 | { |
| 759 | /* |
Bin Meng | 1887ed3 | 2015-08-24 01:14:01 -0700 | [diff] [blame] | 760 | * If there is no pci device listed in the device tree, |
| 761 | * don't bother scanning the device tree. |
| 762 | */ |
| 763 | if (bus->of_offset == -1) |
| 764 | return 0; |
| 765 | |
| 766 | /* |
Simon Glass | ff3e077 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 767 | * Scan the device tree for devices. This does not probe the PCI bus, |
| 768 | * as this is not permitted while binding. It just finds devices |
| 769 | * mentioned in the device tree. |
| 770 | * |
| 771 | * Before relocation, only bind devices marked for pre-relocation |
| 772 | * use. |
| 773 | */ |
| 774 | return dm_scan_fdt_node(bus, gd->fdt_blob, bus->of_offset, |
| 775 | gd->flags & GD_FLG_RELOC ? false : true); |
| 776 | } |
| 777 | |
| 778 | static int decode_regions(struct pci_controller *hose, const void *blob, |
| 779 | int parent_node, int node) |
| 780 | { |
| 781 | int pci_addr_cells, addr_cells, size_cells; |
Simon Glass | 2084c5a | 2015-11-19 20:26:57 -0700 | [diff] [blame] | 782 | phys_addr_t base = 0, size; |
Simon Glass | ff3e077 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 783 | int cells_per_record; |
| 784 | const u32 *prop; |
| 785 | int len; |
| 786 | int i; |
| 787 | |
| 788 | prop = fdt_getprop(blob, node, "ranges", &len); |
| 789 | if (!prop) |
| 790 | return -EINVAL; |
| 791 | pci_addr_cells = fdt_address_cells(blob, node); |
| 792 | addr_cells = fdt_address_cells(blob, parent_node); |
| 793 | size_cells = fdt_size_cells(blob, node); |
| 794 | |
| 795 | /* PCI addresses are always 3-cells */ |
| 796 | len /= sizeof(u32); |
| 797 | cells_per_record = pci_addr_cells + addr_cells + size_cells; |
| 798 | hose->region_count = 0; |
| 799 | debug("%s: len=%d, cells_per_record=%d\n", __func__, len, |
| 800 | cells_per_record); |
| 801 | for (i = 0; i < MAX_PCI_REGIONS; i++, len -= cells_per_record) { |
| 802 | u64 pci_addr, addr, size; |
| 803 | int space_code; |
| 804 | u32 flags; |
| 805 | int type; |
Simon Glass | 9526d83 | 2015-11-19 20:26:58 -0700 | [diff] [blame] | 806 | int pos; |
Simon Glass | ff3e077 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 807 | |
| 808 | if (len < cells_per_record) |
| 809 | break; |
| 810 | flags = fdt32_to_cpu(prop[0]); |
| 811 | space_code = (flags >> 24) & 3; |
| 812 | pci_addr = fdtdec_get_number(prop + 1, 2); |
| 813 | prop += pci_addr_cells; |
| 814 | addr = fdtdec_get_number(prop, addr_cells); |
| 815 | prop += addr_cells; |
| 816 | size = fdtdec_get_number(prop, size_cells); |
| 817 | prop += size_cells; |
| 818 | debug("%s: region %d, pci_addr=%" PRIx64 ", addr=%" PRIx64 |
| 819 | ", size=%" PRIx64 ", space_code=%d\n", __func__, |
| 820 | hose->region_count, pci_addr, addr, size, space_code); |
| 821 | if (space_code & 2) { |
| 822 | type = flags & (1U << 30) ? PCI_REGION_PREFETCH : |
| 823 | PCI_REGION_MEM; |
| 824 | } else if (space_code & 1) { |
| 825 | type = PCI_REGION_IO; |
| 826 | } else { |
| 827 | continue; |
| 828 | } |
Simon Glass | 9526d83 | 2015-11-19 20:26:58 -0700 | [diff] [blame] | 829 | pos = -1; |
| 830 | for (i = 0; i < hose->region_count; i++) { |
| 831 | if (hose->regions[i].flags == type) |
| 832 | pos = i; |
| 833 | } |
| 834 | if (pos == -1) |
| 835 | pos = hose->region_count++; |
| 836 | debug(" - type=%d, pos=%d\n", type, pos); |
| 837 | pci_set_region(hose->regions + pos, pci_addr, addr, size, type); |
Simon Glass | ff3e077 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 838 | } |
| 839 | |
| 840 | /* Add a region for our local memory */ |
Simon Glass | 2084c5a | 2015-11-19 20:26:57 -0700 | [diff] [blame] | 841 | size = gd->ram_size; |
| 842 | #ifdef CONFIG_SYS_SDRAM_BASE |
| 843 | base = CONFIG_SYS_SDRAM_BASE; |
| 844 | #endif |
| 845 | if (gd->pci_ram_top && gd->pci_ram_top < base + size) |
| 846 | size = gd->pci_ram_top - base; |
| 847 | pci_set_region(hose->regions + hose->region_count++, base, base, |
| 848 | size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); |
Simon Glass | ff3e077 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 849 | |
| 850 | return 0; |
| 851 | } |
| 852 | |
| 853 | static int pci_uclass_pre_probe(struct udevice *bus) |
| 854 | { |
| 855 | struct pci_controller *hose; |
| 856 | int ret; |
| 857 | |
| 858 | debug("%s, bus=%d/%s, parent=%s\n", __func__, bus->seq, bus->name, |
| 859 | bus->parent->name); |
| 860 | hose = bus->uclass_priv; |
| 861 | |
| 862 | /* For bridges, use the top-level PCI controller */ |
| 863 | if (device_get_uclass_id(bus->parent) == UCLASS_ROOT) { |
| 864 | hose->ctlr = bus; |
| 865 | ret = decode_regions(hose, gd->fdt_blob, bus->parent->of_offset, |
| 866 | bus->of_offset); |
| 867 | if (ret) { |
| 868 | debug("%s: Cannot decode regions\n", __func__); |
| 869 | return ret; |
| 870 | } |
| 871 | } else { |
| 872 | struct pci_controller *parent_hose; |
| 873 | |
| 874 | parent_hose = dev_get_uclass_priv(bus->parent); |
| 875 | hose->ctlr = parent_hose->bus; |
| 876 | } |
| 877 | hose->bus = bus; |
| 878 | hose->first_busno = bus->seq; |
| 879 | hose->last_busno = bus->seq; |
| 880 | |
| 881 | return 0; |
| 882 | } |
| 883 | |
| 884 | static int pci_uclass_post_probe(struct udevice *bus) |
| 885 | { |
| 886 | int ret; |
| 887 | |
Simon Glass | ff3e077 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 888 | debug("%s: probing bus %d\n", __func__, bus->seq); |
| 889 | ret = pci_bind_bus_devices(bus); |
| 890 | if (ret) |
| 891 | return ret; |
| 892 | |
| 893 | #ifdef CONFIG_PCI_PNP |
| 894 | ret = pci_auto_config_devices(bus); |
Simon Glass | 4d21455 | 2015-09-08 17:52:47 -0600 | [diff] [blame] | 895 | if (ret < 0) |
| 896 | return ret; |
Simon Glass | ff3e077 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 897 | #endif |
| 898 | |
Bin Meng | 348b744 | 2015-08-20 06:40:23 -0700 | [diff] [blame] | 899 | #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP) |
| 900 | /* |
| 901 | * Per Intel FSP specification, we should call FSP notify API to |
| 902 | * inform FSP that PCI enumeration has been done so that FSP will |
| 903 | * do any necessary initialization as required by the chipset's |
| 904 | * BIOS Writer's Guide (BWG). |
| 905 | * |
| 906 | * Unfortunately we have to put this call here as with driver model, |
| 907 | * the enumeration is all done on a lazy basis as needed, so until |
| 908 | * something is touched on PCI it won't happen. |
| 909 | * |
| 910 | * Note we only call this 1) after U-Boot is relocated, and 2) |
| 911 | * root bus has finished probing. |
| 912 | */ |
Simon Glass | 4d21455 | 2015-09-08 17:52:47 -0600 | [diff] [blame] | 913 | if ((gd->flags & GD_FLG_RELOC) && (bus->seq == 0)) { |
Bin Meng | 348b744 | 2015-08-20 06:40:23 -0700 | [diff] [blame] | 914 | ret = fsp_init_phase_pci(); |
Simon Glass | 4d21455 | 2015-09-08 17:52:47 -0600 | [diff] [blame] | 915 | if (ret) |
| 916 | return ret; |
| 917 | } |
Bin Meng | 348b744 | 2015-08-20 06:40:23 -0700 | [diff] [blame] | 918 | #endif |
| 919 | |
Simon Glass | 4d21455 | 2015-09-08 17:52:47 -0600 | [diff] [blame] | 920 | return 0; |
Simon Glass | ff3e077 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 921 | } |
| 922 | |
| 923 | static int pci_uclass_child_post_bind(struct udevice *dev) |
| 924 | { |
| 925 | struct pci_child_platdata *pplat; |
| 926 | struct fdt_pci_addr addr; |
| 927 | int ret; |
| 928 | |
| 929 | if (dev->of_offset == -1) |
| 930 | return 0; |
| 931 | |
| 932 | /* |
| 933 | * We could read vendor, device, class if available. But for now we |
| 934 | * just check the address. |
| 935 | */ |
| 936 | pplat = dev_get_parent_platdata(dev); |
| 937 | ret = fdtdec_get_pci_addr(gd->fdt_blob, dev->of_offset, |
| 938 | FDT_PCI_SPACE_CONFIG, "reg", &addr); |
| 939 | |
| 940 | if (ret) { |
| 941 | if (ret != -ENOENT) |
| 942 | return -EINVAL; |
| 943 | } else { |
Bin Meng | dce54dd | 2015-08-20 06:40:26 -0700 | [diff] [blame] | 944 | /* extract the devfn from fdt_pci_addr */ |
| 945 | pplat->devfn = addr.phys_hi & 0xff00; |
Simon Glass | ff3e077 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 946 | } |
| 947 | |
| 948 | return 0; |
| 949 | } |
| 950 | |
Bin Meng | 4d8615c | 2015-07-19 00:20:04 +0800 | [diff] [blame] | 951 | static int pci_bridge_read_config(struct udevice *bus, pci_dev_t bdf, |
| 952 | uint offset, ulong *valuep, |
| 953 | enum pci_size_t size) |
Simon Glass | ff3e077 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 954 | { |
| 955 | struct pci_controller *hose = bus->uclass_priv; |
Simon Glass | ff3e077 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 956 | |
| 957 | return pci_bus_read_config(hose->ctlr, bdf, offset, valuep, size); |
| 958 | } |
| 959 | |
Bin Meng | 4d8615c | 2015-07-19 00:20:04 +0800 | [diff] [blame] | 960 | static int pci_bridge_write_config(struct udevice *bus, pci_dev_t bdf, |
| 961 | uint offset, ulong value, |
| 962 | enum pci_size_t size) |
Simon Glass | ff3e077 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 963 | { |
| 964 | struct pci_controller *hose = bus->uclass_priv; |
Simon Glass | ff3e077 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 965 | |
| 966 | return pci_bus_write_config(hose->ctlr, bdf, offset, value, size); |
| 967 | } |
| 968 | |
Simon Glass | 76c3fbc | 2015-08-10 07:05:04 -0600 | [diff] [blame] | 969 | static int skip_to_next_device(struct udevice *bus, struct udevice **devp) |
| 970 | { |
| 971 | struct udevice *dev; |
| 972 | int ret = 0; |
| 973 | |
| 974 | /* |
| 975 | * Scan through all the PCI controllers. On x86 there will only be one |
| 976 | * but that is not necessarily true on other hardware. |
| 977 | */ |
| 978 | do { |
| 979 | device_find_first_child(bus, &dev); |
| 980 | if (dev) { |
| 981 | *devp = dev; |
| 982 | return 0; |
| 983 | } |
| 984 | ret = uclass_next_device(&bus); |
| 985 | if (ret) |
| 986 | return ret; |
| 987 | } while (bus); |
| 988 | |
| 989 | return 0; |
| 990 | } |
| 991 | |
| 992 | int pci_find_next_device(struct udevice **devp) |
| 993 | { |
| 994 | struct udevice *child = *devp; |
| 995 | struct udevice *bus = child->parent; |
| 996 | int ret; |
| 997 | |
| 998 | /* First try all the siblings */ |
| 999 | *devp = NULL; |
| 1000 | while (child) { |
| 1001 | device_find_next_child(&child); |
| 1002 | if (child) { |
| 1003 | *devp = child; |
| 1004 | return 0; |
| 1005 | } |
| 1006 | } |
| 1007 | |
| 1008 | /* We ran out of siblings. Try the next bus */ |
| 1009 | ret = uclass_next_device(&bus); |
| 1010 | if (ret) |
| 1011 | return ret; |
| 1012 | |
| 1013 | return bus ? skip_to_next_device(bus, devp) : 0; |
| 1014 | } |
| 1015 | |
| 1016 | int pci_find_first_device(struct udevice **devp) |
| 1017 | { |
| 1018 | struct udevice *bus; |
| 1019 | int ret; |
| 1020 | |
| 1021 | *devp = NULL; |
| 1022 | ret = uclass_first_device(UCLASS_PCI, &bus); |
| 1023 | if (ret) |
| 1024 | return ret; |
| 1025 | |
| 1026 | return skip_to_next_device(bus, devp); |
| 1027 | } |
| 1028 | |
Simon Glass | 9289db6 | 2015-11-19 20:26:59 -0700 | [diff] [blame] | 1029 | ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size) |
| 1030 | { |
| 1031 | switch (size) { |
| 1032 | case PCI_SIZE_8: |
| 1033 | return (value >> ((offset & 3) * 8)) & 0xff; |
| 1034 | case PCI_SIZE_16: |
| 1035 | return (value >> ((offset & 2) * 8)) & 0xffff; |
| 1036 | default: |
| 1037 | return value; |
| 1038 | } |
| 1039 | } |
| 1040 | |
| 1041 | ulong pci_conv_size_to_32(ulong old, ulong value, uint offset, |
| 1042 | enum pci_size_t size) |
| 1043 | { |
| 1044 | uint off_mask; |
| 1045 | uint val_mask, shift; |
| 1046 | ulong ldata, mask; |
| 1047 | |
| 1048 | switch (size) { |
| 1049 | case PCI_SIZE_8: |
| 1050 | off_mask = 3; |
| 1051 | val_mask = 0xff; |
| 1052 | break; |
| 1053 | case PCI_SIZE_16: |
| 1054 | off_mask = 2; |
| 1055 | val_mask = 0xffff; |
| 1056 | break; |
| 1057 | default: |
| 1058 | return value; |
| 1059 | } |
| 1060 | shift = (offset & off_mask) * 8; |
| 1061 | ldata = (value & val_mask) << shift; |
| 1062 | mask = val_mask << shift; |
| 1063 | value = (old & ~mask) | ldata; |
| 1064 | |
| 1065 | return value; |
| 1066 | } |
| 1067 | |
Simon Glass | f926033 | 2015-11-19 20:27:01 -0700 | [diff] [blame] | 1068 | int pci_get_regions(struct udevice *dev, struct pci_region **iop, |
| 1069 | struct pci_region **memp, struct pci_region **prefp) |
| 1070 | { |
| 1071 | struct udevice *bus = pci_get_controller(dev); |
| 1072 | struct pci_controller *hose = dev_get_uclass_priv(bus); |
| 1073 | int i; |
| 1074 | |
| 1075 | *iop = NULL; |
| 1076 | *memp = NULL; |
| 1077 | *prefp = NULL; |
| 1078 | for (i = 0; i < hose->region_count; i++) { |
| 1079 | switch (hose->regions[i].flags) { |
| 1080 | case PCI_REGION_IO: |
| 1081 | if (!*iop || (*iop)->size < hose->regions[i].size) |
| 1082 | *iop = hose->regions + i; |
| 1083 | break; |
| 1084 | case PCI_REGION_MEM: |
| 1085 | if (!*memp || (*memp)->size < hose->regions[i].size) |
| 1086 | *memp = hose->regions + i; |
| 1087 | break; |
| 1088 | case (PCI_REGION_MEM | PCI_REGION_PREFETCH): |
| 1089 | if (!*prefp || (*prefp)->size < hose->regions[i].size) |
| 1090 | *prefp = hose->regions + i; |
| 1091 | break; |
| 1092 | } |
| 1093 | } |
| 1094 | |
| 1095 | return (*iop != NULL) + (*memp != NULL) + (*prefp != NULL); |
| 1096 | } |
| 1097 | |
Simon Glass | bab17cf | 2015-11-29 13:17:53 -0700 | [diff] [blame] | 1098 | u32 dm_pci_read_bar32(struct udevice *dev, int barnum) |
| 1099 | { |
| 1100 | u32 addr; |
| 1101 | int bar; |
| 1102 | |
| 1103 | bar = PCI_BASE_ADDRESS_0 + barnum * 4; |
| 1104 | dm_pci_read_config32(dev, bar, &addr); |
| 1105 | if (addr & PCI_BASE_ADDRESS_SPACE_IO) |
| 1106 | return addr & PCI_BASE_ADDRESS_IO_MASK; |
| 1107 | else |
| 1108 | return addr & PCI_BASE_ADDRESS_MEM_MASK; |
| 1109 | } |
| 1110 | |
Simon Glass | 9d731c8 | 2016-01-18 20:19:15 -0700 | [diff] [blame] | 1111 | void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr) |
| 1112 | { |
| 1113 | int bar; |
| 1114 | |
| 1115 | bar = PCI_BASE_ADDRESS_0 + barnum * 4; |
| 1116 | dm_pci_write_config32(dev, bar, addr); |
| 1117 | } |
| 1118 | |
Simon Glass | 21d1fe7 | 2015-11-29 13:18:03 -0700 | [diff] [blame] | 1119 | static int _dm_pci_bus_to_phys(struct udevice *ctlr, |
| 1120 | pci_addr_t bus_addr, unsigned long flags, |
| 1121 | unsigned long skip_mask, phys_addr_t *pa) |
| 1122 | { |
| 1123 | struct pci_controller *hose = dev_get_uclass_priv(ctlr); |
| 1124 | struct pci_region *res; |
| 1125 | int i; |
| 1126 | |
| 1127 | for (i = 0; i < hose->region_count; i++) { |
| 1128 | res = &hose->regions[i]; |
| 1129 | |
| 1130 | if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0) |
| 1131 | continue; |
| 1132 | |
| 1133 | if (res->flags & skip_mask) |
| 1134 | continue; |
| 1135 | |
| 1136 | if (bus_addr >= res->bus_start && |
| 1137 | (bus_addr - res->bus_start) < res->size) { |
| 1138 | *pa = (bus_addr - res->bus_start + res->phys_start); |
| 1139 | return 0; |
| 1140 | } |
| 1141 | } |
| 1142 | |
| 1143 | return 1; |
| 1144 | } |
| 1145 | |
| 1146 | phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t bus_addr, |
| 1147 | unsigned long flags) |
| 1148 | { |
| 1149 | phys_addr_t phys_addr = 0; |
| 1150 | struct udevice *ctlr; |
| 1151 | int ret; |
| 1152 | |
| 1153 | /* The root controller has the region information */ |
| 1154 | ctlr = pci_get_controller(dev); |
| 1155 | |
| 1156 | /* |
| 1157 | * if PCI_REGION_MEM is set we do a two pass search with preference |
| 1158 | * on matches that don't have PCI_REGION_SYS_MEMORY set |
| 1159 | */ |
| 1160 | if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) { |
| 1161 | ret = _dm_pci_bus_to_phys(ctlr, bus_addr, |
| 1162 | flags, PCI_REGION_SYS_MEMORY, |
| 1163 | &phys_addr); |
| 1164 | if (!ret) |
| 1165 | return phys_addr; |
| 1166 | } |
| 1167 | |
| 1168 | ret = _dm_pci_bus_to_phys(ctlr, bus_addr, flags, 0, &phys_addr); |
| 1169 | |
| 1170 | if (ret) |
| 1171 | puts("pci_hose_bus_to_phys: invalid physical address\n"); |
| 1172 | |
| 1173 | return phys_addr; |
| 1174 | } |
| 1175 | |
| 1176 | int _dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr, |
| 1177 | unsigned long flags, unsigned long skip_mask, |
| 1178 | pci_addr_t *ba) |
| 1179 | { |
| 1180 | struct pci_region *res; |
| 1181 | struct udevice *ctlr; |
| 1182 | pci_addr_t bus_addr; |
| 1183 | int i; |
| 1184 | struct pci_controller *hose; |
| 1185 | |
| 1186 | /* The root controller has the region information */ |
| 1187 | ctlr = pci_get_controller(dev); |
| 1188 | hose = dev_get_uclass_priv(ctlr); |
| 1189 | |
| 1190 | for (i = 0; i < hose->region_count; i++) { |
| 1191 | res = &hose->regions[i]; |
| 1192 | |
| 1193 | if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0) |
| 1194 | continue; |
| 1195 | |
| 1196 | if (res->flags & skip_mask) |
| 1197 | continue; |
| 1198 | |
| 1199 | bus_addr = phys_addr - res->phys_start + res->bus_start; |
| 1200 | |
| 1201 | if (bus_addr >= res->bus_start && |
| 1202 | (bus_addr - res->bus_start) < res->size) { |
| 1203 | *ba = bus_addr; |
| 1204 | return 0; |
| 1205 | } |
| 1206 | } |
| 1207 | |
| 1208 | return 1; |
| 1209 | } |
| 1210 | |
| 1211 | pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr, |
| 1212 | unsigned long flags) |
| 1213 | { |
| 1214 | pci_addr_t bus_addr = 0; |
| 1215 | int ret; |
| 1216 | |
| 1217 | /* |
| 1218 | * if PCI_REGION_MEM is set we do a two pass search with preference |
| 1219 | * on matches that don't have PCI_REGION_SYS_MEMORY set |
| 1220 | */ |
| 1221 | if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) { |
| 1222 | ret = _dm_pci_phys_to_bus(dev, phys_addr, flags, |
| 1223 | PCI_REGION_SYS_MEMORY, &bus_addr); |
| 1224 | if (!ret) |
| 1225 | return bus_addr; |
| 1226 | } |
| 1227 | |
| 1228 | ret = _dm_pci_phys_to_bus(dev, phys_addr, flags, 0, &bus_addr); |
| 1229 | |
| 1230 | if (ret) |
| 1231 | puts("pci_hose_phys_to_bus: invalid physical address\n"); |
| 1232 | |
| 1233 | return bus_addr; |
| 1234 | } |
| 1235 | |
| 1236 | void *dm_pci_map_bar(struct udevice *dev, int bar, int flags) |
| 1237 | { |
| 1238 | pci_addr_t pci_bus_addr; |
| 1239 | u32 bar_response; |
| 1240 | |
| 1241 | /* read BAR address */ |
| 1242 | dm_pci_read_config32(dev, bar, &bar_response); |
| 1243 | pci_bus_addr = (pci_addr_t)(bar_response & ~0xf); |
| 1244 | |
| 1245 | /* |
| 1246 | * Pass "0" as the length argument to pci_bus_to_virt. The arg |
| 1247 | * isn't actualy used on any platform because u-boot assumes a static |
| 1248 | * linear mapping. In the future, this could read the BAR size |
| 1249 | * and pass that as the size if needed. |
| 1250 | */ |
| 1251 | return dm_pci_bus_to_virt(dev, pci_bus_addr, flags, 0, MAP_NOCACHE); |
| 1252 | } |
| 1253 | |
Simon Glass | ff3e077 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 1254 | UCLASS_DRIVER(pci) = { |
| 1255 | .id = UCLASS_PCI, |
| 1256 | .name = "pci", |
Simon Glass | 2bb02e4 | 2015-05-10 21:08:06 -0600 | [diff] [blame] | 1257 | .flags = DM_UC_FLAG_SEQ_ALIAS, |
Simon Glass | ff3e077 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 1258 | .post_bind = pci_uclass_post_bind, |
| 1259 | .pre_probe = pci_uclass_pre_probe, |
| 1260 | .post_probe = pci_uclass_post_probe, |
| 1261 | .child_post_bind = pci_uclass_child_post_bind, |
| 1262 | .per_device_auto_alloc_size = sizeof(struct pci_controller), |
| 1263 | .per_child_platdata_auto_alloc_size = |
| 1264 | sizeof(struct pci_child_platdata), |
| 1265 | }; |
| 1266 | |
| 1267 | static const struct dm_pci_ops pci_bridge_ops = { |
| 1268 | .read_config = pci_bridge_read_config, |
| 1269 | .write_config = pci_bridge_write_config, |
| 1270 | }; |
| 1271 | |
| 1272 | static const struct udevice_id pci_bridge_ids[] = { |
| 1273 | { .compatible = "pci-bridge" }, |
| 1274 | { } |
| 1275 | }; |
| 1276 | |
| 1277 | U_BOOT_DRIVER(pci_bridge_drv) = { |
| 1278 | .name = "pci_bridge_drv", |
| 1279 | .id = UCLASS_PCI, |
| 1280 | .of_match = pci_bridge_ids, |
| 1281 | .ops = &pci_bridge_ops, |
| 1282 | }; |
| 1283 | |
| 1284 | UCLASS_DRIVER(pci_generic) = { |
| 1285 | .id = UCLASS_PCI_GENERIC, |
| 1286 | .name = "pci_generic", |
| 1287 | }; |
| 1288 | |
| 1289 | static const struct udevice_id pci_generic_ids[] = { |
| 1290 | { .compatible = "pci-generic" }, |
| 1291 | { } |
| 1292 | }; |
| 1293 | |
| 1294 | U_BOOT_DRIVER(pci_generic_drv) = { |
| 1295 | .name = "pci_generic_drv", |
| 1296 | .id = UCLASS_PCI_GENERIC, |
| 1297 | .of_match = pci_generic_ids, |
| 1298 | }; |
Stephen Warren | e578b92 | 2016-01-26 11:10:11 -0700 | [diff] [blame] | 1299 | |
| 1300 | void pci_init(void) |
| 1301 | { |
| 1302 | struct udevice *bus; |
| 1303 | |
| 1304 | /* |
| 1305 | * Enumerate all known controller devices. Enumeration has the side- |
| 1306 | * effect of probing them, so PCIe devices will be enumerated too. |
| 1307 | */ |
| 1308 | for (uclass_first_device(UCLASS_PCI, &bus); |
| 1309 | bus; |
| 1310 | uclass_next_device(&bus)) { |
| 1311 | ; |
| 1312 | } |
| 1313 | } |