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wdenk0f8c9762002-08-19 11:57:05 +00001/*
2 * (C) Copyright 2000
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
37#define CONFIG_ESTEEM192E 1 /* ...on a EST ESTEEM192E */
38
Wolfgang Denk2ae18242010-10-06 09:05:45 +020039#define CONFIG_SYS_TEXT_BASE 0x40000000
40
wdenk0f8c9762002-08-19 11:57:05 +000041#define CONFIG_FLASH_16BIT 1 /* Rom 16 bit data bus */
42
43#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
44#undef CONFIG_8xx_CONS_SMC2
45#undef CONFIG_8xx_CONS_NONE
46
47#define MPC8XX_FACT 10 /* Multiply by 10 */
48#define MPC8XX_XIN 4915200 /* 4.915200 MHz in - ??? - XXX */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020049#define CONFIG_SYS_PLPRCR_MF ((MPC8XX_FACT-1) << 20)
wdenk0f8c9762002-08-19 11:57:05 +000050#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT)) /* 49,152,000 Hz */
51
52#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ /* Force it - dont measure it */
53
54#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
55
56#define CONFIG_BAUDRATE 9600
57#if 0
58#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
59#else
60#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
61#endif
62#define CONFIG_BOOTCOMMAND "bootm 40030000" /* autoboot command */
63
64#define CONFIG_BOOTARGS "root=/dev/ram rw ramdisk=8192 " \
65 "ip=100.100.100.21:100.100.100.14:100.100.100.1:255.0.0.0 "
66/*
67 * Miscellaneous configurable options
68 */
69
70#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020071#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenk0f8c9762002-08-19 11:57:05 +000072
73#undef CONFIG_WATCHDOG /* watchdog disabled */
74
Jon Loeliger5d2ebe12007-07-09 21:16:53 -050075/*
76 * BOOTP options
77 */
78#define CONFIG_BOOTP_SUBNETMASK
79#define CONFIG_BOOTP_GATEWAY
80#define CONFIG_BOOTP_HOSTNAME
81#define CONFIG_BOOTP_BOOTPATH
82#define CONFIG_BOOTP_BOOTFILESIZE
83
wdenk0f8c9762002-08-19 11:57:05 +000084
Jon Loeligerdcaa7152007-07-07 20:56:05 -050085/*
86 * Command line configuration.
87 */
88#include <config_cmd_default.h>
89
wdenk0f8c9762002-08-19 11:57:05 +000090
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020091#define CONFIG_SYS_LONGHELP /* undef to save memory */
92#define CONFIG_SYS_PROMPT "BOOT: " /* Monitor Command Prompt */
93#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
94#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
95#define CONFIG_SYS_MAXARGS 8 /* max number of command args */
96#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk0f8c9762002-08-19 11:57:05 +000097
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020098#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
99#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenk0f8c9762002-08-19 11:57:05 +0000100
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenk0f8c9762002-08-19 11:57:05 +0000102
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200103#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenk0f8c9762002-08-19 11:57:05 +0000104
105
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200106#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenk0f8c9762002-08-19 11:57:05 +0000107
108
109/*
110 * Low Level Configuration Settings
111 * (address mappings, register initial values, etc.)
112 * You should know what you are doing if you make changes here.
113 */
114/*-----------------------------------------------------------------------
115 * Internal Memory Mapped Register
116 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117#define CONFIG_SYS_IMMR 0xFF000000
wdenk0f8c9762002-08-19 11:57:05 +0000118
119 /*-----------------------------------------------------------------------
120 * Definitions for initial stack pointer and data area (in DPRAM)
121 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200123#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200124#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk0f8c9762002-08-19 11:57:05 +0000126
127
wdenk0f8c9762002-08-19 11:57:05 +0000128/*-----------------------------------------------------------------------
129 * Start addresses for the final memory configuration
130 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenk0f8c9762002-08-19 11:57:05 +0000132 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133#define CONFIG_SYS_SDRAM_BASE 0x00000000
134#define CONFIG_SYS_FLASH_BASE 0x40000000
wdenk0f8c9762002-08-19 11:57:05 +0000135#ifdef DEBUG
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
wdenk0f8c9762002-08-19 11:57:05 +0000137#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
wdenk0f8c9762002-08-19 11:57:05 +0000139#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
141#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenk0f8c9762002-08-19 11:57:05 +0000142
143/*
144 * For booting Linux, the board info and command line data
145 * have to be in the first 8 MB of memory, since this is
146 * the maximum mapped by the Linux kernel during initialization.
147 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk0f8c9762002-08-19 11:57:05 +0000149/*-----------------------------------------------------------------------
150 * FLASH organization
151 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
153#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
wdenk0f8c9762002-08-19 11:57:05 +0000154
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
156#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenk0f8c9762002-08-19 11:57:05 +0000157
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200158#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200159#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
160#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
wdenk0f8c9762002-08-19 11:57:05 +0000161/*-----------------------------------------------------------------------
162 * Cache Configuration
163 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
wdenk0f8c9762002-08-19 11:57:05 +0000165
166/*-----------------------------------------------------------------------
167 * SYPCR - System Protection Control 11-9
168 * SYPCR can only be written once after reset!
169 *-----------------------------------------------------------------------
170 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
171 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200172#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
wdenk0f8c9762002-08-19 11:57:05 +0000173
174/*-----------------------------------------------------------------------
175 * SUMCR - SIU Module Configuration 11-6
176 *-----------------------------------------------------------------------
177 * PCMCIA config., multi-function pin tri-state
178 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) /* DBGC00 */
wdenk0f8c9762002-08-19 11:57:05 +0000180
181/*-----------------------------------------------------------------------
182 * TBSCR - Time Base Status and Control 11-26
183 *-----------------------------------------------------------------------
184 * Clear Reference Interrupt Status, Timebase freezing enabled
185 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
wdenk0f8c9762002-08-19 11:57:05 +0000187
188/* (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) */
189
190
191/*-----------------------------------------------------------------------
192 * PISCR - Periodic Interrupt Status and Control 11-31
193 *-----------------------------------------------------------------------
194 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
195 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
wdenk0f8c9762002-08-19 11:57:05 +0000197
198/*-----------------------------------------------------------------------
199 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
200 *-----------------------------------------------------------------------
201 * Reset PLL lock status sticky bit, timer expired status bit and timer
202 * interrupt status bit - leave PLL multiplication factor unchanged !
203 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204#define CONFIG_SYS_PLPRCR (CONFIG_SYS_PLPRCR_MF | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
wdenk0f8c9762002-08-19 11:57:05 +0000205
206/*-----------------------------------------------------------------------
207 * SCCR - System Clock and reset Control Register 15-27
208 *-----------------------------------------------------------------------
209 * Set clock output, timebase and RTC source and divider,
210 * power management and some other internal clocks
211 */
212#define SCCR_MASK SCCR_EBDF11
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_SYS_SCCR (SCCR_TBS | \
wdenk0f8c9762002-08-19 11:57:05 +0000214 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
215 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
216 SCCR_DFALCD00)
217
218/*-----------------------------------------------------------------------
219 * PCMCIA stuff
220 *-----------------------------------------------------------------------
221 *
222 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
224#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
225#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
226#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
227#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
228#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
229#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
230#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
wdenk0f8c9762002-08-19 11:57:05 +0000231
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232#define CONFIG_SYS_PCMCIA_INTERRUPT SIU_LEVEL6
wdenk0f8c9762002-08-19 11:57:05 +0000233
234/*-----------------------------------------------------------------------
235 *
236 *-----------------------------------------------------------------------
237 *
238 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200239/*#define CONFIG_SYS_DER 0x2002000F*/
240#define CONFIG_SYS_DER 0
241/*#define CONFIG_SYS_DER 0x02002000 */
wdenk0f8c9762002-08-19 11:57:05 +0000242
243
244/*
245 * Init Memory Controller:
246 *
247 * BR0/1 and OR0/1 (FLASH)
248 */
249
250#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
251#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
252
253/* used to re-map FLASH both when starting from SRAM or FLASH:
254 * restrict access enough to keep SRAM working (if any)
255 * but not too much to meddle with FLASH accesses
256 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200257#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
258#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
wdenk0f8c9762002-08-19 11:57:05 +0000259
260/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200261#define CONFIG_SYS_OR_TIMING_FLASH 0x00000160
wdenk0f8c9762002-08-19 11:57:05 +0000262 /*(OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \
263 OR_SCY_5_CLK | OR_EHTR) */
264
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200265#define CONFIG_SYS_OR0_REMAP 0x80000160 /*(CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)*/
266#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
267#define CONFIG_SYS_BR0_PRELIM ( FLASH_BASE0_PRELIM | 0x00000801 )
wdenk0f8c9762002-08-19 11:57:05 +0000268
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200269#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
270#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
271#define CONFIG_SYS_BR1_PRELIM ( FLASH_BASE1_PRELIM | 0x00000801 )
wdenk0f8c9762002-08-19 11:57:05 +0000272
273/*
274 * BR2/3 and OR2/3 (SDRAM)
275 *
276 */
277#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
278#define SDRAM_BASE3_PRELIM 0x04000000 /* SDRAM bank #1 */
279#define SDRAM_MAX_SIZE 0x02000000 /* max 32 MB per bank */
280
281/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200282#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
wdenk0f8c9762002-08-19 11:57:05 +0000283
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200284#define CONFIG_SYS_OR2_PRELIM 0xFC000E00
285#define CONFIG_SYS_BR2_PRELIM (SDRAM_BASE2_PRELIM | 0x00000081)
wdenk0f8c9762002-08-19 11:57:05 +0000286
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200287#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
288#define CONFIG_SYS_BR3_PRELIM (SDRAM_BASE3_PRELIM | 0x00000081)
wdenk0f8c9762002-08-19 11:57:05 +0000289
290
291/*
292 * Memory Periodic Timer Prescaler
293 */
294
295/* periodic timer for refresh */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200296#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */
wdenk0f8c9762002-08-19 11:57:05 +0000297
298/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200299#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
300#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
wdenk0f8c9762002-08-19 11:57:05 +0000301
302/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200303#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
304#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
wdenk0f8c9762002-08-19 11:57:05 +0000305
306/*
307 * MAMR settings for SDRAM
308 */
309
310/* 8 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200311#define CONFIG_SYS_MAMR_8COL 0x18803112
312#define CONFIG_SYS_MAMR_9COL 0x18803112 /* same as 8 column because its just easier to port with*/
wdenk0f8c9762002-08-19 11:57:05 +0000313
wdenk0f8c9762002-08-19 11:57:05 +0000314#endif /* __CONFIG_H */