blob: d6783db2c25c1b9fe6cc31722e7e8b588e2eae5a [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Wang Huanc8a7d9d2014-09-05 13:52:45 +08002/*
3 * Copyright 2014 Freescale Semiconductor, Inc.
Biwen Li9ebde882019-12-31 15:33:44 +08004 * Copyright 2019 NXP
Wang Huanc8a7d9d2014-09-05 13:52:45 +08005 */
6
7#ifndef __CONFIG_H
8#define __CONFIG_H
9
Hongbo Zhang32886282016-07-21 18:09:39 +080010#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
11
Gong Qianyu18fb0e32015-10-26 19:47:42 +080012#define CONFIG_SYS_FSL_CLK
Wang Huanc8a7d9d2014-09-05 13:52:45 +080013
Wang Huanc8a7d9d2014-09-05 13:52:45 +080014#define CONFIG_SKIP_LOWLEVEL_INIT
Tang Yuantian99e1bd42015-05-14 17:20:28 +080015#define CONFIG_DEEP_SLEEP
Wang Huanc8a7d9d2014-09-05 13:52:45 +080016
17/*
18 * Size of malloc() pool
19 */
20#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
21
22#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
23#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
24
Wang Huanc8a7d9d2014-09-05 13:52:45 +080025#define CONFIG_SYS_CLK_FREQ 100000000
26#define CONFIG_DDR_CLK_FREQ 100000000
27
York Suna88cc3b2015-04-29 10:35:35 -070028#define DDR_SDRAM_CFG 0x470c0008
29#define DDR_CS0_BNDS 0x008000bf
30#define DDR_CS0_CONFIG 0x80014302
31#define DDR_TIMING_CFG_0 0x50550004
32#define DDR_TIMING_CFG_1 0xbcb38c56
33#define DDR_TIMING_CFG_2 0x0040d120
34#define DDR_TIMING_CFG_3 0x010e1000
35#define DDR_TIMING_CFG_4 0x00000001
36#define DDR_TIMING_CFG_5 0x03401400
37#define DDR_SDRAM_CFG_2 0x00401010
38#define DDR_SDRAM_MODE 0x00061c60
39#define DDR_SDRAM_MODE_2 0x00180000
40#define DDR_SDRAM_INTERVAL 0x18600618
41#define DDR_DDR_WRLVL_CNTL 0x8655f605
42#define DDR_DDR_WRLVL_CNTL_2 0x05060607
43#define DDR_DDR_WRLVL_CNTL_3 0x05050505
44#define DDR_DDR_CDR1 0x80040000
45#define DDR_DDR_CDR2 0x00000001
46#define DDR_SDRAM_CLK_CNTL 0x02000000
47#define DDR_DDR_ZQ_CNTL 0x89080600
48#define DDR_CS0_CONFIG_2 0
49#define DDR_SDRAM_CFG_MEM_EN 0x80000000
Tang Yuantian99e1bd42015-05-14 17:20:28 +080050#define SDRAM_CFG2_D_INIT 0x00000010
51#define DDR_CDR2_VREF_TRAIN_EN 0x00000080
52#define SDRAM_CFG2_FRC_SR 0x80000000
53#define SDRAM_CFG_BI 0x00000001
York Suna88cc3b2015-04-29 10:35:35 -070054
Alison Wang8415bb62014-12-03 15:00:48 +080055#ifdef CONFIG_RAMBOOT_PBL
56#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg
57#endif
58
59#ifdef CONFIG_SD_BOOT
Alison Wang947cee12015-10-15 17:54:40 +080060#ifdef CONFIG_SD_BOOT_QSPI
61#define CONFIG_SYS_FSL_PBL_RCW \
62 board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg
63#else
64#define CONFIG_SYS_FSL_PBL_RCW \
65 board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg
66#endif
Sumit Garge7e720c2016-06-14 13:52:40 -040067
Udit Agarwal5536c3c2019-11-07 16:11:32 +000068#ifdef CONFIG_NXP_ESBC
Sumit Garge7e720c2016-06-14 13:52:40 -040069/*
70 * HDR would be appended at end of image and copied to DDR along
71 * with U-Boot image.
72 */
Semen Protsenko693d4c92016-11-16 19:19:06 +020073#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
Udit Agarwal5536c3c2019-11-07 16:11:32 +000074#endif /* ifdef CONFIG_NXP_ESBC */
Alison Wang8415bb62014-12-03 15:00:48 +080075
Alison Wang8415bb62014-12-03 15:00:48 +080076#define CONFIG_SPL_MAX_SIZE 0x1a000
77#define CONFIG_SPL_STACK 0x1001d000
78#define CONFIG_SPL_PAD_TO 0x1c000
Alison Wang8415bb62014-12-03 15:00:48 +080079
Tang Yuantian99e1bd42015-05-14 17:20:28 +080080#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
81 CONFIG_SYS_MONITOR_LEN)
Alison Wang8415bb62014-12-03 15:00:48 +080082#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
83#define CONFIG_SPL_BSS_START_ADDR 0x80100000
84#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
Sumit Garge7e720c2016-06-14 13:52:40 -040085
86#ifdef CONFIG_U_BOOT_HDR_SIZE
87/*
88 * HDR would be appended at end of image and copied to DDR along
89 * with U-Boot image. Here u-boot max. size is 512K. So if binary
90 * size increases then increase this size in case of secure boot as
91 * it uses raw u-boot image instead of fit image.
92 */
Vinitha Pillai9b6639f2017-02-01 18:28:53 +053093#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
Sumit Garge7e720c2016-06-14 13:52:40 -040094#else
Vinitha Pillai9b6639f2017-02-01 18:28:53 +053095#define CONFIG_SYS_MONITOR_LEN 0x100000
Sumit Garge7e720c2016-06-14 13:52:40 -040096#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
Alison Wang8415bb62014-12-03 15:00:48 +080097#endif
98
Wang Huanc8a7d9d2014-09-05 13:52:45 +080099#define PHYS_SDRAM 0x80000000
100#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
101
102#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
103#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
104
Alison Wang15809702019-03-06 14:49:14 +0800105#define CONFIG_CHIP_SELECTS_PER_CTRL 4
106
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800107/*
108 * IFC Definitions
109 */
Alison Wang947cee12015-10-15 17:54:40 +0800110#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800111#define CONFIG_FSL_IFC
112#define CONFIG_SYS_FLASH_BASE 0x60000000
113#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
114
115#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
116#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
117 CSPR_PORT_SIZE_16 | \
118 CSPR_MSEL_NOR | \
119 CSPR_V)
120#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
121
122/* NOR Flash Timing Params */
123#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
124 CSOR_NOR_TRHZ_80)
125#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
126 FTIM0_NOR_TEADC(0x5) | \
127 FTIM0_NOR_TAVDS(0x0) | \
128 FTIM0_NOR_TEAHC(0x5))
129#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
130 FTIM1_NOR_TRAD_NOR(0x1A) | \
131 FTIM1_NOR_TSEQRAD_NOR(0x13))
132#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
133 FTIM2_NOR_TCH(0x4) | \
134 FTIM2_NOR_TWP(0x1c) | \
135 FTIM2_NOR_TWPH(0x0e))
136#define CONFIG_SYS_NOR_FTIM3 0
137
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800138#define CONFIG_SYS_FLASH_QUIET_TEST
139#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
140
141#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
142#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
143#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
144#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
145
146#define CONFIG_SYS_FLASH_EMPTY_INFO
147#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
148
149#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
Yuan Yao272c5262014-10-17 15:26:34 +0800150#define CONFIG_SYS_WRITE_SWAPPED_DATA
Alison Wangd612f0a2014-12-09 17:38:02 +0800151#endif
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800152
153/* CPLD */
154
155#define CONFIG_SYS_CPLD_BASE 0x7fb00000
156#define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
157
158#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
159#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
160 CSPR_PORT_SIZE_8 | \
161 CSPR_MSEL_GPCM | \
162 CSPR_V)
163#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
164#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
165 CSOR_NOR_NOR_MODE_AVD_NOR | \
166 CSOR_NOR_TRHZ_80)
167
168/* CPLD Timing parameters for IFC GPCM */
169#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \
170 FTIM0_GPCM_TEADC(0xf) | \
171 FTIM0_GPCM_TEAHC(0xf))
172#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
173 FTIM1_GPCM_TRAD(0x3f))
174#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
175 FTIM2_GPCM_TCH(0xf) | \
176 FTIM2_GPCM_TWP(0xff))
177#define CONFIG_SYS_FPGA_FTIM3 0x0
178#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
179#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
180#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
181#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
182#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
183#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
184#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
185#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
186#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT
187#define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR
188#define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK
189#define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR
190#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0
191#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1
192#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2
193#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3
194
195/*
196 * Serial Port
197 */
Alison Wang55d53ab2015-01-04 15:30:59 +0800198#ifdef CONFIG_LPUART
Alison Wang55d53ab2015-01-04 15:30:59 +0800199#define CONFIG_LPUART_32B_REG
200#else
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800201#define CONFIG_SYS_NS16550_SERIAL
Bin Mengf833cd62016-01-13 19:38:59 -0800202#ifndef CONFIG_DM_SERIAL
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800203#define CONFIG_SYS_NS16550_REG_SIZE 1
Bin Mengf833cd62016-01-13 19:38:59 -0800204#endif
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800205#define CONFIG_SYS_NS16550_CLK get_serial_clock()
Alison Wang55d53ab2015-01-04 15:30:59 +0800206#endif
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800207
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800208/*
209 * I2C
210 */
Igor Opaniuk2147a162021-02-09 13:52:45 +0200211#if !CONFIG_IS_ENABLED(DM_I2C)
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800212#define CONFIG_SYS_I2C
Biwen Li9ebde882019-12-31 15:33:44 +0800213#else
214#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
215#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
216#endif
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800217#define CONFIG_SYS_I2C_MXC
Albert ARIBAUD \\(3ADEV\\)03544c62015-09-21 22:43:38 +0200218#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
219#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
York Sunf8cb1012015-03-20 10:20:40 -0700220#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800221
Biwen Li7c1f0952021-02-05 19:02:02 +0800222/* GPIO */
223#ifdef CONFIG_DM_GPIO
224#ifndef CONFIG_MPC8XXX_GPIO
225#define CONFIG_MPC8XXX_GPIO
226#endif
227#endif
228
Alison Wang5175a282014-10-17 15:26:35 +0800229/* EEPROM */
Alison Wang5175a282014-10-17 15:26:35 +0800230#define CONFIG_ID_EEPROM
231#define CONFIG_SYS_I2C_EEPROM_NXID
232#define CONFIG_SYS_EEPROM_BUS_NUM 1
233#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
234#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
235#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
236#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
Alison Wang5175a282014-10-17 15:26:35 +0800237
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800238/*
239 * MMC
240 */
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800241
242/*
Wang Huanb4ecc8c2014-09-05 13:52:50 +0800243 * Video
244 */
Sanchayan Maityb215fb32017-04-11 11:12:09 +0530245#ifdef CONFIG_VIDEO_FSL_DCU_FB
Wang Huanb4ecc8c2014-09-05 13:52:50 +0800246#define CONFIG_VIDEO_LOGO
247#define CONFIG_VIDEO_BMP_LOGO
248
249#define CONFIG_FSL_DCU_SII9022A
250#define CONFIG_SYS_I2C_DVI_BUS_NUM 1
251#define CONFIG_SYS_I2C_DVI_ADDR 0x39
252#endif
253
254/*
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800255 * eTSEC
256 */
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800257
258#ifdef CONFIG_TSEC_ENET
Bin Mengf588b4d2019-07-19 00:29:59 +0300259#define CONFIG_ETHPRIME "ethernet@2d10000"
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800260#endif
261
Minghuan Lianda419022014-10-31 13:43:44 +0800262/* PCIe */
Robert P. J. Dayb38eaec2016-05-03 19:52:49 -0400263#define CONFIG_PCIE1 /* PCIE controller 1 */
264#define CONFIG_PCIE2 /* PCIE controller 2 */
Minghuan Lianda419022014-10-31 13:43:44 +0800265
Minghuan Lian180b8682015-01-21 17:29:19 +0800266#ifdef CONFIG_PCI
Minghuan Lian180b8682015-01-21 17:29:19 +0800267#define CONFIG_PCI_SCAN_SHOW
Minghuan Lian180b8682015-01-21 17:29:19 +0800268#endif
269
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800270#define CONFIG_CMDLINE_TAG
Alison Wang8415bb62014-12-03 15:00:48 +0800271
Xiubo Li1a2826f2014-11-21 17:40:57 +0800272#define CONFIG_PEN_ADDR_BIG_ENDIAN
Mingkai Hu435acd82015-10-26 19:47:41 +0800273#define CONFIG_LAYERSCAPE_NS_ACCESS
Xiubo Li1a2826f2014-11-21 17:40:57 +0800274#define CONFIG_SMP_PEN_ADDR 0x01ee0200
Andre Przywarae4916e82017-02-16 01:20:19 +0000275#define COUNTER_FREQUENCY 12500000
Xiubo Li1a2826f2014-11-21 17:40:57 +0800276
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800277#define CONFIG_HWCONFIG
Zhuoyu Zhang03c22442015-08-17 18:55:12 +0800278#define HWCONFIG_BUFFER_SIZE 256
279
280#define CONFIG_FSL_DEVICE_DISABLE
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800281
Alison Wanga65d7402017-05-26 15:46:15 +0800282#define BOOT_TARGET_DEVICES(func) \
283 func(MMC, mmc, 0) \
Yunfeng Dingd2c49aa2019-02-19 14:44:04 +0800284 func(USB, usb, 0) \
285 func(DHCP, dhcp, na)
Alison Wanga65d7402017-05-26 15:46:15 +0800286#include <config_distro_bootcmd.h>
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800287
Alison Wang55d53ab2015-01-04 15:30:59 +0800288#ifdef CONFIG_LPUART
289#define CONFIG_EXTRA_ENV_SETTINGS \
Alison Wang33c3dfd2020-04-23 22:37:34 +0800290 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200 " \
291 "cma=64M@0x0-0xb0000000\0" \
Alison Wang7ff71662015-10-26 14:08:28 +0800292 "initrd_high=0xffffffff\0" \
Alison Wanga65d7402017-05-26 15:46:15 +0800293 "fdt_addr=0x64f00000\0" \
294 "kernel_addr=0x65000000\0" \
295 "scriptaddr=0x80000000\0" \
Sumit Gargb8ae6792017-06-06 20:51:31 +0530296 "scripthdraddr=0x80080000\0" \
Alison Wanga65d7402017-05-26 15:46:15 +0800297 "fdtheader_addr_r=0x80100000\0" \
298 "kernelheader_addr_r=0x80200000\0" \
299 "kernel_addr_r=0x81000000\0" \
300 "fdt_addr_r=0x90000000\0" \
301 "ramdisk_addr_r=0xa0000000\0" \
302 "load_addr=0xa0000000\0" \
303 "kernel_size=0x2800000\0" \
Shengzhou Liu397a1732017-11-09 17:57:57 +0800304 "kernel_addr_sd=0x8000\0" \
305 "kernel_size_sd=0x14000\0" \
Alison Wangfeb8fa22020-01-21 07:33:01 +0000306 "othbootargs=cma=64M@0x0-0xb0000000\0" \
Alison Wanga65d7402017-05-26 15:46:15 +0800307 BOOTENV \
308 "boot_scripts=ls1021atwr_boot.scr\0" \
Sumit Gargb8ae6792017-06-06 20:51:31 +0530309 "boot_script_hdr=hdr_ls1021atwr_bs.out\0" \
Alison Wanga65d7402017-05-26 15:46:15 +0800310 "scan_dev_for_boot_part=" \
311 "part list ${devtype} ${devnum} devplist; " \
312 "env exists devplist || setenv devplist 1; " \
313 "for distro_bootpart in ${devplist}; do " \
314 "if fstype ${devtype} " \
315 "${devnum}:${distro_bootpart} " \
316 "bootfstype; then " \
317 "run scan_dev_for_boot; " \
318 "fi; " \
319 "done\0" \
Sumit Gargb8ae6792017-06-06 20:51:31 +0530320 "scan_dev_for_boot=" \
321 "echo Scanning ${devtype} " \
322 "${devnum}:${distro_bootpart}...; " \
323 "for prefix in ${boot_prefixes}; do " \
324 "run scan_dev_for_scripts; " \
325 "done;" \
326 "\0" \
327 "boot_a_script=" \
328 "load ${devtype} ${devnum}:${distro_bootpart} " \
329 "${scriptaddr} ${prefix}${script}; " \
330 "env exists secureboot && load ${devtype} " \
331 "${devnum}:${distro_bootpart} " \
Vinitha V Pillai78c58082019-04-23 05:52:17 +0000332 "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
333 "env exists secureboot " \
Sumit Gargb8ae6792017-06-06 20:51:31 +0530334 "&& esbc_validate ${scripthdraddr};" \
335 "source ${scriptaddr}\0" \
Alison Wanga65d7402017-05-26 15:46:15 +0800336 "installer=load mmc 0:2 $load_addr " \
337 "/flex_installer_arm32.itb; " \
338 "bootm $load_addr#ls1021atwr\0" \
339 "qspi_bootcmd=echo Trying load from qspi..;" \
340 "sf probe && sf read $load_addr " \
341 "$kernel_addr $kernel_size && bootm $load_addr#$board\0" \
342 "nor_bootcmd=echo Trying load from nor..;" \
343 "cp.b $kernel_addr $load_addr " \
344 "$kernel_size && bootm $load_addr#$board\0"
Alison Wang55d53ab2015-01-04 15:30:59 +0800345#else
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800346#define CONFIG_EXTRA_ENV_SETTINGS \
Alison Wang33c3dfd2020-04-23 22:37:34 +0800347 "bootargs=root=/dev/ram0 rw console=ttyS0,115200 " \
348 "cma=64M@0x0-0xb0000000\0" \
Alison Wang7ff71662015-10-26 14:08:28 +0800349 "initrd_high=0xffffffff\0" \
Alison Wanga65d7402017-05-26 15:46:15 +0800350 "fdt_addr=0x64f00000\0" \
Vinitha Pillai-B572239b457cc2017-11-22 10:38:35 +0530351 "kernel_addr=0x61000000\0" \
352 "kernelheader_addr=0x60800000\0" \
Alison Wanga65d7402017-05-26 15:46:15 +0800353 "scriptaddr=0x80000000\0" \
Sumit Gargb8ae6792017-06-06 20:51:31 +0530354 "scripthdraddr=0x80080000\0" \
Alison Wanga65d7402017-05-26 15:46:15 +0800355 "fdtheader_addr_r=0x80100000\0" \
356 "kernelheader_addr_r=0x80200000\0" \
357 "kernel_addr_r=0x81000000\0" \
Vinitha Pillai-B572239b457cc2017-11-22 10:38:35 +0530358 "kernelheader_size=0x40000\0" \
Alison Wanga65d7402017-05-26 15:46:15 +0800359 "fdt_addr_r=0x90000000\0" \
360 "ramdisk_addr_r=0xa0000000\0" \
361 "load_addr=0xa0000000\0" \
362 "kernel_size=0x2800000\0" \
Vinitha Pillai-B572239b457cc2017-11-22 10:38:35 +0530363 "kernel_addr_sd=0x8000\0" \
364 "kernel_size_sd=0x14000\0" \
365 "kernelhdr_addr_sd=0x4000\0" \
366 "kernelhdr_size_sd=0x10\0" \
Alison Wangfeb8fa22020-01-21 07:33:01 +0000367 "othbootargs=cma=64M@0x0-0xb0000000\0" \
Alison Wanga65d7402017-05-26 15:46:15 +0800368 BOOTENV \
369 "boot_scripts=ls1021atwr_boot.scr\0" \
Sumit Gargb8ae6792017-06-06 20:51:31 +0530370 "boot_script_hdr=hdr_ls1021atwr_bs.out\0" \
Alison Wanga65d7402017-05-26 15:46:15 +0800371 "scan_dev_for_boot_part=" \
372 "part list ${devtype} ${devnum} devplist; " \
373 "env exists devplist || setenv devplist 1; " \
374 "for distro_bootpart in ${devplist}; do " \
375 "if fstype ${devtype} " \
376 "${devnum}:${distro_bootpart} " \
377 "bootfstype; then " \
378 "run scan_dev_for_boot; " \
379 "fi; " \
380 "done\0" \
Sumit Gargb8ae6792017-06-06 20:51:31 +0530381 "scan_dev_for_boot=" \
382 "echo Scanning ${devtype} " \
383 "${devnum}:${distro_bootpart}...; " \
384 "for prefix in ${boot_prefixes}; do " \
385 "run scan_dev_for_scripts; " \
386 "done;" \
387 "\0" \
388 "boot_a_script=" \
389 "load ${devtype} ${devnum}:${distro_bootpart} " \
390 "${scriptaddr} ${prefix}${script}; " \
391 "env exists secureboot && load ${devtype} " \
392 "${devnum}:${distro_bootpart} " \
393 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
394 "&& esbc_validate ${scripthdraddr};" \
395 "source ${scriptaddr}\0" \
Alison Wanga65d7402017-05-26 15:46:15 +0800396 "qspi_bootcmd=echo Trying load from qspi..;" \
397 "sf probe && sf read $load_addr " \
Vinitha Pillai-B572239b457cc2017-11-22 10:38:35 +0530398 "$kernel_addr $kernel_size; env exists secureboot " \
399 "&& sf read $kernelheader_addr_r $kernelheader_addr " \
400 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
401 "bootm $load_addr#$board\0" \
Alison Wanga65d7402017-05-26 15:46:15 +0800402 "nor_bootcmd=echo Trying load from nor..;" \
403 "cp.b $kernel_addr $load_addr " \
Vinitha Pillai-B572239b457cc2017-11-22 10:38:35 +0530404 "$kernel_size; env exists secureboot " \
405 "&& cp.b $kernelheader_addr $kernelheader_addr_r " \
406 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
407 "bootm $load_addr#$board\0" \
Shengzhou Liu397a1732017-11-09 17:57:57 +0800408 "sd_bootcmd=echo Trying load from SD ..;" \
409 "mmcinfo && mmc read $load_addr " \
410 "$kernel_addr_sd $kernel_size_sd && " \
Vinitha Pillai-B572239b457cc2017-11-22 10:38:35 +0530411 "env exists secureboot && mmc read $kernelheader_addr_r " \
412 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
413 " && esbc_validate ${kernelheader_addr_r};" \
Shengzhou Liu397a1732017-11-09 17:57:57 +0800414 "bootm $load_addr#$board\0"
Alison Wang55d53ab2015-01-04 15:30:59 +0800415#endif
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800416
Alison Wanga65d7402017-05-26 15:46:15 +0800417#undef CONFIG_BOOTCOMMAND
418#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
Vladimir Olteanc40e65e2019-07-19 00:30:00 +0300419#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
Vinitha Pillai-B572239b457cc2017-11-22 10:38:35 +0530420 "env exists secureboot && esbc_halt"
Shengzhou Liu397a1732017-11-09 17:57:57 +0800421#elif defined(CONFIG_SD_BOOT)
Vinitha Pillai-B572239b457cc2017-11-22 10:38:35 +0530422#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \
423 "env exists secureboot && esbc_halt;"
Alison Wanga65d7402017-05-26 15:46:15 +0800424#else
Vinitha Pillai-B572239b457cc2017-11-22 10:38:35 +0530425#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd;" \
426 "env exists secureboot && esbc_halt;"
Alison Wanga65d7402017-05-26 15:46:15 +0800427#endif
428
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800429/*
430 * Miscellaneous configurable options
431 */
Alison Wangc463eeb2020-02-03 15:25:19 +0800432#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800433
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800434#define CONFIG_SYS_LOAD_ADDR 0x82000000
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800435
Xiubo Li660673a2014-11-21 17:40:59 +0800436#define CONFIG_LS102XA_STREAM_ID
437
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800438#define CONFIG_SYS_INIT_SP_OFFSET \
439 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
440#define CONFIG_SYS_INIT_SP_ADDR \
441 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
442
Alison Wang8415bb62014-12-03 15:00:48 +0800443#ifdef CONFIG_SPL_BUILD
444#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
445#else
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800446#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Alison Wang8415bb62014-12-03 15:00:48 +0800447#endif
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800448
Alison Wang615bfce2017-05-16 10:45:57 +0800449#define CONFIG_SYS_QE_FW_ADDR 0x60940000
Zhao Qiangeaa859e2014-09-26 16:25:33 +0800450
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800451/*
452 * Environment
453 */
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800454
Aneesh Bansalef6c55a2016-01-22 16:37:22 +0530455#include <asm/fsl_secure_boot.h>
Alison Wangcc7b8b92016-01-15 15:29:32 +0800456#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
Ruchika Gupta4ba4a092014-10-15 11:39:06 +0530457
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800458#endif