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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Tom Warrenf01b6312012-12-11 13:34:18 +00002/*
3 * (C) Copyright 2010-2012
4 * NVIDIA Corporation <www.nvidia.com>
Tom Warrenf01b6312012-12-11 13:34:18 +00005 */
6
Tom Warrenbfcf46d2013-02-26 12:18:48 +00007#ifndef _TEGRA_COMMON_H_
8#define _TEGRA_COMMON_H_
Alexey Brodkin1ace4022014-02-26 17:47:58 +04009#include <linux/sizes.h>
Tom Warrenf01b6312012-12-11 13:34:18 +000010#include <linux/stringify.h>
11
12/*
13 * High Level Configuration Options
14 */
Tom Warrenf01b6312012-12-11 13:34:18 +000015#define CONFIG_SYS_L2CACHE_OFF /* No L2 cache */
16
Tom Warrenf01b6312012-12-11 13:34:18 +000017#include <asm/arch/tegra.h> /* get chip and board defs */
18
Thierry Redingf41f0a12015-07-28 11:35:54 +020019/* Use the Tegra US timer on ARMv7, but the architected timer on ARMv8. */
20#ifndef CONFIG_ARM64
Rob Herring31df9892013-10-04 10:22:47 -050021#define CONFIG_SYS_TIMER_RATE 1000000
22#define CONFIG_SYS_TIMER_COUNTER NV_PA_TMRUS_BASE
Thierry Redingf41f0a12015-07-28 11:35:54 +020023#endif
Rob Herring31df9892013-10-04 10:22:47 -050024
Tom Warrenf01b6312012-12-11 13:34:18 +000025#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
Tom Warrenf01b6312012-12-11 13:34:18 +000026
27/* Environment */
Tom Warrenf01b6312012-12-11 13:34:18 +000028
29/*
Tom Warrenbfcf46d2013-02-26 12:18:48 +000030 * NS16550 Configuration
Tom Warrenf01b6312012-12-11 13:34:18 +000031 */
Thomas Chou18746262015-11-19 21:48:11 +080032#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
Tom Warrenf01b6312012-12-11 13:34:18 +000033
34/*
Stephen Warrenf1756032014-04-18 10:56:11 -060035 * Common HW configuration.
36 * If this varies between SoCs later, move to tegraNN-common.h
37 * Note: This is number of devices, not max device ID.
38 */
39#define CONFIG_SYS_MMC_MAX_DEVICE 4
40
Tom Warrenf01b6312012-12-11 13:34:18 +000041/*
Tom Warrenf01b6312012-12-11 13:34:18 +000042 * Increasing the size of the IO buffer as default nfsargs size is more
43 * than 256 and so it is not possible to edit it
44 */
Bryan Wu64a4fe72016-09-01 23:49:57 +000045#define CONFIG_SYS_CBSIZE (1024 * 2) /* Console I/O Buffer Size */
Tom Warrenf01b6312012-12-11 13:34:18 +000046/* Print Buffer Size */
Bryan Wu64a4fe72016-09-01 23:49:57 +000047#define CONFIG_SYS_MAXARGS 64 /* max number of command args */
48
Tom Warrenf01b6312012-12-11 13:34:18 +000049/* Boot Argument Buffer Size */
50#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
51
Peter Robinson632fb972020-04-02 00:28:54 +010052#ifdef CONFIG_ARM64
53#define FDTFILE "nvidia/" CONFIG_DEFAULT_DEVICE_TREE ".dtb"
54#else
55#define FDTFILE CONFIG_DEFAULT_DEVICE_TREE ".dtb"
56#endif
57
Tom Warrenf01b6312012-12-11 13:34:18 +000058/*-----------------------------------------------------------------------
59 * Physical Memory Map
60 */
Tom Warrenf01b6312012-12-11 13:34:18 +000061#define PHYS_SDRAM_1 NV_PA_SDRC_CS0
62#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */
63
Tom Warrenf01b6312012-12-11 13:34:18 +000064#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
65
66#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */
67
Stephen Warrenf0975322017-12-19 18:30:37 -070068#ifndef CONFIG_ARM64
Tom Warrenf01b6312012-12-11 13:34:18 +000069#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE
70#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN
71#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
72 CONFIG_SYS_INIT_RAM_SIZE - \
73 GENERATED_GBL_DATA_SIZE)
Stephen Warrenf0975322017-12-19 18:30:37 -070074#endif
Tom Warrenf01b6312012-12-11 13:34:18 +000075
Stephen Warren0d1bd152017-12-19 18:30:35 -070076#ifndef CONFIG_ARM64
Tom Warrenf01b6312012-12-11 13:34:18 +000077/* Defines for SPL */
Albert ARIBAUD6ebc3462013-04-12 05:14:30 +000078#define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_TEXT_BASE - \
Tom Warrenf01b6312012-12-11 13:34:18 +000079 CONFIG_SPL_TEXT_BASE)
80#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000
Stephen Warren0d1bd152017-12-19 18:30:35 -070081#endif
Tom Warrenf01b6312012-12-11 13:34:18 +000082
Tom Warrenf01b6312012-12-11 13:34:18 +000083#endif /* _TEGRA_COMMON_H_ */