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wdenk012771d2002-03-08 21:31:05 +00001/* gt64260R.h - GT64260 Internal registers definition file */
2
3/* Copyright - Galileo technology. */
4
5#ifndef __INCgt64260rh
6#define __INCgt64260rh
7
8#ifndef GT64260
9#define GT64260
10#endif
11
12/* CPU MASTER CONTROL REGISTER */
13#define CPU_CONFIGURATION 0x0
14#define CPU_MASTER_CONTROL 0x160
15
16/****************************************/
Wolfgang Denk53677ef2008-05-20 16:00:29 +020017/* Processor Address Space */
wdenk012771d2002-03-08 21:31:05 +000018/****************************************/
19
20/* Sdram's BAR'S */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020021#define SCS_0_LOW_DECODE_ADDRESS 0x008
22#define SCS_0_HIGH_DECODE_ADDRESS 0x010
23#define SCS_1_LOW_DECODE_ADDRESS 0x208
24#define SCS_1_HIGH_DECODE_ADDRESS 0x210
25#define SCS_2_LOW_DECODE_ADDRESS 0x018
26#define SCS_2_HIGH_DECODE_ADDRESS 0x020
27#define SCS_3_LOW_DECODE_ADDRESS 0x218
28#define SCS_3_HIGH_DECODE_ADDRESS 0x220
wdenk012771d2002-03-08 21:31:05 +000029/* Devices BAR'S */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020030#define CS_0_LOW_DECODE_ADDRESS 0x028
31#define CS_0_HIGH_DECODE_ADDRESS 0x030
32#define CS_1_LOW_DECODE_ADDRESS 0x228
33#define CS_1_HIGH_DECODE_ADDRESS 0x230
34#define CS_2_LOW_DECODE_ADDRESS 0x248
35#define CS_2_HIGH_DECODE_ADDRESS 0x250
36#define CS_3_LOW_DECODE_ADDRESS 0x038
37#define CS_3_HIGH_DECODE_ADDRESS 0x040
38#define BOOTCS_LOW_DECODE_ADDRESS 0x238
39#define BOOTCS_HIGH_DECODE_ADDRESS 0x240
wdenk012771d2002-03-08 21:31:05 +000040
Wolfgang Denk53677ef2008-05-20 16:00:29 +020041#define PCI_0I_O_LOW_DECODE_ADDRESS 0x048
42#define PCI_0I_O_HIGH_DECODE_ADDRESS 0x050
43#define PCI_0MEMORY0_LOW_DECODE_ADDRESS 0x058
44#define PCI_0MEMORY0_HIGH_DECODE_ADDRESS 0x060
45#define PCI_0MEMORY1_LOW_DECODE_ADDRESS 0x080
46#define PCI_0MEMORY1_HIGH_DECODE_ADDRESS 0x088
47#define PCI_0MEMORY2_LOW_DECODE_ADDRESS 0x258
48#define PCI_0MEMORY2_HIGH_DECODE_ADDRESS 0x260
49#define PCI_0MEMORY3_LOW_DECODE_ADDRESS 0x280
50#define PCI_0MEMORY3_HIGH_DECODE_ADDRESS 0x288
wdenk012771d2002-03-08 21:31:05 +000051
Wolfgang Denk53677ef2008-05-20 16:00:29 +020052#define PCI_1I_O_LOW_DECODE_ADDRESS 0x090
53#define PCI_1I_O_HIGH_DECODE_ADDRESS 0x098
54#define PCI_1MEMORY0_LOW_DECODE_ADDRESS 0x0a0
55#define PCI_1MEMORY0_HIGH_DECODE_ADDRESS 0x0a8
56#define PCI_1MEMORY1_LOW_DECODE_ADDRESS 0x0b0
57#define PCI_1MEMORY1_HIGH_DECODE_ADDRESS 0x0b8
58#define PCI_1MEMORY2_LOW_DECODE_ADDRESS 0x2a0
59#define PCI_1MEMORY2_HIGH_DECODE_ADDRESS 0x2a8
60#define PCI_1MEMORY3_LOW_DECODE_ADDRESS 0x2b0
61#define PCI_1MEMORY3_HIGH_DECODE_ADDRESS 0x2b8
wdenk012771d2002-03-08 21:31:05 +000062
63
Wolfgang Denk53677ef2008-05-20 16:00:29 +020064#define INTERNAL_SPACE_DECODE 0x068
wdenk012771d2002-03-08 21:31:05 +000065
Wolfgang Denk53677ef2008-05-20 16:00:29 +020066#define CPU_0_LOW_DECODE_ADDRESS 0x290
67#define CPU_0_HIGH_DECODE_ADDRESS 0x298
68#define CPU_1_LOW_DECODE_ADDRESS 0x2c0
69#define CPU_1_HIGH_DECODE_ADDRESS 0x2c8
wdenk012771d2002-03-08 21:31:05 +000070
Wolfgang Denk53677ef2008-05-20 16:00:29 +020071#define PCI_0I_O_ADDRESS_REMAP 0x0f0
72#define PCI_0MEMORY0_ADDRESS_REMAP 0x0f8
73#define PCI_0MEMORY0_HIGH_ADDRESS_REMAP 0x320
74#define PCI_0MEMORY1_ADDRESS_REMAP 0x100
75#define PCI_0MEMORY1_HIGH_ADDRESS_REMAP 0x328
76#define PCI_0MEMORY2_ADDRESS_REMAP 0x2f8
77#define PCI_0MEMORY2_HIGH_ADDRESS_REMAP 0x330
78#define PCI_0MEMORY3_ADDRESS_REMAP 0x300
79#define PCI_0MEMORY3_HIGH_ADDRESS_REMAP 0x338
wdenk012771d2002-03-08 21:31:05 +000080
Wolfgang Denk53677ef2008-05-20 16:00:29 +020081#define PCI_1I_O_ADDRESS_REMAP 0x108
82#define PCI_1MEMORY0_ADDRESS_REMAP 0x110
83#define PCI_1MEMORY0_HIGH_ADDRESS_REMAP 0x340
84#define PCI_1MEMORY1_ADDRESS_REMAP 0x118
85#define PCI_1MEMORY1_HIGH_ADDRESS_REMAP 0x348
86#define PCI_1MEMORY2_ADDRESS_REMAP 0x310
87#define PCI_1MEMORY2_HIGH_ADDRESS_REMAP 0x350
88#define PCI_1MEMORY3_ADDRESS_REMAP 0x318
89#define PCI_1MEMORY3_HIGH_ADDRESS_REMAP 0x358
wdenk012771d2002-03-08 21:31:05 +000090
91
wdenk012771d2002-03-08 21:31:05 +000092/****************************************/
Wolfgang Denk53677ef2008-05-20 16:00:29 +020093/* CPU Sync Barrier */
wdenk012771d2002-03-08 21:31:05 +000094/****************************************/
95
Wolfgang Denk53677ef2008-05-20 16:00:29 +020096#define PCI_0SYNC_BARIER_VIRTUAL_REGISTER 0x0c0
97#define PCI_1SYNC_BARIER_VIRTUAL_REGISTER 0x0c8
wdenk012771d2002-03-08 21:31:05 +000098
99
100/****************************************/
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200101/* CPU Access Protect */
wdenk012771d2002-03-08 21:31:05 +0000102/****************************************/
103
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200104#define CPU_LOW_PROTECT_ADDRESS_0 0x180
105#define CPU_HIGH_PROTECT_ADDRESS_0 0x188
106#define CPU_LOW_PROTECT_ADDRESS_1 0x190
107#define CPU_HIGH_PROTECT_ADDRESS_1 0x198
108#define CPU_LOW_PROTECT_ADDRESS_2 0x1a0
109#define CPU_HIGH_PROTECT_ADDRESS_2 0x1a8
110#define CPU_LOW_PROTECT_ADDRESS_3 0x1b0
111#define CPU_HIGH_PROTECT_ADDRESS_3 0x1b8
112#define CPU_LOW_PROTECT_ADDRESS_4 0x1c0
113#define CPU_HIGH_PROTECT_ADDRESS_4 0x1c8
114#define CPU_LOW_PROTECT_ADDRESS_5 0x1d0
115#define CPU_HIGH_PROTECT_ADDRESS_5 0x1d8
116#define CPU_LOW_PROTECT_ADDRESS_6 0x1e0
117#define CPU_HIGH_PROTECT_ADDRESS_6 0x1e8
118#define CPU_LOW_PROTECT_ADDRESS_7 0x1f0
119#define CPU_HIGH_PROTECT_ADDRESS_7 0x1f8
wdenk012771d2002-03-08 21:31:05 +0000120
121
122/****************************************/
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200123/* Snoop Control */
wdenk012771d2002-03-08 21:31:05 +0000124/****************************************/
125
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200126#define SNOOP_BASE_ADDRESS_0 0x380
127#define SNOOP_TOP_ADDRESS_0 0x388
128#define SNOOP_BASE_ADDRESS_1 0x390
129#define SNOOP_TOP_ADDRESS_1 0x398
130#define SNOOP_BASE_ADDRESS_2 0x3a0
131#define SNOOP_TOP_ADDRESS_2 0x3a8
132#define SNOOP_BASE_ADDRESS_3 0x3b0
133#define SNOOP_TOP_ADDRESS_3 0x3b8
wdenk012771d2002-03-08 21:31:05 +0000134
135/****************************************/
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200136/* CPU Error Report */
wdenk012771d2002-03-08 21:31:05 +0000137/****************************************/
138
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200139#define CPU_ERROR_ADDRESS_LOW 0x070
140#define CPU_ERROR_ADDRESS_HIGH 0x078
141#define CPU_ERROR_DATA_LOW 0x128
142#define CPU_ERROR_DATA_HIGH 0x130
143#define CPU_ERROR_PARITY 0x138
144#define CPU_ERROR_CAUSE 0x140
145#define CPU_ERROR_MASK 0x148
wdenk012771d2002-03-08 21:31:05 +0000146
147/****************************************/
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200148/* Pslave Debug */
wdenk012771d2002-03-08 21:31:05 +0000149/****************************************/
150
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200151#define X_0_ADDRESS 0x360
152#define X_0_COMMAND_ID 0x368
153#define X_1_ADDRESS 0x370
154#define X_1_COMMAND_ID 0x378
155#define WRITE_DATA_LOW 0x3c0
156#define WRITE_DATA_HIGH 0x3c8
157#define WRITE_BYTE_ENABLE 0x3e0
158#define READ_DATA_LOW 0x3d0
159#define READ_DATA_HIGH 0x3d8
160#define READ_ID 0x3e8
wdenk012771d2002-03-08 21:31:05 +0000161
162
163/****************************************/
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200164/* SDRAM and Device Address Space */
wdenk012771d2002-03-08 21:31:05 +0000165/****************************************/
166
167
168/****************************************/
169/* SDRAM Configuration */
170/****************************************/
171
172
173#define SDRAM_CONFIGURATION 0x448
174#define SDRAM_OPERATION_MODE 0x474
175#define SDRAM_ADDRESS_DECODE 0x47c
176#define SDRAM_UMA_CONTROL 0x4a4
177#define SDRAM_CROSS_BAR_CONTROL_LOW 0x4a8
178#define SDRAM_CROSS_BAR_CONTROL_HIGH 0x4ac
179#define SDRAM_CROSS_BAR_TIMEOUT 0x4b0
180#define SDRAM_TIMING 0x4b4
181
182
183/****************************************/
184/* SDRAM Parameters */
185/****************************************/
186
187#define SDRAM_BANK0PARAMETERS 0x44C
188#define SDRAM_BANK1PARAMETERS 0x450
189#define SDRAM_BANK2PARAMETERS 0x454
190#define SDRAM_BANK3PARAMETERS 0x458
191
192
193/****************************************/
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200194/* SDRAM Error Report */
wdenk012771d2002-03-08 21:31:05 +0000195/****************************************/
196
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200197#define SDRAM_ERROR_DATA_LOW 0x484
198#define SDRAM_ERROR_DATA_HIGH 0x480
199#define SDRAM_AND_DEVICE_ERROR_ADDRESS 0x490
200#define SDRAM_RECEIVED_ECC 0x488
201#define SDRAM_CALCULATED_ECC 0x48c
202#define SDRAM_ECC_CONTROL 0x494
203#define SDRAM_ECC_ERROR_COUNTER 0x498
wdenk012771d2002-03-08 21:31:05 +0000204
205
206/****************************************/
207/* SDunit Debug (for internal use) */
208/****************************************/
209
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200210#define X0_ADDRESS 0x500
211#define X0_COMMAND_AND_ID 0x504
212#define X0_WRITE_DATA_LOW 0x508
213#define X0_WRITE_DATA_HIGH 0x50c
214#define X0_WRITE_BYTE_ENABLE 0x518
215#define X0_READ_DATA_LOW 0x510
216#define X0_READ_DATA_HIGH 0x514
217#define X0_READ_ID 0x51c
218#define X1_ADDRESS 0x520
219#define X1_COMMAND_AND_ID 0x524
220#define X1_WRITE_DATA_LOW 0x528
221#define X1_WRITE_DATA_HIGH 0x52c
222#define X1_WRITE_BYTE_ENABLE 0x538
223#define X1_READ_DATA_LOW 0x530
224#define X1_READ_DATA_HIGH 0x534
225#define X1_READ_ID 0x53c
226#define X0_SNOOP_ADDRESS 0x540
227#define X0_SNOOP_COMMAND 0x544
228#define X1_SNOOP_ADDRESS 0x548
229#define X1_SNOOP_COMMAND 0x54c
wdenk012771d2002-03-08 21:31:05 +0000230
231
wdenk012771d2002-03-08 21:31:05 +0000232/****************************************/
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200233/* Device Parameters */
wdenk012771d2002-03-08 21:31:05 +0000234/****************************************/
235
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200236#define DEVICE_BANK0PARAMETERS 0x45c
237#define DEVICE_BANK1PARAMETERS 0x460
238#define DEVICE_BANK2PARAMETERS 0x464
239#define DEVICE_BANK3PARAMETERS 0x468
240#define DEVICE_BOOT_BANK_PARAMETERS 0x46c
241#define DEVICE_CONTROL 0x4c0
242#define DEVICE_CROSS_BAR_CONTROL_LOW 0x4c8
243#define DEVICE_CROSS_BAR_CONTROL_HIGH 0x4cc
244#define DEVICE_CROSS_BAR_TIMEOUT 0x4c4
wdenk012771d2002-03-08 21:31:05 +0000245
246
247/****************************************/
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200248/* Device Interrupt */
wdenk012771d2002-03-08 21:31:05 +0000249/****************************************/
250
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200251#define DEVICE_INTERRUPT_CAUSE 0x4d0
252#define DEVICE_INTERRUPT_MASK 0x4d4
253#define DEVICE_ERROR_ADDRESS 0x4d8
wdenk012771d2002-03-08 21:31:05 +0000254
255/****************************************/
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200256/* DMA Record */
wdenk012771d2002-03-08 21:31:05 +0000257/****************************************/
258
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200259#define CHANNEL0_DMA_BYTE_COUNT 0x800
260#define CHANNEL1_DMA_BYTE_COUNT 0x804
261#define CHANNEL2_DMA_BYTE_COUNT 0x808
262#define CHANNEL3_DMA_BYTE_COUNT 0x80C
263#define CHANNEL4_DMA_BYTE_COUNT 0x900
264#define CHANNEL5_DMA_BYTE_COUNT 0x904
265#define CHANNEL6_DMA_BYTE_COUNT 0x908
266#define CHANNEL7_DMA_BYTE_COUNT 0x90C
267#define CHANNEL0_DMA_SOURCE_ADDRESS 0x810
268#define CHANNEL1_DMA_SOURCE_ADDRESS 0x814
269#define CHANNEL2_DMA_SOURCE_ADDRESS 0x818
270#define CHANNEL3_DMA_SOURCE_ADDRESS 0x81C
271#define CHANNEL4_DMA_SOURCE_ADDRESS 0x910
272#define CHANNEL5_DMA_SOURCE_ADDRESS 0x914
273#define CHANNEL6_DMA_SOURCE_ADDRESS 0x918
274#define CHANNEL7_DMA_SOURCE_ADDRESS 0x91C
275#define CHANNEL0_DMA_DESTINATION_ADDRESS 0x820
276#define CHANNEL1_DMA_DESTINATION_ADDRESS 0x824
277#define CHANNEL2_DMA_DESTINATION_ADDRESS 0x828
278#define CHANNEL3_DMA_DESTINATION_ADDRESS 0x82C
279#define CHANNEL4_DMA_DESTINATION_ADDRESS 0x920
280#define CHANNEL5_DMA_DESTINATION_ADDRESS 0x924
281#define CHANNEL6_DMA_DESTINATION_ADDRESS 0x928
282#define CHANNEL7_DMA_DESTINATION_ADDRESS 0x92C
283#define CHANNEL0NEXT_RECORD_POINTER 0x830
284#define CHANNEL1NEXT_RECORD_POINTER 0x834
285#define CHANNEL2NEXT_RECORD_POINTER 0x838
286#define CHANNEL3NEXT_RECORD_POINTER 0x83C
287#define CHANNEL4NEXT_RECORD_POINTER 0x930
288#define CHANNEL5NEXT_RECORD_POINTER 0x934
289#define CHANNEL6NEXT_RECORD_POINTER 0x938
290#define CHANNEL7NEXT_RECORD_POINTER 0x93C
291#define CHANNEL0CURRENT_DESCRIPTOR_POINTER 0x870
292#define CHANNEL1CURRENT_DESCRIPTOR_POINTER 0x874
293#define CHANNEL2CURRENT_DESCRIPTOR_POINTER 0x878
294#define CHANNEL3CURRENT_DESCRIPTOR_POINTER 0x87C
295#define CHANNEL4CURRENT_DESCRIPTOR_POINTER 0x970
296#define CHANNEL5CURRENT_DESCRIPTOR_POINTER 0x974
297#define CHANNEL6CURRENT_DESCRIPTOR_POINTER 0x978
298#define CHANNEL7CURRENT_DESCRIPTOR_POINTER 0x97C
299#define CHANNEL0_DMA_SOURCE_HIGH_PCI_ADDRESS 0x890
300#define CHANNEL1_DMA_SOURCE_HIGH_PCI_ADDRESS 0x894
301#define CHANNEL2_DMA_SOURCE_HIGH_PCI_ADDRESS 0x898
302#define CHANNEL3_DMA_SOURCE_HIGH_PCI_ADDRESS 0x89c
303#define CHANNEL4_DMA_SOURCE_HIGH_PCI_ADDRESS 0x990
304#define CHANNEL5_DMA_SOURCE_HIGH_PCI_ADDRESS 0x994
305#define CHANNEL6_DMA_SOURCE_HIGH_PCI_ADDRESS 0x998
306#define CHANNEL7_DMA_SOURCE_HIGH_PCI_ADDRESS 0x99c
307#define CHANNEL0_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a0
308#define CHANNEL1_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a4
309#define CHANNEL2_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a8
310#define CHANNEL3_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8ac
311#define CHANNEL4_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a0
312#define CHANNEL5_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a4
313#define CHANNEL6_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a8
314#define CHANNEL7_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9ac
315#define CHANNEL0_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b0
316#define CHANNEL1_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b4
317#define CHANNEL2_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b8
318#define CHANNEL3_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8bc
319#define CHANNEL4_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b0
320#define CHANNEL5_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b4
321#define CHANNEL6_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b8
322#define CHANNEL7_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9bc
wdenk012771d2002-03-08 21:31:05 +0000323
324/****************************************/
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200325/* DMA Channel Control */
wdenk012771d2002-03-08 21:31:05 +0000326/****************************************/
327
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200328#define CHANNEL0CONTROL 0x840
329#define CHANNEL0CONTROL_HIGH 0x880
330#define CHANNEL1CONTROL 0x844
331#define CHANNEL1CONTROL_HIGH 0x884
332#define CHANNEL2CONTROL 0x848
333#define CHANNEL2CONTROL_HIGH 0x888
334#define CHANNEL3CONTROL 0x84C
335#define CHANNEL3CONTROL_HIGH 0x88C
wdenk012771d2002-03-08 21:31:05 +0000336
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200337#define CHANNEL4CONTROL 0x940
338#define CHANNEL4CONTROL_HIGH 0x980
339#define CHANNEL5CONTROL 0x944
340#define CHANNEL5CONTROL_HIGH 0x984
341#define CHANNEL6CONTROL 0x948
342#define CHANNEL6CONTROL_HIGH 0x988
343#define CHANNEL7CONTROL 0x94C
344#define CHANNEL7CONTROL_HIGH 0x98C
wdenk012771d2002-03-08 21:31:05 +0000345
346
347/****************************************/
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200348/* DMA Arbiter */
wdenk012771d2002-03-08 21:31:05 +0000349/****************************************/
350
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200351#define ARBITER_CONTROL_0_3 0x860
352#define ARBITER_CONTROL_4_7 0x960
wdenk012771d2002-03-08 21:31:05 +0000353
354
355/****************************************/
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200356/* DMA Interrupt */
wdenk012771d2002-03-08 21:31:05 +0000357/****************************************/
358
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200359#define CHANELS0_3_INTERRUPT_CAUSE 0x8c0
360#define CHANELS0_3_INTERRUPT_MASK 0x8c4
361#define CHANELS0_3_ERROR_ADDRESS 0x8c8
362#define CHANELS0_3_ERROR_SELECT 0x8cc
363#define CHANELS4_7_INTERRUPT_CAUSE 0x9c0
364#define CHANELS4_7_INTERRUPT_MASK 0x9c4
365#define CHANELS4_7_ERROR_ADDRESS 0x9c8
366#define CHANELS4_7_ERROR_SELECT 0x9cc
wdenk012771d2002-03-08 21:31:05 +0000367
368
369/****************************************/
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200370/* DMA Debug (for internal use) */
wdenk012771d2002-03-08 21:31:05 +0000371/****************************************/
372
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200373#define DMA_X0_ADDRESS 0x8e0
374#define DMA_X0_COMMAND_AND_ID 0x8e4
375#define DMA_X0_WRITE_DATA_LOW 0x8e8
376#define DMA_X0_WRITE_DATA_HIGH 0x8ec
377#define DMA_X0_WRITE_BYTE_ENABLE 0x8f8
378#define DMA_X0_READ_DATA_LOW 0x8f0
379#define DMA_X0_READ_DATA_HIGH 0x8f4
380#define DMA_X0_READ_ID 0x8fc
381#define DMA_X1_ADDRESS 0x9e0
382#define DMA_X1_COMMAND_AND_ID 0x9e4
383#define DMA_X1_WRITE_DATA_LOW 0x9e8
384#define DMA_X1_WRITE_DATA_HIGH 0x9ec
385#define DMA_X1_WRITE_BYTE_ENABLE 0x9f8
386#define DMA_X1_READ_DATA_LOW 0x9f0
387#define DMA_X1_READ_DATA_HIGH 0x9f4
388#define DMA_X1_READ_ID 0x9fc
wdenk012771d2002-03-08 21:31:05 +0000389
390/****************************************/
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200391/* Timer_Counter */
wdenk012771d2002-03-08 21:31:05 +0000392/****************************************/
393
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200394#define TIMER_COUNTER0 0x850
395#define TIMER_COUNTER1 0x854
396#define TIMER_COUNTER2 0x858
397#define TIMER_COUNTER3 0x85C
398#define TIMER_COUNTER_0_3_CONTROL 0x864
399#define TIMER_COUNTER_0_3_INTERRUPT_CAUSE 0x868
400#define TIMER_COUNTER_0_3_INTERRUPT_MASK 0x86c
401#define TIMER_COUNTER4 0x950
402#define TIMER_COUNTER5 0x954
403#define TIMER_COUNTER6 0x958
404#define TIMER_COUNTER7 0x95C
405#define TIMER_COUNTER_4_7_CONTROL 0x964
406#define TIMER_COUNTER_4_7_INTERRUPT_CAUSE 0x968
407#define TIMER_COUNTER_4_7_INTERRUPT_MASK 0x96c
wdenk012771d2002-03-08 21:31:05 +0000408
409/****************************************/
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200410/* PCI Slave Address Decoding */
wdenk012771d2002-03-08 21:31:05 +0000411/****************************************/
412
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200413#define PCI_0SCS_0_BANK_SIZE 0xc08
414#define PCI_1SCS_0_BANK_SIZE 0xc88
415#define PCI_0SCS_1_BANK_SIZE 0xd08
416#define PCI_1SCS_1_BANK_SIZE 0xd88
417#define PCI_0SCS_2_BANK_SIZE 0xc0c
418#define PCI_1SCS_2_BANK_SIZE 0xc8c
419#define PCI_0SCS_3_BANK_SIZE 0xd0c
420#define PCI_1SCS_3_BANK_SIZE 0xd8c
421#define PCI_0CS_0_BANK_SIZE 0xc10
422#define PCI_1CS_0_BANK_SIZE 0xc90
423#define PCI_0CS_1_BANK_SIZE 0xd10
424#define PCI_1CS_1_BANK_SIZE 0xd90
425#define PCI_0CS_2_BANK_SIZE 0xd18
426#define PCI_1CS_2_BANK_SIZE 0xd98
427#define PCI_0CS_3_BANK_SIZE 0xc14
428#define PCI_1CS_3_BANK_SIZE 0xc94
429#define PCI_0CS_BOOT_BANK_SIZE 0xd14
430#define PCI_1CS_BOOT_BANK_SIZE 0xd94
431#define PCI_0P2P_MEM0_BAR_SIZE 0xd1c
432#define PCI_1P2P_MEM0_BAR_SIZE 0xd9c
433#define PCI_0P2P_MEM1_BAR_SIZE 0xd20
434#define PCI_1P2P_MEM1_BAR_SIZE 0xda0
435#define PCI_0P2P_I_O_BAR_SIZE 0xd24
436#define PCI_1P2P_I_O_BAR_SIZE 0xda4
437#define PCI_0CPU_BAR_SIZE 0xd28
438#define PCI_1CPU_BAR_SIZE 0xda8
439#define PCI_0DAC_SCS_0_BANK_SIZE 0xe00
440#define PCI_1DAC_SCS_0_BANK_SIZE 0xe80
441#define PCI_0DAC_SCS_1_BANK_SIZE 0xe04
442#define PCI_1DAC_SCS_1_BANK_SIZE 0xe84
443#define PCI_0DAC_SCS_2_BANK_SIZE 0xe08
444#define PCI_1DAC_SCS_2_BANK_SIZE 0xe88
445#define PCI_0DAC_SCS_3_BANK_SIZE 0xe0c
446#define PCI_1DAC_SCS_3_BANK_SIZE 0xe8c
447#define PCI_0DAC_CS_0_BANK_SIZE 0xe10
448#define PCI_1DAC_CS_0_BANK_SIZE 0xe90
449#define PCI_0DAC_CS_1_BANK_SIZE 0xe14
450#define PCI_1DAC_CS_1_BANK_SIZE 0xe94
451#define PCI_0DAC_CS_2_BANK_SIZE 0xe18
452#define PCI_1DAC_CS_2_BANK_SIZE 0xe98
453#define PCI_0DAC_CS_3_BANK_SIZE 0xe1c
454#define PCI_1DAC_CS_3_BANK_SIZE 0xe9c
455#define PCI_0DAC_BOOTCS_BANK_SIZE 0xe20
456#define PCI_1DAC_BOOTCS_BANK_SIZE 0xea0
457#define PCI_0DAC_P2P_MEM0_BAR_SIZE 0xe24
458#define PCI_1DAC_P2P_MEM0_BAR_SIZE 0xea4
459#define PCI_0DAC_P2P_MEM1_BAR_SIZE 0xe28
460#define PCI_1DAC_P2P_MEM1_BAR_SIZE 0xea8
461#define PCI_0DAC_CPU_BAR_SIZE 0xe2c
462#define PCI_1DAC_CPU_BAR_SIZE 0xeac
463#define PCI_0EXPANSION_ROM_BAR_SIZE 0xd2c
464#define PCI_1EXPANSION_ROM_BAR_SIZE 0xdac
465#define PCI_0BASE_ADDRESS_REGISTERS_ENABLE 0xc3c
466#define PCI_1BASE_ADDRESS_REGISTERS_ENABLE 0xcbc
467#define PCI_0SCS_0_BASE_ADDRESS_REMAP 0xc48
468#define PCI_1SCS_0_BASE_ADDRESS_REMAP 0xcc8
469#define PCI_0SCS_1_BASE_ADDRESS_REMAP 0xd48
470#define PCI_1SCS_1_BASE_ADDRESS_REMAP 0xdc8
471#define PCI_0SCS_2_BASE_ADDRESS_REMAP 0xc4c
472#define PCI_1SCS_2_BASE_ADDRESS_REMAP 0xccc
473#define PCI_0SCS_3_BASE_ADDRESS_REMAP 0xd4c
474#define PCI_1SCS_3_BASE_ADDRESS_REMAP 0xdcc
475#define PCI_0CS_0_BASE_ADDRESS_REMAP 0xc50
476#define PCI_1CS_0_BASE_ADDRESS_REMAP 0xcd0
477#define PCI_0CS_1_BASE_ADDRESS_REMAP 0xd50
478#define PCI_1CS_1_BASE_ADDRESS_REMAP 0xdd0
479#define PCI_0CS_2_BASE_ADDRESS_REMAP 0xd58
480#define PCI_1CS_2_BASE_ADDRESS_REMAP 0xdd8
481#define PCI_0CS_3_BASE_ADDRESS_REMAP 0xc54
482#define PCI_1CS_3_BASE_ADDRESS_REMAP 0xcd4
483#define PCI_0CS_BOOTCS_BASE_ADDRESS_REMAP 0xd54
484#define PCI_1CS_BOOTCS_BASE_ADDRESS_REMAP 0xdd4
485#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xd5c
486#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xddc
487#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xd60
488#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xde0
489#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xd64
490#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xde4
491#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xd68
492#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xde8
493#define PCI_0P2P_I_O_BASE_ADDRESS_REMAP 0xd6c
494#define PCI_1P2P_I_O_BASE_ADDRESS_REMAP 0xdec
495#define PCI_0CPU_BASE_ADDRESS_REMAP 0xd70
496#define PCI_1CPU_BASE_ADDRESS_REMAP 0xdf0
497#define PCI_0DAC_SCS_0_BASE_ADDRESS_REMAP 0xf00
498#define PCI_1DAC_SCS_0_BASE_ADDRESS_REMAP 0xff0
499#define PCI_0DAC_SCS_1_BASE_ADDRESS_REMAP 0xf04
500#define PCI_1DAC_SCS_1_BASE_ADDRESS_REMAP 0xf84
501#define PCI_0DAC_SCS_2_BASE_ADDRESS_REMAP 0xf08
502#define PCI_1DAC_SCS_2_BASE_ADDRESS_REMAP 0xf88
503#define PCI_0DAC_SCS_3_BASE_ADDRESS_REMAP 0xf0c
504#define PCI_1DAC_SCS_3_BASE_ADDRESS_REMAP 0xf8c
505#define PCI_0DAC_CS_0_BASE_ADDRESS_REMAP 0xf10
506#define PCI_1DAC_CS_0_BASE_ADDRESS_REMAP 0xf90
507#define PCI_0DAC_CS_1_BASE_ADDRESS_REMAP 0xf14
508#define PCI_1DAC_CS_1_BASE_ADDRESS_REMAP 0xf94
509#define PCI_0DAC_CS_2_BASE_ADDRESS_REMAP 0xf18
510#define PCI_1DAC_CS_2_BASE_ADDRESS_REMAP 0xf98
511#define PCI_0DAC_CS_3_BASE_ADDRESS_REMAP 0xf1c
512#define PCI_1DAC_CS_3_BASE_ADDRESS_REMAP 0xf9c
513#define PCI_0DAC_BOOTCS_BASE_ADDRESS_REMAP 0xf20
514#define PCI_1DAC_BOOTCS_BASE_ADDRESS_REMAP 0xfa0
515#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xf24
516#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xfa4
517#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xf28
518#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xfa8
519#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xf2c
520#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xfac
521#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xf30
522#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xfb0
523#define PCI_0DAC_CPU_BASE_ADDRESS_REMAP 0xf34
524#define PCI_1DAC_CPU_BASE_ADDRESS_REMAP 0xfb4
525#define PCI_0EXPANSION_ROM_BASE_ADDRESS_REMAP 0xf38
526#define PCI_1EXPANSION_ROM_BASE_ADDRESS_REMAP 0xfb8
527#define PCI_0ADDRESS_DECODE_CONTROL 0xd3c
528#define PCI_1ADDRESS_DECODE_CONTROL 0xdbc
wdenk012771d2002-03-08 21:31:05 +0000529
530/****************************************/
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200531/* PCI Control */
wdenk012771d2002-03-08 21:31:05 +0000532/****************************************/
533
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200534#define PCI_0COMMAND 0xc00
535#define PCI_1COMMAND 0xc80
536#define PCI_0MODE 0xd00
537#define PCI_1MODE 0xd80
538#define PCI_0TIMEOUT_RETRY 0xc04
539#define PCI_1TIMEOUT_RETRY 0xc84
540#define PCI_0READ_BUFFER_DISCARD_TIMER 0xd04
541#define PCI_1READ_BUFFER_DISCARD_TIMER 0xd84
542#define MSI_0TRIGGER_TIMER 0xc38
543#define MSI_1TRIGGER_TIMER 0xcb8
544#define PCI_0ARBITER_CONTROL 0x1d00
545#define PCI_1ARBITER_CONTROL 0x1d80
wdenk012771d2002-03-08 21:31:05 +0000546/* changing untill here */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200547#define PCI_0CROSS_BAR_CONTROL_LOW 0x1d08
548#define PCI_0CROSS_BAR_CONTROL_HIGH 0x1d0c
549#define PCI_0CROSS_BAR_TIMEOUT 0x1d04
550#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_LOW 0x1d18
551#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_HIGH 0x1d1c
552#define PCI_0SYNC_BARRIER_VIRTUAL_REGISTER 0x1d10
553#define PCI_0P2P_CONFIGURATION 0x1d14
554#define PCI_0ACCESS_CONTROL_BASE_0_LOW 0x1e00
555#define PCI_0ACCESS_CONTROL_BASE_0_HIGH 0x1e04
556#define PCI_0ACCESS_CONTROL_TOP_0 0x1e08
557#define PCI_0ACCESS_CONTROL_BASE_1_LOW 0x1e10
558#define PCI_0ACCESS_CONTROL_BASE_1_HIGH 0x1e14
559#define PCI_0ACCESS_CONTROL_TOP_1 0x1e18
560#define PCI_0ACCESS_CONTROL_BASE_2_LOW 0x1e20
561#define PCI_0ACCESS_CONTROL_BASE_2_HIGH 0x1e24
562#define PCI_0ACCESS_CONTROL_TOP_2 0x1e28
563#define PCI_0ACCESS_CONTROL_BASE_3_LOW 0x1e30
564#define PCI_0ACCESS_CONTROL_BASE_3_HIGH 0x1e34
565#define PCI_0ACCESS_CONTROL_TOP_3 0x1e38
566#define PCI_0ACCESS_CONTROL_BASE_4_LOW 0x1e40
567#define PCI_0ACCESS_CONTROL_BASE_4_HIGH 0x1e44
568#define PCI_0ACCESS_CONTROL_TOP_4 0x1e48
569#define PCI_0ACCESS_CONTROL_BASE_5_LOW 0x1e50
570#define PCI_0ACCESS_CONTROL_BASE_5_HIGH 0x1e54
571#define PCI_0ACCESS_CONTROL_TOP_5 0x1e58
572#define PCI_0ACCESS_CONTROL_BASE_6_LOW 0x1e60
573#define PCI_0ACCESS_CONTROL_BASE_6_HIGH 0x1e64
574#define PCI_0ACCESS_CONTROL_TOP_6 0x1e68
575#define PCI_0ACCESS_CONTROL_BASE_7_LOW 0x1e70
576#define PCI_0ACCESS_CONTROL_BASE_7_HIGH 0x1e74
577#define PCI_0ACCESS_CONTROL_TOP_7 0x1e78
578#define PCI_1CROSS_BAR_CONTROL_LOW 0x1d88
579#define PCI_1CROSS_BAR_CONTROL_HIGH 0x1d8c
580#define PCI_1CROSS_BAR_TIMEOUT 0x1d84
581#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_LOW 0x1d98
582#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_HIGH 0x1d9c
583#define PCI_1SYNC_BARRIER_VIRTUAL_REGISTER 0x1d90
584#define PCI_1P2P_CONFIGURATION 0x1d94
585#define PCI_1ACCESS_CONTROL_BASE_0_LOW 0x1e80
586#define PCI_1ACCESS_CONTROL_BASE_0_HIGH 0x1e84
587#define PCI_1ACCESS_CONTROL_TOP_0 0x1e88
588#define PCI_1ACCESS_CONTROL_BASE_1_LOW 0x1e90
589#define PCI_1ACCESS_CONTROL_BASE_1_HIGH 0x1e94
590#define PCI_1ACCESS_CONTROL_TOP_1 0x1e98
591#define PCI_1ACCESS_CONTROL_BASE_2_LOW 0x1ea0
592#define PCI_1ACCESS_CONTROL_BASE_2_HIGH 0x1ea4
593#define PCI_1ACCESS_CONTROL_TOP_2 0x1ea8
594#define PCI_1ACCESS_CONTROL_BASE_3_LOW 0x1eb0
595#define PCI_1ACCESS_CONTROL_BASE_3_HIGH 0x1eb4
596#define PCI_1ACCESS_CONTROL_TOP_3 0x1eb8
597#define PCI_1ACCESS_CONTROL_BASE_4_LOW 0x1ec0
598#define PCI_1ACCESS_CONTROL_BASE_4_HIGH 0x1ec4
599#define PCI_1ACCESS_CONTROL_TOP_4 0x1ec8
600#define PCI_1ACCESS_CONTROL_BASE_5_LOW 0x1ed0
601#define PCI_1ACCESS_CONTROL_BASE_5_HIGH 0x1ed4
602#define PCI_1ACCESS_CONTROL_TOP_5 0x1ed8
603#define PCI_1ACCESS_CONTROL_BASE_6_LOW 0x1ee0
604#define PCI_1ACCESS_CONTROL_BASE_6_HIGH 0x1ee4
605#define PCI_1ACCESS_CONTROL_TOP_6 0x1ee8
606#define PCI_1ACCESS_CONTROL_BASE_7_LOW 0x1ef0
607#define PCI_1ACCESS_CONTROL_BASE_7_HIGH 0x1ef4
608#define PCI_1ACCESS_CONTROL_TOP_7 0x1ef8
wdenk012771d2002-03-08 21:31:05 +0000609
610/****************************************/
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200611/* PCI Snoop Control */
wdenk012771d2002-03-08 21:31:05 +0000612/****************************************/
613
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200614#define PCI_0SNOOP_CONTROL_BASE_0_LOW 0x1f00
615#define PCI_0SNOOP_CONTROL_BASE_0_HIGH 0x1f04
616#define PCI_0SNOOP_CONTROL_TOP_0 0x1f08
617#define PCI_0SNOOP_CONTROL_BASE_1_0_LOW 0x1f10
618#define PCI_0SNOOP_CONTROL_BASE_1_0_HIGH 0x1f14
619#define PCI_0SNOOP_CONTROL_TOP_1 0x1f18
620#define PCI_0SNOOP_CONTROL_BASE_2_0_LOW 0x1f20
621#define PCI_0SNOOP_CONTROL_BASE_2_0_HIGH 0x1f24
622#define PCI_0SNOOP_CONTROL_TOP_2 0x1f28
623#define PCI_0SNOOP_CONTROL_BASE_3_0_LOW 0x1f30
624#define PCI_0SNOOP_CONTROL_BASE_3_0_HIGH 0x1f34
625#define PCI_0SNOOP_CONTROL_TOP_3 0x1f38
626#define PCI_1SNOOP_CONTROL_BASE_0_LOW 0x1f80
627#define PCI_1SNOOP_CONTROL_BASE_0_HIGH 0x1f84
628#define PCI_1SNOOP_CONTROL_TOP_0 0x1f88
629#define PCI_1SNOOP_CONTROL_BASE_1_0_LOW 0x1f90
630#define PCI_1SNOOP_CONTROL_BASE_1_0_HIGH 0x1f94
631#define PCI_1SNOOP_CONTROL_TOP_1 0x1f98
632#define PCI_1SNOOP_CONTROL_BASE_2_0_LOW 0x1fa0
633#define PCI_1SNOOP_CONTROL_BASE_2_0_HIGH 0x1fa4
634#define PCI_1SNOOP_CONTROL_TOP_2 0x1fa8
635#define PCI_1SNOOP_CONTROL_BASE_3_0_LOW 0x1fb0
636#define PCI_1SNOOP_CONTROL_BASE_3_0_HIGH 0x1fb4
637#define PCI_1SNOOP_CONTROL_TOP_3 0x1fb8
wdenk012771d2002-03-08 21:31:05 +0000638
639/****************************************/
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200640/* PCI Configuration Address */
wdenk012771d2002-03-08 21:31:05 +0000641/****************************************/
642
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200643#define PCI_0CONFIGURATION_ADDRESS 0xcf8
644#define PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER 0xcfc
645#define PCI_1CONFIGURATION_ADDRESS 0xc78
646#define PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER 0xc7c
647#define PCI_0INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER 0xc34
648#define PCI_1INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER 0xcb4
wdenk012771d2002-03-08 21:31:05 +0000649
650/****************************************/
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200651/* PCI Error Report */
wdenk012771d2002-03-08 21:31:05 +0000652/****************************************/
653
654#define PCI_0SERR_MASK 0xc28
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200655#define PCI_0ERROR_ADDRESS_LOW 0x1d40
656#define PCI_0ERROR_ADDRESS_HIGH 0x1d44
657#define PCI_0ERROR_DATA_LOW 0x1d48
658#define PCI_0ERROR_DATA_HIGH 0x1d4c
659#define PCI_0ERROR_COMMAND 0x1d50
660#define PCI_0ERROR_CAUSE 0x1d58
661#define PCI_0ERROR_MASK 0x1d5c
wdenk012771d2002-03-08 21:31:05 +0000662#define PCI_1SERR_MASK 0xca8
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200663#define PCI_1ERROR_ADDRESS_LOW 0x1dc0
664#define PCI_1ERROR_ADDRESS_HIGH 0x1dc4
665#define PCI_1ERROR_DATA_LOW 0x1dc8
666#define PCI_1ERROR_DATA_HIGH 0x1dcc
667#define PCI_1ERROR_COMMAND 0x1dd0
668#define PCI_1ERROR_CAUSE 0x1dd8
669#define PCI_1ERROR_MASK 0x1ddc
wdenk012771d2002-03-08 21:31:05 +0000670
671
672/****************************************/
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200673/* Lslave Debug (for internal use) */
wdenk012771d2002-03-08 21:31:05 +0000674/****************************************/
675
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200676#define L_SLAVE_X0_ADDRESS 0x1d20
677#define L_SLAVE_X0_COMMAND_AND_ID 0x1d24
678#define L_SLAVE_X1_ADDRESS 0x1d28
679#define L_SLAVE_X1_COMMAND_AND_ID 0x1d2c
680#define L_SLAVE_WRITE_DATA_LOW 0x1d30
681#define L_SLAVE_WRITE_DATA_HIGH 0x1d34
682#define L_SLAVE_WRITE_BYTE_ENABLE 0x1d60
683#define L_SLAVE_READ_DATA_LOW 0x1d38
684#define L_SLAVE_READ_DATA_HIGH 0x1d3c
685#define L_SLAVE_READ_ID 0x1d64
wdenk012771d2002-03-08 21:31:05 +0000686
687/****************************************/
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200688/* PCI Configuration Function 0 */
wdenk012771d2002-03-08 21:31:05 +0000689/****************************************/
690
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200691#define PCI_DEVICE_AND_VENDOR_ID 0x000
692#define PCI_STATUS_AND_COMMAND 0x004
693#define PCI_CLASS_CODE_AND_REVISION_ID 0x008
694#define PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 0x00C
695#define PCI_SCS_0_BASE_ADDRESS 0x010
696#define PCI_SCS_1_BASE_ADDRESS 0x014
697#define PCI_SCS_2_BASE_ADDRESS 0x018
698#define PCI_SCS_3_BASE_ADDRESS 0x01C
699#define PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS 0x020
700#define PCI_INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS 0x024
701#define PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID 0x02C
702#define PCI_EXPANSION_ROM_BASE_ADDRESS_REGISTER 0x030
703#define PCI_CAPABILTY_LIST_POINTER 0x034
704#define PCI_INTERRUPT_PIN_AND_LINE 0x03C
705#define PCI_POWER_MANAGEMENT_CAPABILITY 0x040
706#define PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL 0x044
707#define PCI_VPD_ADDRESS 0x048
708#define PCI_VPD_DATA 0x04c
709#define PCI_MSI_MESSAGE_CONTROL 0x050
710#define PCI_MSI_MESSAGE_ADDRESS 0x054
711#define PCI_MSI_MESSAGE_UPPER_ADDRESS 0x058
712#define PCI_MSI_MESSAGE_DATA 0x05c
713#define PCI_COMPACT_PCI_HOT_SWAP_CAPABILITY 0x058
wdenk012771d2002-03-08 21:31:05 +0000714
715/****************************************/
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200716/* PCI Configuration Function 1 */
wdenk012771d2002-03-08 21:31:05 +0000717/****************************************/
718
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200719#define PCI_CS_0_BASE_ADDRESS 0x110
720#define PCI_CS_1_BASE_ADDRESS 0x114
721#define PCI_CS_2_BASE_ADDRESS 0x118
722#define PCI_CS_3_BASE_ADDRESS 0x11c
723#define PCI_BOOTCS_BASE_ADDRESS 0x120
wdenk012771d2002-03-08 21:31:05 +0000724
725/****************************************/
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200726/* PCI Configuration Function 2 */
wdenk012771d2002-03-08 21:31:05 +0000727/****************************************/
728
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200729#define PCI_P2P_MEM0_BASE_ADDRESS 0x210
730#define PCI_P2P_MEM1_BASE_ADDRESS 0x214
731#define PCI_P2P_I_O_BASE_ADDRESS 0x218
732#define PCI_CPU_BASE_ADDRESS 0x21c
wdenk012771d2002-03-08 21:31:05 +0000733
734/****************************************/
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200735/* PCI Configuration Function 4 */
wdenk012771d2002-03-08 21:31:05 +0000736/****************************************/
737
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200738#define PCI_DAC_SCS_0_BASE_ADDRESS_LOW 0x410
739#define PCI_DAC_SCS_0_BASE_ADDRESS_HIGH 0x414
740#define PCI_DAC_SCS_1_BASE_ADDRESS_LOW 0x418
741#define PCI_DAC_SCS_1_BASE_ADDRESS_HIGH 0x41c
742#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_LOW 0x420
743#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_HIGH 0x424
wdenk012771d2002-03-08 21:31:05 +0000744
745
746/****************************************/
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200747/* PCI Configuration Function 5 */
wdenk012771d2002-03-08 21:31:05 +0000748/****************************************/
749
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200750#define PCI_DAC_SCS_2_BASE_ADDRESS_LOW 0x510
751#define PCI_DAC_SCS_2_BASE_ADDRESS_HIGH 0x514
752#define PCI_DAC_SCS_3_BASE_ADDRESS_LOW 0x518
753#define PCI_DAC_SCS_3_BASE_ADDRESS_HIGH 0x51c
754#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_LOW 0x520
755#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_HIGH 0x524
wdenk012771d2002-03-08 21:31:05 +0000756
757
758/****************************************/
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200759/* PCI Configuration Function 6 */
wdenk012771d2002-03-08 21:31:05 +0000760/****************************************/
761
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200762#define PCI_DAC_CS_0_BASE_ADDRESS_LOW 0x610
763#define PCI_DAC_CS_0_BASE_ADDRESS_HIGH 0x614
764#define PCI_DAC_CS_1_BASE_ADDRESS_LOW 0x618
765#define PCI_DAC_CS_1_BASE_ADDRESS_HIGH 0x61c
766#define PCI_DAC_CS_2_BASE_ADDRESS_LOW 0x620
767#define PCI_DAC_CS_2_BASE_ADDRESS_HIGH 0x624
wdenk012771d2002-03-08 21:31:05 +0000768
769/****************************************/
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200770/* PCI Configuration Function 7 */
wdenk012771d2002-03-08 21:31:05 +0000771/****************************************/
772
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200773#define PCI_DAC_CS_3_BASE_ADDRESS_LOW 0x710
774#define PCI_DAC_CS_3_BASE_ADDRESS_HIGH 0x714
775#define PCI_DAC_BOOTCS_BASE_ADDRESS_LOW 0x718
776#define PCI_DAC_BOOTCS_BASE_ADDRESS_HIGH 0x71c
777#define PCI_DAC_CPU_BASE_ADDRESS_LOW 0x720
778#define PCI_DAC_CPU_BASE_ADDRESS_HIGH 0x724
wdenk012771d2002-03-08 21:31:05 +0000779
780/****************************************/
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200781/* Interrupts */
wdenk012771d2002-03-08 21:31:05 +0000782/****************************************/
783
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200784#define LOW_INTERRUPT_CAUSE_REGISTER 0xc18
785#define HIGH_INTERRUPT_CAUSE_REGISTER 0xc68
786#define CPU_INTERRUPT_MASK_REGISTER_LOW 0xc1c
787#define CPU_INTERRUPT_MASK_REGISTER_HIGH 0xc6c
788#define CPU_SELECT_CAUSE_REGISTER 0xc70
789#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW 0xc24
790#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH 0xc64
791#define PCI_0SELECT_CAUSE 0xc74
792#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW 0xca4
793#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH 0xce4
794#define PCI_1SELECT_CAUSE 0xcf4
795#define CPU_INT_0_MASK 0xe60
796#define CPU_INT_1_MASK 0xe64
797#define CPU_INT_2_MASK 0xe68
798#define CPU_INT_3_MASK 0xe6c
wdenk012771d2002-03-08 21:31:05 +0000799
800/****************************************/
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200801/* I20 Support registers */
wdenk012771d2002-03-08 21:31:05 +0000802/****************************************/
803
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200804#define INBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x010
805#define INBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x014
806#define OUTBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x018
807#define OUTBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x01C
808#define INBOUND_DOORBELL_REGISTER_PCI_SIDE 0x020
809#define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x024
810#define INBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x028
811#define OUTBOUND_DOORBELL_REGISTER_PCI_SIDE 0x02C
812#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x030
813#define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x034
814#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x040
815#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x044
816#define QUEUE_CONTROL_REGISTER_PCI_SIDE 0x050
817#define QUEUE_BASE_ADDRESS_REGISTER_PCI_SIDE 0x054
818#define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x060
819#define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x064
820#define INBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x068
821#define INBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x06C
822#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x070
823#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x074
824#define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x078
825#define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x07C
wdenk012771d2002-03-08 21:31:05 +0000826
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200827#define INBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1C10
828#define INBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1C14
829#define OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1C18
830#define OUTBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1C1C
831#define INBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1C20
832#define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1C24
833#define INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1C28
834#define OUTBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1C2C
835#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1C30
836#define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1C34
837#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1C40
838#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1C44
839#define QUEUE_CONTROL_REGISTER_CPU_SIDE 0x1C50
840#define QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE 0x1C54
841#define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C60
842#define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C64
843#define INBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C68
844#define INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C6C
845#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C70
846#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C74
847#define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C78
848#define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C7C
wdenk012771d2002-03-08 21:31:05 +0000849
850/****************************************/
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200851/* Communication Unit Registers */
wdenk012771d2002-03-08 21:31:05 +0000852/****************************************/
853
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200854#define ETHERNET_0_ADDRESS_CONTROL_LOW 0xf200
855#define ETHERNET_0_ADDRESS_CONTROL_HIGH 0xf204
856#define ETHERNET_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf208
857#define ETHERNET_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf20c
858#define ETHERNET_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf210
859#define ETHERNET_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf214
860#define ETHERNET_0_HASH_TABLE_PCI_HIGH_ADDRESS 0xf218
861#define ETHERNET_1_ADDRESS_CONTROL_LOW 0xf220
862#define ETHERNET_1_ADDRESS_CONTROL_HIGH 0xf224
863#define ETHERNET_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf228
864#define ETHERNET_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf22c
865#define ETHERNET_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf230
866#define ETHERNET_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf234
867#define ETHERNET_1_HASH_TABLE_PCI_HIGH_ADDRESS 0xf238
868#define ETHERNET_2_ADDRESS_CONTROL_LOW 0xf240
869#define ETHERNET_2_ADDRESS_CONTROL_HIGH 0xf244
870#define ETHERNET_2_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf248
871#define ETHERNET_2_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf24c
872#define ETHERNET_2_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf250
873#define ETHERNET_2_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf254
874#define ETHERNET_2_HASH_TABLE_PCI_HIGH_ADDRESS 0xf258
875#define MPSC_0_ADDRESS_CONTROL_LOW 0xf280
876#define MPSC_0_ADDRESS_CONTROL_HIGH 0xf284
877#define MPSC_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf288
878#define MPSC_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf28c
879#define MPSC_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf290
880#define MPSC_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf294
881#define MPSC_1_ADDRESS_CONTROL_LOW 0xf2c0
882#define MPSC_1_ADDRESS_CONTROL_HIGH 0xf2c4
883#define MPSC_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf2c8
884#define MPSC_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf2cc
885#define MPSC_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2d0
886#define MPSC_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2d4
887#define SERIAL_INIT_PCI_HIGH_ADDRESS 0xf320
888#define SERIAL_INIT_LAST_DATA 0xf324
889#define SERIAL_INIT_STATUS_AND_CONTROL 0xf328
890#define COMM_UNIT_ARBITER_CONTROL 0xf300
891#define COMM_UNIT_CROSS_BAR_TIMEOUT 0xf304
892#define COMM_UNIT_INTERRUPT_CAUSE 0xf310
893#define COMM_UNIT_INTERRUPT_MASK 0xf314
894#define COMM_UNIT_ERROR_ADDRESS 0xf314
wdenk012771d2002-03-08 21:31:05 +0000895
896/****************************************/
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200897/* Cunit Debug (for internal use) */
wdenk012771d2002-03-08 21:31:05 +0000898/****************************************/
899
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200900#define CUNIT_ADDRESS 0xf340
901#define CUNIT_COMMAND_AND_ID 0xf344
902#define CUNIT_WRITE_DATA_LOW 0xf348
903#define CUNIT_WRITE_DATA_HIGH 0xf34c
904#define CUNIT_WRITE_BYTE_ENABLE 0xf358
905#define CUNIT_READ_DATA_LOW 0xf350
906#define CUNIT_READ_DATA_HIGH 0xf354
907#define CUNIT_READ_ID 0xf35c
wdenk012771d2002-03-08 21:31:05 +0000908
909/****************************************/
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200910/* Fast Ethernet Unit Registers */
wdenk012771d2002-03-08 21:31:05 +0000911/****************************************/
912
913/* Ethernet */
914
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200915#define ETHERNET_PHY_ADDRESS_REGISTER 0x2000
916#define ETHERNET_SMI_REGISTER 0x2010
wdenk012771d2002-03-08 21:31:05 +0000917
918/* Ethernet 0 */
919
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200920#define ETHERNET0_PORT_CONFIGURATION_REGISTER 0x2400
921#define ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER 0x2408
922#define ETHERNET0_PORT_COMMAND_REGISTER 0x2410
923#define ETHERNET0_PORT_STATUS_REGISTER 0x2418
924#define ETHERNET0_SERIAL_PARAMETRS_REGISTER 0x2420
925#define ETHERNET0_HASH_TABLE_POINTER_REGISTER 0x2428
926#define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2430
927#define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2438
928#define ETHERNET0_SDMA_CONFIGURATION_REGISTER 0x2440
929#define ETHERNET0_SDMA_COMMAND_REGISTER 0x2448
930#define ETHERNET0_INTERRUPT_CAUSE_REGISTER 0x2450
931#define ETHERNET0_INTERRUPT_MASK_REGISTER 0x2458
932#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0 0x2480
933#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER1 0x2484
934#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER2 0x2488
935#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER3 0x248c
936#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0 0x24a0
937#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER1 0x24a4
938#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER2 0x24a8
939#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER3 0x24ac
940#define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0 0x24e0
941#define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER1 0x24e4
942#define ETHERNET0_MIB_COUNTER_BASE 0x2500
wdenk012771d2002-03-08 21:31:05 +0000943
944/* Ethernet 1 */
945
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200946#define ETHERNET1_PORT_CONFIGURATION_REGISTER 0x2800
947#define ETHERNET1_PORT_CONFIGURATION_EXTEND_REGISTER 0x2808
948#define ETHERNET1_PORT_COMMAND_REGISTER 0x2810
949#define ETHERNET1_PORT_STATUS_REGISTER 0x2818
950#define ETHERNET1_SERIAL_PARAMETRS_REGISTER 0x2820
951#define ETHERNET1_HASH_TABLE_POINTER_REGISTER 0x2828
952#define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2830
953#define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2838
954#define ETHERNET1_SDMA_CONFIGURATION_REGISTER 0x2840
955#define ETHERNET1_SDMA_COMMAND_REGISTER 0x2848
956#define ETHERNET1_INTERRUPT_CAUSE_REGISTER 0x2850
957#define ETHERNET1_INTERRUPT_MASK_REGISTER 0x2858
958#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER0 0x2880
959#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER1 0x2884
960#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER2 0x2888
961#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER3 0x288c
962#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER0 0x28a0
963#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER1 0x28a4
964#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER2 0x28a8
965#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER3 0x28ac
966#define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER0 0x28e0
967#define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER1 0x28e4
968#define ETHERNET1_MIB_COUNTER_BASE 0x2900
wdenk012771d2002-03-08 21:31:05 +0000969
970/* Ethernet 2 */
971
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200972#define ETHERNET2_PORT_CONFIGURATION_REGISTER 0x2c00
973#define ETHERNET2_PORT_CONFIGURATION_EXTEND_REGISTER 0x2c08
974#define ETHERNET2_PORT_COMMAND_REGISTER 0x2c10
975#define ETHERNET2_PORT_STATUS_REGISTER 0x2c18
976#define ETHERNET2_SERIAL_PARAMETRS_REGISTER 0x2c20
977#define ETHERNET2_HASH_TABLE_POINTER_REGISTER 0x2c28
978#define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2c30
979#define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2c38
980#define ETHERNET2_SDMA_CONFIGURATION_REGISTER 0x2c40
981#define ETHERNET2_SDMA_COMMAND_REGISTER 0x2c48
982#define ETHERNET2_INTERRUPT_CAUSE_REGISTER 0x2c50
983#define ETHERNET2_INTERRUPT_MASK_REGISTER 0x2c58
984#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER0 0x2c80
985#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER1 0x2c84
986#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER2 0x2c88
987#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER3 0x2c8c
988#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER0 0x2ca0
989#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER1 0x2ca4
990#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER2 0x2ca8
991#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER3 0x2cac
992#define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER0 0x2ce0
993#define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER1 0x2ce4
994#define ETHERNET2_MIB_COUNTER_BASE 0x2d00
wdenk012771d2002-03-08 21:31:05 +0000995
996/****************************************/
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200997/* SDMA Registers */
wdenk012771d2002-03-08 21:31:05 +0000998/****************************************/
999
Wolfgang Denk53677ef2008-05-20 16:00:29 +02001000#define SDMA_GROUP_CONFIGURATION_REGISTER 0xb1f0
1001#define CHANNEL0_CONFIGURATION_REGISTER 0x4000
1002#define CHANNEL0_COMMAND_REGISTER 0x4008
1003#define CHANNEL0_RX_CMD_STATUS 0x4800
1004#define CHANNEL0_RX_PACKET_AND_BUFFER_SIZES 0x4804
1005#define CHANNEL0_RX_BUFFER_POINTER 0x4808
1006#define CHANNEL0_RX_NEXT_POINTER 0x480c
1007#define CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER 0x4810
1008#define CHANNEL0_TX_CMD_STATUS 0x4C00
1009#define CHANNEL0_TX_PACKET_SIZE 0x4C04
1010#define CHANNEL0_TX_BUFFER_POINTER 0x4C08
1011#define CHANNEL0_TX_NEXT_POINTER 0x4C0c
1012#define CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER 0x4c10
1013#define CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER 0x4c14
1014#define CHANNEL1_CONFIGURATION_REGISTER 0x5000
1015#define CHANNEL1_COMMAND_REGISTER 0x5008
1016#define CHANNEL1_RX_CMD_STATUS 0x5800
1017#define CHANNEL1_RX_PACKET_AND_BUFFER_SIZES 0x5804
1018#define CHANNEL1_RX_BUFFER_POINTER 0x5808
1019#define CHANNEL1_RX_NEXT_POINTER 0x580c
1020#define CHANNEL1_TX_CMD_STATUS 0x5C00
1021#define CHANNEL1_TX_PACKET_SIZE 0x5C04
1022#define CHANNEL1_TX_BUFFER_POINTER 0x5C08
1023#define CHANNEL1_TX_NEXT_POINTER 0x5C0c
1024#define CHANNEL1_CURRENT_RX_DESCRIPTOR_POINTER 0x5810
1025#define CHANNEL1_CURRENT_TX_DESCRIPTOR_POINTER 0x5c10
1026#define CHANNEL1_FIRST_TX_DESCRIPTOR_POINTER 0x5c14
1027#define CHANNEL2_CONFIGURATION_REGISTER 0x6000
1028#define CHANNEL2_COMMAND_REGISTER 0x6008
1029#define CHANNEL2_RX_CMD_STATUS 0x6800
1030#define CHANNEL2_RX_PACKET_AND_BUFFER_SIZES 0x6804
1031#define CHANNEL2_RX_BUFFER_POINTER 0x6808
1032#define CHANNEL2_RX_NEXT_POINTER 0x680c
1033#define CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER 0x6810
1034#define CHANNEL2_TX_CMD_STATUS 0x6C00
1035#define CHANNEL2_TX_PACKET_SIZE 0x6C04
1036#define CHANNEL2_TX_BUFFER_POINTER 0x6C08
1037#define CHANNEL2_TX_NEXT_POINTER 0x6C0c
1038#define CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER 0x6810
1039#define CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER 0x6c10
1040#define CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER 0x6c14
wdenk012771d2002-03-08 21:31:05 +00001041
1042/* SDMA Interrupt */
1043
Wolfgang Denk53677ef2008-05-20 16:00:29 +02001044#define SDMA_CAUSE 0xb820
1045#define SDMA_MASK 0xb8a0
wdenk012771d2002-03-08 21:31:05 +00001046
1047
1048/****************************************/
Wolfgang Denk53677ef2008-05-20 16:00:29 +02001049/* Baude Rate Generators Registers */
wdenk012771d2002-03-08 21:31:05 +00001050/****************************************/
1051
1052/* BRG 0 */
1053
Wolfgang Denk53677ef2008-05-20 16:00:29 +02001054#define BRG0_CONFIGURATION_REGISTER 0xb200
1055#define BRG0_BAUDE_TUNING_REGISTER 0xb204
wdenk012771d2002-03-08 21:31:05 +00001056
1057/* BRG 1 */
1058
Wolfgang Denk53677ef2008-05-20 16:00:29 +02001059#define BRG1_CONFIGURATION_REGISTER 0xb208
1060#define BRG1_BAUDE_TUNING_REGISTER 0xb20c
wdenk012771d2002-03-08 21:31:05 +00001061
1062/* BRG 2 */
1063
Wolfgang Denk53677ef2008-05-20 16:00:29 +02001064#define BRG2_CONFIGURATION_REGISTER 0xb210
1065#define BRG2_BAUDE_TUNING_REGISTER 0xb214
wdenk012771d2002-03-08 21:31:05 +00001066
1067/* BRG Interrupts */
1068
Wolfgang Denk53677ef2008-05-20 16:00:29 +02001069#define BRG_CAUSE_REGISTER 0xb834
1070#define BRG_MASK_REGISTER 0xb8b4
wdenk012771d2002-03-08 21:31:05 +00001071
1072/* MISC */
1073
Wolfgang Denk53677ef2008-05-20 16:00:29 +02001074#define MAIN_ROUTING_REGISTER 0xb400
1075#define RECEIVE_CLOCK_ROUTING_REGISTER 0xb404
1076#define TRANSMIT_CLOCK_ROUTING_REGISTER 0xb408
1077#define COMM_UNIT_ARBITER_CONFIGURATION_REGISTER 0xb40c
1078#define WATCHDOG_CONFIGURATION_REGISTER 0xb410
1079#define WATCHDOG_VALUE_REGISTER 0xb414
wdenk012771d2002-03-08 21:31:05 +00001080
1081
1082/****************************************/
Wolfgang Denk53677ef2008-05-20 16:00:29 +02001083/* Flex TDM Registers */
wdenk012771d2002-03-08 21:31:05 +00001084/****************************************/
1085
1086/* FTDM Port */
1087
Wolfgang Denk53677ef2008-05-20 16:00:29 +02001088#define FLEXTDM_TRANSMIT_READ_POINTER 0xa800
1089#define FLEXTDM_RECEIVE_READ_POINTER 0xa804
1090#define FLEXTDM_CONFIGURATION_REGISTER 0xa808
1091#define FLEXTDM_AUX_CHANNELA_TX_REGISTER 0xa80c
1092#define FLEXTDM_AUX_CHANNELA_RX_REGISTER 0xa810
1093#define FLEXTDM_AUX_CHANNELB_TX_REGISTER 0xa814
1094#define FLEXTDM_AUX_CHANNELB_RX_REGISTER 0xa818
wdenk012771d2002-03-08 21:31:05 +00001095
1096/* FTDM Interrupts */
1097
Wolfgang Denk53677ef2008-05-20 16:00:29 +02001098#define FTDM_CAUSE_REGISTER 0xb830
1099#define FTDM_MASK_REGISTER 0xb8b0
wdenk012771d2002-03-08 21:31:05 +00001100
1101
1102/****************************************/
Wolfgang Denk53677ef2008-05-20 16:00:29 +02001103/* GPP Interface Registers */
wdenk012771d2002-03-08 21:31:05 +00001104/****************************************/
1105
Wolfgang Denk53677ef2008-05-20 16:00:29 +02001106#define GPP_IO_CONTROL 0xf100
1107#define GPP_LEVEL_CONTROL 0xf110
1108#define GPP_VALUE 0xf104
1109#define GPP_INTERRUPT_CAUSE 0xf108
1110#define GPP_INTERRUPT_MASK 0xf10c
wdenk012771d2002-03-08 21:31:05 +00001111
Wolfgang Denk53677ef2008-05-20 16:00:29 +02001112#define MPP_CONTROL0 0xf000
1113#define MPP_CONTROL1 0xf004
1114#define MPP_CONTROL2 0xf008
1115#define MPP_CONTROL3 0xf00c
1116#define DEBUG_PORT_MULTIPLEX 0xf014
1117#define SERIAL_PORT_MULTIPLEX 0xf010
wdenk012771d2002-03-08 21:31:05 +00001118
1119/****************************************/
Wolfgang Denk53677ef2008-05-20 16:00:29 +02001120/* I2C Registers */
wdenk012771d2002-03-08 21:31:05 +00001121/****************************************/
1122
Wolfgang Denk53677ef2008-05-20 16:00:29 +02001123#define I2C_SLAVE_ADDRESS 0xc000
1124#define I2C_EXTENDED_SLAVE_ADDRESS 0xc040
1125#define I2C_DATA 0xc004
1126#define I2C_CONTROL 0xc008
1127#define I2C_STATUS_BAUDE_RATE 0xc00C
1128#define I2C_SOFT_RESET 0xc01c
wdenk012771d2002-03-08 21:31:05 +00001129
1130/****************************************/
Wolfgang Denk53677ef2008-05-20 16:00:29 +02001131/* MPSC Registers */
wdenk012771d2002-03-08 21:31:05 +00001132/****************************************/
1133
1134/* MPSC0 */
1135
Wolfgang Denk53677ef2008-05-20 16:00:29 +02001136#define MPSC0_MAIN_CONFIGURATION_LOW 0x8000
1137#define MPSC0_MAIN_CONFIGURATION_HIGH 0x8004
1138#define MPSC0_PROTOCOL_CONFIGURATION 0x8008
1139#define CHANNEL0_REGISTER1 0x800c
1140#define CHANNEL0_REGISTER2 0x8010
1141#define CHANNEL0_REGISTER3 0x8014
1142#define CHANNEL0_REGISTER4 0x8018
1143#define CHANNEL0_REGISTER5 0x801c
1144#define CHANNEL0_REGISTER6 0x8020
1145#define CHANNEL0_REGISTER7 0x8024
1146#define CHANNEL0_REGISTER8 0x8028
1147#define CHANNEL0_REGISTER9 0x802c
1148#define CHANNEL0_REGISTER10 0x8030
1149#define CHANNEL0_REGISTER11 0x8034
wdenk012771d2002-03-08 21:31:05 +00001150
1151/* MPSC1 */
1152
Wolfgang Denk53677ef2008-05-20 16:00:29 +02001153#define MPSC1_MAIN_CONFIGURATION_LOW 0x8840
1154#define MPSC1_MAIN_CONFIGURATION_HIGH 0x8844
1155#define MPSC1_PROTOCOL_CONFIGURATION 0x8848
1156#define CHANNEL1_REGISTER1 0x884c
1157#define CHANNEL1_REGISTER2 0x8850
1158#define CHANNEL1_REGISTER3 0x8854
1159#define CHANNEL1_REGISTER4 0x8858
1160#define CHANNEL1_REGISTER5 0x885c
1161#define CHANNEL1_REGISTER6 0x8860
1162#define CHANNEL1_REGISTER7 0x8864
1163#define CHANNEL1_REGISTER8 0x8868
1164#define CHANNEL1_REGISTER9 0x886c
1165#define CHANNEL1_REGISTER10 0x8870
1166#define CHANNEL1_REGISTER11 0x8874
wdenk012771d2002-03-08 21:31:05 +00001167
1168/* MPSC2 */
1169
Wolfgang Denk53677ef2008-05-20 16:00:29 +02001170#define MPSC2_MAIN_CONFIGURATION_LOW 0x9040
1171#define MPSC2_MAIN_CONFIGURATION_HIGH 0x9044
1172#define MPSC2_PROTOCOL_CONFIGURATION 0x9048
1173#define CHANNEL2_REGISTER1 0x904c
1174#define CHANNEL2_REGISTER2 0x9050
1175#define CHANNEL2_REGISTER3 0x9054
1176#define CHANNEL2_REGISTER4 0x9058
1177#define CHANNEL2_REGISTER5 0x905c
1178#define CHANNEL2_REGISTER6 0x9060
1179#define CHANNEL2_REGISTER7 0x9064
1180#define CHANNEL2_REGISTER8 0x9068
1181#define CHANNEL2_REGISTER9 0x906c
1182#define CHANNEL2_REGISTER10 0x9070
1183#define CHANNEL2_REGISTER11 0x9074
wdenk012771d2002-03-08 21:31:05 +00001184
Mike Williams16263082011-07-22 04:01:30 +00001185/* MPSCs Interrupts */
wdenk012771d2002-03-08 21:31:05 +00001186
Wolfgang Denk53677ef2008-05-20 16:00:29 +02001187#define MPSC0_CAUSE 0xb824
1188#define MPSC0_MASK 0xb8a4
1189#define MPSC1_CAUSE 0xb828
1190#define MPSC1_MASK 0xb8a8
1191#define MPSC2_CAUSE 0xb82c
1192#define MPSC2_MASK 0xb8ac
wdenk012771d2002-03-08 21:31:05 +00001193
1194#endif /* __INCgt64260rh */