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Stefan Roese13354832016-05-25 08:23:31 +02001/*
2 * Copyright (C) 2016 Marvell Technology Group Ltd.
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPLv2 or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43/*
44 * Device Tree file for Marvell Armada AP806.
45 */
46
47#include <dt-bindings/interrupt-controller/arm-gic.h>
48
49/dts-v1/;
50
51/ {
52 model = "Marvell Armada AP806";
53 compatible = "marvell,armada-ap806";
54 #address-cells = <2>;
55 #size-cells = <2>;
56
57 aliases {
58 serial0 = &uart0;
59 serial1 = &uart1;
60 };
61
62 psci {
63 compatible = "arm,psci-0.2";
64 method = "smc";
65 };
66
67 ap806 {
68 #address-cells = <2>;
69 #size-cells = <2>;
70 compatible = "simple-bus";
71 interrupt-parent = <&gic>;
72 ranges;
73
74 config-space {
75 #address-cells = <1>;
76 #size-cells = <1>;
77 compatible = "simple-bus";
78 ranges = <0x0 0x0 0xf0000000 0x1000000>;
79
80 gic: interrupt-controller@210000 {
81 compatible = "arm,gic-400";
82 #interrupt-cells = <3>;
83 #address-cells = <1>;
84 #size-cells = <1>;
85 ranges;
86 interrupt-controller;
87 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
88 reg = <0x210000 0x10000>,
89 <0x220000 0x20000>,
90 <0x240000 0x20000>,
91 <0x260000 0x20000>;
92
93 gic_v2m0: v2m@280000 {
94 compatible = "arm,gic-v2m-frame";
95 msi-controller;
96 reg = <0x280000 0x1000>;
97 arm,msi-base-spi = <160>;
98 arm,msi-num-spis = <32>;
99 };
100 gic_v2m1: v2m@290000 {
101 compatible = "arm,gic-v2m-frame";
102 msi-controller;
103 reg = <0x290000 0x1000>;
104 arm,msi-base-spi = <192>;
105 arm,msi-num-spis = <32>;
106 };
107 gic_v2m2: v2m@2a0000 {
108 compatible = "arm,gic-v2m-frame";
109 msi-controller;
110 reg = <0x2a0000 0x1000>;
111 arm,msi-base-spi = <224>;
112 arm,msi-num-spis = <32>;
113 };
114 gic_v2m3: v2m@2b0000 {
115 compatible = "arm,gic-v2m-frame";
116 msi-controller;
117 reg = <0x2b0000 0x1000>;
118 arm,msi-base-spi = <256>;
119 arm,msi-num-spis = <32>;
120 };
121 };
122
123 timer {
124 compatible = "arm,armv8-timer";
125 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>,
126 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>,
127 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>,
128 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
129 };
130
131 odmi: odmi@300000 {
132 compatible = "marvell,odmi-controller";
133 interrupt-controller;
134 msi-controller;
135 marvell,odmi-frames = <4>;
136 reg = <0x300000 0x4000>,
137 <0x304000 0x4000>,
138 <0x308000 0x4000>,
139 <0x30C000 0x4000>;
140 marvell,spi-base = <128>, <136>, <144>, <152>;
141 };
142
Konstantin Porotchkinf99386c2016-12-08 12:22:30 +0200143 ap_pinctl: ap-pinctl@6F4000 {
144 compatible = "marvell,armada-ap806-pinctrl";
145 bank-name ="apn-806";
146 reg = <0x6F4000 0x10>;
147 pin-count = <20>;
148 max-func = <3>;
149
150 ap_i2c0_pins: i2c-pins-0 {
151 marvell,pins = < 4 5 >;
152 marvell,function = <3>;
153 };
154 ap_emmc_pins: emmc-pins-0 {
155 marvell,pins = < 0 1 2 3 4 5 6 7
156 8 9 10 >;
157 marvell,function = <1>;
158 };
159 };
160
Konstantin Porotchkin9eb34682017-02-08 17:34:11 +0200161 ap_gpio0: gpio@6F5040 {
162 compatible = "marvell,orion-gpio";
163 reg = <0x6F5040 0x40>;
164 ngpios = <20>;
165 gpio-controller;
166 #gpio-cells = <2>;
167 };
168
Stefan Roese13354832016-05-25 08:23:31 +0200169 xor@400000 {
170 compatible = "marvell,mv-xor-v2";
171 reg = <0x400000 0x1000>,
172 <0x410000 0x1000>;
173 msi-parent = <&gic_v2m0>;
174 dma-coherent;
175 };
176
177 xor@420000 {
178 compatible = "marvell,mv-xor-v2";
179 reg = <0x420000 0x1000>,
180 <0x430000 0x1000>;
181 msi-parent = <&gic_v2m0>;
182 dma-coherent;
183 };
184
185 xor@440000 {
186 compatible = "marvell,mv-xor-v2";
187 reg = <0x440000 0x1000>,
188 <0x450000 0x1000>;
189 msi-parent = <&gic_v2m0>;
190 dma-coherent;
191 };
192
193 xor@460000 {
194 compatible = "marvell,mv-xor-v2";
195 reg = <0x460000 0x1000>,
196 <0x470000 0x1000>;
197 msi-parent = <&gic_v2m0>;
198 dma-coherent;
199 };
200
201 spi0: spi@510600 {
202 compatible = "marvell,armada-380-spi";
203 reg = <0x510600 0x50>;
204 #address-cells = <1>;
205 #size-cells = <0>;
206 cell-index = <0>;
207 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
208 clocks = <&ap_syscon 3>;
209 status = "disabled";
210 };
211
212 i2c0: i2c@511000 {
213 compatible = "marvell,mv78230-i2c";
214 reg = <0x511000 0x20>;
215 #address-cells = <1>;
216 #size-cells = <0>;
217 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
218 timeout-ms = <1000>;
219 clocks = <&ap_syscon 3>;
220 status = "disabled";
221 };
222
223 uart0: serial@512000 {
224 compatible = "snps,dw-apb-uart";
225 reg = <0x512000 0x100>;
226 reg-shift = <2>;
227 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
228 reg-io-width = <1>;
229 clocks = <&ap_syscon 3>;
230 status = "disabled";
Stefan Roeseb5fbf5a2016-05-25 08:34:47 +0200231 clock-frequency = <200000000>;
Stefan Roese13354832016-05-25 08:23:31 +0200232 };
233
234 uart1: serial@512100 {
235 compatible = "snps,dw-apb-uart";
236 reg = <0x512100 0x100>;
237 reg-shift = <2>;
238 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
239 reg-io-width = <1>;
240 clocks = <&ap_syscon 3>;
241 status = "disabled";
242
243 };
244
Stefan Roeseb14b0b12016-12-09 15:40:05 +0100245 ap_sdhci0: sdhci@6e0000 {
246 compatible = "marvell,armada-8k-sdhci";
247 reg = <0x6e0000 0x300>;
248 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
249 dma-coherent;
250 status = "disabled";
251 };
252
Stefan Roese13354832016-05-25 08:23:31 +0200253 ap_syscon: system-controller@6f4000 {
254 compatible = "marvell,ap806-system-controller",
255 "syscon";
256 #clock-cells = <1>;
257 clock-output-names = "ap-cpu-cluster-0",
258 "ap-cpu-cluster-1",
259 "ap-fixed", "ap-mss";
260 reg = <0x6f4000 0x1000>;
261 };
262 };
263 };
264};