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wdenk0f8c9762002-08-19 11:57:05 +00001/*
2 * (C) Copyright 2000
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_MPC860 1 /* This is a MPC860 CPU */
37#define CONFIG_IVMS8 1 /* ...on a IVMS8 board */
38
39#if defined (CONFIG_IVMS8_16M)
40# define CONFIG_IDENT_STRING " IVMS8"
41#elif defined (CONFIG_IVMS8_32M)
42# define CONFIG_IDENT_STRING " IVMS8_128"
43#elif defined (CONFIG_IVMS8_64M)
44# define CONFIG_IDENT_STRING " IVMS8_256"
45#endif
46
47#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
48#undef CONFIG_8xx_CONS_SMC2
49#undef CONFIG_8xx_CONS_NONE
50#define CONFIG_BAUDRATE 115200
51
52#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
53#define CONFIG_8xx_GCLK_FREQ 50331648
54
55#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */
56
57#if 0
58#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
59#else
60#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
61#endif
62#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */
63
64#define CONFIG_BOOTARGS "root=/dev/nfs rw " \
65 "nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \
66 "nfsaddrs=10.0.0.99:10.0.0.2"
67
68#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
69#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
70
71#undef CONFIG_WATCHDOG /* watchdog disabled */
72
73#define CONFIG_STATUS_LED 1 /* Status LED enabled */
74
75#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_IDE)
76#define CONFIG_MAC_PARTITION
77#define CONFIG_DOS_PARTITION
78
79#define CONFIG_BOOTP_MASK \
80 ((CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) & ~CONFIG_BOOTP_GATEWAY)
81
82/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
83#include <cmd_confdefs.h>
84
85/*----------------------------------------------------------------------*/
86
87/*
88 * Miscellaneous configurable options
89 */
90#define CFG_LONGHELP /* undef to save memory */
91#define CFG_PROMPT "=> " /* Monitor Command Prompt */
92#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
93#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
94#else
95#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
96#endif
97#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
98#define CFG_MAXARGS 16 /* max number of command args */
99#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
100
101#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
102#define CFG_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */
103
104#define CFG_LOAD_ADDR 0x00100000 /* default load address */
105
106#define CFG_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
107
108#define CFG_PB_SDRAM_CLKE 0x00008000 /* PB 16 */
109#define CFG_PB_ETH_POWERDOWN 0x00010000 /* PB 15 */
110#define CFG_PB_IDE_MOTOR 0x00020000 /* PB 14 */
111
112#define CFG_PC_ETH_RESET ((ushort)0x0010) /* PC 11 */
113#define CFG_PC_IDE_RESET ((ushort)0x0020) /* PC 10 */
114
115#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
116
117#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
118
119/*
120 * Low Level Configuration Settings
121 * (address mappings, register initial values, etc.)
122 * You should know what you are doing if you make changes here.
123 */
124/*-----------------------------------------------------------------------
125 * Internal Memory Mapped Register
126 */
127#define CFG_IMMR 0xFFF00000 /* was: 0xFF000000 */
128
129/*-----------------------------------------------------------------------
130 * Definitions for initial stack pointer and data area (in DPRAM)
131 */
132#define CFG_INIT_RAM_ADDR CFG_IMMR
133#if defined (CONFIG_IVMS8_16M)
134# define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
135#elif defined (CONFIG_IVMS8_32M)
136# define CFG_INIT_RAM_END 0x3000 /* End of used area in DPRAM */
137#elif defined (CONFIG_IVMS8_64M)
138# define CFG_INIT_RAM_END 0x3000 /* End of used area in DPRAM */
139#endif
140
141#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
142#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
143#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
144
145/*-----------------------------------------------------------------------
146 * Start addresses for the final memory configuration
147 * (Set up by the startup code)
148 * Please note that CFG_SDRAM_BASE _must_ start at 0
149 */
150#define CFG_SDRAM_BASE 0x00000000
151#define CFG_FLASH_BASE 0xFF000000
152#ifdef DEBUG
153#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
154#else
155#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
156#endif
157#define CFG_MONITOR_BASE CFG_FLASH_BASE
158#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
159
160/*
161 * For booting Linux, the board info and command line data
162 * have to be in the first 8 MB of memory, since this is
163 * the maximum mapped by the Linux kernel during initialization.
164 */
165#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
166/*-----------------------------------------------------------------------
167 * FLASH organization
168 */
169#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
170#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
171
172#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
173#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
174
175#define CFG_ENV_IS_IN_FLASH 1
176#define CFG_ENV_OFFSET 0x7A000 /* Offset of Environment Sector */
177#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
178/*-----------------------------------------------------------------------
179 * Cache Configuration
180 */
181#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
182#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
183#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
184#endif
185
186/*-----------------------------------------------------------------------
187 * SYPCR - System Protection Control 11-9
188 * SYPCR can only be written once after reset!
189 *-----------------------------------------------------------------------
190 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
191 */
192#if defined(CONFIG_WATCHDOG)
193# if defined (CONFIG_IVMS8_16M)
194# define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
195 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
196# elif defined (CONFIG_IVMS8_32M)
197# define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
198 SYPCR_SWE | SYPCR_SWP)
199# elif defined (CONFIG_IVMS8_64M)
200# define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
201 SYPCR_SWE | SYPCR_SWP)
202# endif
203#else
204# define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
205#endif
206
207/*-----------------------------------------------------------------------
208 * SIUMCR - SIU Module Configuration 11-6
209 *-----------------------------------------------------------------------
210 * PCMCIA config., multi-function pin tri-state
211 */
212/* EARB, DBGC and DBPC are initialised by the HCW */
213/* => 0x000000C0 */
214#define CFG_SIUMCR (SIUMCR_BSC | SIUMCR_GB5E)
215
216/*-----------------------------------------------------------------------
217 * TBSCR - Time Base Status and Control 11-26
218 *-----------------------------------------------------------------------
219 * Clear Reference Interrupt Status, Timebase freezing enabled
220 */
221#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
222
223/*-----------------------------------------------------------------------
224 * PISCR - Periodic Interrupt Status and Control 11-31
225 *-----------------------------------------------------------------------
226 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
227 */
228#define CFG_PISCR (PISCR_PS | PISCR_PITF)
229
230/*-----------------------------------------------------------------------
231 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
232 *-----------------------------------------------------------------------
233 * Reset PLL lock status sticky bit, timer expired status bit and timer
234 * interrupt status bit, set PLL multiplication factor !
235 */
236/* 0x00B0C0C0 */
237#define CFG_PLPRCR \
238 ( (11 << PLPRCR_MF_SHIFT) | \
239 PLPRCR_SPLSS | PLPRCR_TEXPS | /*PLPRCR_TMIST|*/ \
240 /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \
241 PLPRCR_CSR | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/ \
242 )
243
244/*-----------------------------------------------------------------------
245 * SCCR - System Clock and reset Control Register 15-27
246 *-----------------------------------------------------------------------
247 * Set clock output, timebase and RTC source and divider,
248 * power management and some other internal clocks
249 */
250#define SCCR_MASK SCCR_EBDF11
251/* 0x01800014 */
252#define CFG_SCCR (SCCR_COM01 | /*SCCR_TBS|*/ \
253 SCCR_RTDIV | SCCR_RTSEL | \
254 /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \
255 SCCR_EBDF00 | SCCR_DFSYNC00 | \
256 SCCR_DFBRG00 | SCCR_DFNL000 | \
257 SCCR_DFNH000 | SCCR_DFLCD101 | \
258 SCCR_DFALCD00)
259
260/*-----------------------------------------------------------------------
261 * RTCSC - Real-Time Clock Status and Control Register 11-27
262 *-----------------------------------------------------------------------
263 */
264/* 0x00C3 */
265#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
266
267
268/*-----------------------------------------------------------------------
269 * RCCR - RISC Controller Configuration Register 19-4
270 *-----------------------------------------------------------------------
271 */
272/* TIMEP=2 */
273#define CFG_RCCR 0x0200
274
275/*-----------------------------------------------------------------------
276 * RMDS - RISC Microcode Development Support Control Register
277 *-----------------------------------------------------------------------
278 */
279#define CFG_RMDS 0
280
281/*-----------------------------------------------------------------------
282 *
283 * Interrupt Levels
284 *-----------------------------------------------------------------------
285 */
286#define CFG_CPM_INTERRUPT 13 /* SIU_LEVEL6 */
287
288/*-----------------------------------------------------------------------
289 * PCMCIA stuff
290 *-----------------------------------------------------------------------
291 *
292 */
293#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
294#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
295#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
296#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
297#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
298#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
299#define CFG_PCMCIA_IO_ADDR (0xEC000000)
300#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
301
302/*-----------------------------------------------------------------------
303 * IDE/ATA stuff
304 *-----------------------------------------------------------------------
305 */
306#define CONFIG_IDE_8xx_DIRECT 1 /* PCMCIA interface required */
307#define CONFIG_IDE_RESET 1 /* reset for ide supported */
308
309#define CFG_IDE_MAXBUS 1 /* The IVMS8 has only 1 IDE bus */
310#define CFG_IDE_MAXDEVICE 1 /* ... and only 1 IDE device */
311
312#define CFG_ATA_BASE_ADDR 0xFE100000
313#define CFG_ATA_IDE0_OFFSET 0x0000
314#undef CFG_ATA_IDE1_OFFSET /* only one IDE bus available */
315
316#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
317#define CFG_ATA_REG_OFFSET 0x0080 /* Offset for normal register accesses */
318#define CFG_ATA_ALT_OFFSET 0x0100 /* Offset for alternate registers */
319
320/*-----------------------------------------------------------------------
321 *
322 *-----------------------------------------------------------------------
323 *
324 */
wdenk0f8c9762002-08-19 11:57:05 +0000325#define CFG_DER 0
326
327/*
328 * Init Memory Controller:
329 *
330 * BR0 and OR0 (FLASH)
331 */
332
333#define FLASH_BASE0_PRELIM 0xFF000000 /* FLASH bank #0 */
334
335/* used to re-map FLASH both when starting from SRAM or FLASH:
336 * restrict access enough to keep SRAM working (if any)
337 * but not too much to meddle with FLASH accesses
338 */
339/* EPROMs are 512kb */
340#define CFG_REMAP_OR_AM 0xFFF80000 /* OR addr mask */
341#define CFG_PRELIM_OR_AM 0xFFF80000 /* OR addr mask */
342
343/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
344#define CFG_OR_TIMING_FLASH (/* OR_CSNT_SAM | */ OR_ACS_DIV4 | OR_BI | \
345 OR_SCY_5_CLK | OR_EHTR)
346
347#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
348#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
349/* 16 bit, bank valid */
350#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
351
352/*
353 * BR1/OR1 - ELIC SACCO bank @ 0xFE000000
354 *
355 * AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1
356 */
357#define ELIC_SACCO_BASE 0xFE000000
358#define ELIC_SACCO_OR_AM 0xFFFF8000
359#define ELIC_SACCO_TIMING 0x00000F26
360
361#define CFG_OR1 (ELIC_SACCO_OR_AM | ELIC_SACCO_TIMING)
362#define CFG_BR1 ((ELIC_SACCO_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
363
364/*
365 * BR2/OR2 - ELIC EPIC bank @ 0xFE008000
366 *
367 * AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1
368 */
369#define ELIC_EPIC_BASE 0xFE008000
370#define ELIC_EPIC_OR_AM 0xFFFF8000
371#define ELIC_EPIC_TIMING 0x00000F26
372
373#define CFG_OR2 (ELIC_EPIC_OR_AM | ELIC_EPIC_TIMING)
374#define CFG_BR2 ((ELIC_EPIC_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
375
376/*
377 * BR3/OR3: SDRAM
378 *
379 * Multiplexed addresses, GPL5 output to GPL5_A (don't care)
380 */
381#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */
382#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */
383#define SDRAM_TIMING 0x00000A00 /* SDRAM-Timing */
384
385#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */
386
387#define CFG_OR3_PRELIM (SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
388#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V )
389
390/*
391 * BR4/OR4: not used
392 */
393
394/*
395 * BR5/OR5: SHARC ADSP-2165L
396 *
397 * AM=0xFFC00 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=3 BIH=1 SCY=0 SETA=0 TRLX=0 EHTR=0
398 */
399#define SHARC_BASE 0xFE400000
400#define SHARC_OR_AM 0xFFC00000
401#define SHARC_TIMING 0x00000700
402
403#define CFG_OR5 (SHARC_OR_AM | SHARC_TIMING )
404#define CFG_BR5 ((SHARC_BASE & BR_BA_MSK) | BR_PS_32 | BR_MS_UPMA | BR_V )
405
406/*
407 * Memory Periodic Timer Prescaler
408 */
409
410/* periodic timer for refresh */
wdenk2535d602003-07-17 23:16:40 +0000411#define CFG_MBMR_PTB 204
wdenk0f8c9762002-08-19 11:57:05 +0000412
413/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
414#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
415#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
416
417/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
418#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
419#if defined (CONFIG_IVMS8_16M)
420 #define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
421#elif defined (CONFIG_IVMS8_32M)
422#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
423#elif defined (CONFIG_IVMS8_64M)
424#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV8 /* setting for 1 bank */
425#endif
426
427
428/*
429 * MBMR settings for SDRAM
430 */
431
432#if defined (CONFIG_IVMS8_16M)
433 /* 8 column SDRAM */
wdenk2535d602003-07-17 23:16:40 +0000434# define CFG_MBMR_8COL ((CFG_MBMR_PTB << MBMR_PTB_SHIFT) | \
435 MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 | \
436 MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X)
wdenk0f8c9762002-08-19 11:57:05 +0000437#elif defined (CONFIG_IVMS8_32M)
438/* 128 MBit SDRAM */
wdenk2535d602003-07-17 23:16:40 +0000439#define CFG_MBMR_8COL ((CFG_MBMR_PTB << MBMR_PTB_SHIFT) | \
440 MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 | \
441 MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X)
wdenk0f8c9762002-08-19 11:57:05 +0000442#elif defined (CONFIG_IVMS8_64M)
443/* 128 MBit SDRAM */
wdenk2535d602003-07-17 23:16:40 +0000444#define CFG_MBMR_8COL ((CFG_MBMR_PTB << MBMR_PTB_SHIFT) | \
445 MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 | \
446 MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X)
wdenk0f8c9762002-08-19 11:57:05 +0000447
448#endif
449
450/*
451 * Internal Definitions
452 *
453 * Boot Flags
454 */
455#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
456#define BOOTFLAG_WARM 0x02 /* Software reboot */
457
458#endif /* __CONFIG_H */