Masahiro Yamada | dd84058 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 1 | CONFIG_PPC=y |
Tom Rini | 278b90c | 2018-02-03 12:10:38 -0500 | [diff] [blame] | 2 | CONFIG_SYS_TEXT_BASE=0xF0000000 |
Mario Six | ff3bb0c | 2019-01-21 09:17:53 +0100 | [diff] [blame] | 3 | CONFIG_SYS_CLK_FREQ=66000000 |
Masahiro Yamada | dd84058 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 4 | CONFIG_MPC83xx=y |
Mario Six | 93de253 | 2019-01-21 09:17:56 +0100 | [diff] [blame] | 5 | CONFIG_HIGH_BATS=y |
Mario Six | 71c7900 | 2019-01-21 09:17:33 +0100 | [diff] [blame] | 6 | CONFIG_TARGET_KMOPTI2=y |
Mario Six | 21c1502 | 2019-01-21 09:17:54 +0100 | [diff] [blame] | 7 | CONFIG_CORE_PLL_RATIO_25_1=y |
| 8 | CONFIG_QUICC_MULT_FACTOR_3=y |
| 9 | CONFIG_BOOT_MEMORY_SPACE_LOW=y |
| 10 | CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y |
Mario Six | 30915ab | 2019-01-21 09:17:57 +0100 | [diff] [blame] | 11 | CONFIG_BAT0=y |
| 12 | CONFIG_BAT0_NAME="SDRAM" |
| 13 | CONFIG_BAT0_BASE=0x00000000 |
| 14 | CONFIG_BAT0_LENGTH_256_MBYTES=y |
| 15 | CONFIG_BAT0_ACCESS_RW=y |
| 16 | CONFIG_BAT0_ICACHE_INHIBITED=y |
| 17 | CONFIG_BAT0_ICACHE_GUARDED=y |
| 18 | CONFIG_BAT0_DCACHE_INHIBITED=y |
| 19 | CONFIG_BAT0_DCACHE_GUARDED=y |
| 20 | CONFIG_BAT0_USER_MODE_VALID=y |
| 21 | CONFIG_BAT0_SUPERVISOR_MODE_VALID=y |
| 22 | CONFIG_BAT1=y |
| 23 | CONFIG_BAT1_NAME="IMMR" |
| 24 | CONFIG_BAT1_BASE=0xE0000000 |
| 25 | CONFIG_BAT1_LENGTH_4_MBYTES=y |
| 26 | CONFIG_BAT1_ACCESS_RW=y |
| 27 | CONFIG_BAT1_ICACHE_INHIBITED=y |
| 28 | CONFIG_BAT1_ICACHE_GUARDED=y |
| 29 | CONFIG_BAT1_DCACHE_INHIBITED=y |
| 30 | CONFIG_BAT1_DCACHE_GUARDED=y |
| 31 | CONFIG_BAT1_USER_MODE_VALID=y |
| 32 | CONFIG_BAT1_SUPERVISOR_MODE_VALID=y |
| 33 | CONFIG_BAT2=y |
| 34 | CONFIG_BAT2_NAME="KMBEC_FPGA" |
| 35 | CONFIG_BAT2_BASE=0xE8000000 |
| 36 | CONFIG_BAT2_LENGTH_128_MBYTES=y |
| 37 | CONFIG_BAT2_ACCESS_RW=y |
| 38 | CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y |
| 39 | CONFIG_BAT2_DCACHE_INHIBITED=y |
| 40 | CONFIG_BAT2_DCACHE_GUARDED=y |
| 41 | CONFIG_BAT2_USER_MODE_VALID=y |
| 42 | CONFIG_BAT2_SUPERVISOR_MODE_VALID=y |
| 43 | CONFIG_BAT3=y |
| 44 | CONFIG_BAT3_NAME="FLASH" |
| 45 | CONFIG_BAT3_BASE=0xF0000000 |
| 46 | CONFIG_BAT3_LENGTH_256_MBYTES=y |
| 47 | CONFIG_BAT3_ACCESS_RW=y |
| 48 | CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y |
| 49 | CONFIG_BAT3_DCACHE_INHIBITED=y |
| 50 | CONFIG_BAT3_DCACHE_GUARDED=y |
| 51 | CONFIG_BAT3_USER_MODE_VALID=y |
| 52 | CONFIG_BAT3_SUPERVISOR_MODE_VALID=y |
| 53 | CONFIG_BAT4=y |
| 54 | CONFIG_BAT4_NAME="STACK_IN_DCACHE" |
| 55 | CONFIG_BAT4_BASE=0xE6000000 |
| 56 | CONFIG_BAT4_ACCESS_RW=y |
| 57 | CONFIG_BAT4_USER_MODE_VALID=y |
| 58 | CONFIG_BAT4_SUPERVISOR_MODE_VALID=y |
| 59 | CONFIG_BAT5=y |
| 60 | CONFIG_BAT5_NAME="APP1" |
| 61 | CONFIG_BAT5_BASE=0xA0000000 |
| 62 | CONFIG_BAT5_LENGTH_256_MBYTES=y |
| 63 | CONFIG_BAT5_ACCESS_RW=y |
| 64 | CONFIG_BAT5_ICACHE_MEMORYCOHERENCE=y |
| 65 | CONFIG_BAT5_DCACHE_INHIBITED=y |
| 66 | CONFIG_BAT5_DCACHE_GUARDED=y |
| 67 | CONFIG_BAT5_USER_MODE_VALID=y |
| 68 | CONFIG_BAT5_SUPERVISOR_MODE_VALID=y |
| 69 | CONFIG_BAT6=y |
| 70 | CONFIG_BAT6_NAME="APP2" |
| 71 | CONFIG_BAT6_BASE=0xB0000000 |
| 72 | CONFIG_BAT6_LENGTH_256_MBYTES=y |
| 73 | CONFIG_BAT6_ACCESS_RW=y |
| 74 | CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y |
| 75 | CONFIG_BAT6_DCACHE_INHIBITED=y |
| 76 | CONFIG_BAT6_DCACHE_GUARDED=y |
| 77 | CONFIG_BAT6_USER_MODE_VALID=y |
| 78 | CONFIG_BAT6_SUPERVISOR_MODE_VALID=y |
Mario Six | 9c5df7a | 2019-01-21 09:17:58 +0100 | [diff] [blame] | 79 | CONFIG_LBLAW0=y |
| 80 | CONFIG_LBLAW0_BASE=0xF0000000 |
| 81 | CONFIG_LBLAW0_NAME="FLASH" |
| 82 | CONFIG_LBLAW0_LENGTH_256_MBYTES=y |
| 83 | CONFIG_LBLAW1=y |
| 84 | CONFIG_LBLAW1_BASE=0xE8000000 |
| 85 | CONFIG_LBLAW1_NAME="KMBEC_FPGA" |
| 86 | CONFIG_LBLAW1_LENGTH_128_MBYTES=y |
| 87 | CONFIG_LBLAW2=y |
| 88 | CONFIG_LBLAW2_BASE=0xA0000000 |
| 89 | CONFIG_LBLAW2_NAME="APP1" |
| 90 | CONFIG_LBLAW2_LENGTH_256_MBYTES=y |
| 91 | CONFIG_LBLAW3=y |
| 92 | CONFIG_LBLAW3_BASE=0xB0000000 |
| 93 | CONFIG_LBLAW3_NAME="APP2" |
| 94 | CONFIG_LBLAW3_LENGTH_256_MBYTES=y |
Mario Six | be5abb0 | 2019-01-21 09:18:09 +0100 | [diff] [blame] | 95 | CONFIG_HID0_FINAL_EMCP=y |
| 96 | CONFIG_HID0_FINAL_ICE=y |
| 97 | CONFIG_HID2_HBE=y |
Mario Six | 73df96a | 2019-01-21 09:18:12 +0100 | [diff] [blame] | 98 | CONFIG_ACR_PIPE_DEP_4=y |
| 99 | CONFIG_ACR_RPTCNT_4=y |
| 100 | CONFIG_ACR_APARK_MASTER=y |
| 101 | CONFIG_ACR_PARKM_USB_I2C1_BOOT=y |
Simon Glass | 73223f0 | 2016-02-22 22:55:43 -0700 | [diff] [blame] | 102 | CONFIG_OF_BOARD_SETUP=y |
| 103 | CONFIG_OF_STDOUT_VIA_ALIAS=y |
Adam Ford | 8ccf98b | 2018-07-29 13:13:29 -0500 | [diff] [blame] | 104 | CONFIG_MISC_INIT_R=y |
Heiko Schocher | 9dd1d0a | 2016-09-09 08:12:49 +0200 | [diff] [blame] | 105 | CONFIG_VERSION_VARIABLE=y |
Mario Six | 02ddc14 | 2018-03-28 14:38:15 +0200 | [diff] [blame] | 106 | CONFIG_BOARD_EARLY_INIT_R=y |
Mario Six | 2aeb22d | 2018-03-28 14:38:16 +0200 | [diff] [blame] | 107 | CONFIG_LAST_STAGE_INIT=y |
Tom Rini | adad96e | 2016-04-21 21:37:19 -0400 | [diff] [blame] | 108 | CONFIG_HUSH_PARSER=y |
Tom Rini | 78d1e1d | 2016-04-22 16:41:25 -0400 | [diff] [blame] | 109 | CONFIG_AUTOBOOT_KEYED=y |
| 110 | CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n" |
| 111 | CONFIG_AUTOBOOT_STOP_STR=" " |
Tuomas Tynkkynen | ad12dc1 | 2017-10-08 21:48:01 +0300 | [diff] [blame] | 112 | CONFIG_CMD_IMLS=y |
Tom Rini | 89cb2b5 | 2016-04-24 17:29:26 -0400 | [diff] [blame] | 113 | CONFIG_CMD_ASKENV=y |
| 114 | CONFIG_CMD_GREPENV=y |
Simon Glass | a1dc980 | 2017-05-17 03:25:10 -0600 | [diff] [blame] | 115 | CONFIG_CMD_EEPROM=y |
Tom Rini | 78d1e1d | 2016-04-22 16:41:25 -0400 | [diff] [blame] | 116 | CONFIG_CMD_I2C=y |
| 117 | CONFIG_CMD_DHCP=y |
Tom Rini | 89cb2b5 | 2016-04-24 17:29:26 -0400 | [diff] [blame] | 118 | CONFIG_CMD_MII=y |
Tom Rini | 78d1e1d | 2016-04-22 16:41:25 -0400 | [diff] [blame] | 119 | CONFIG_CMD_PING=y |
Simon Glass | b8682a7 | 2017-05-17 03:25:37 -0600 | [diff] [blame] | 120 | CONFIG_CMD_JFFS2=y |
Tom Rini | cbabe7f | 2018-11-13 19:54:45 -0500 | [diff] [blame] | 121 | CONFIG_CMD_MTDPARTS=y |
Tom Rini | 43ede0b | 2017-10-22 17:55:07 -0400 | [diff] [blame] | 122 | CONFIG_MTDIDS_DEFAULT="nor0=boot" |
| 123 | CONFIG_MTDPARTS_DEFAULT="mtdparts=boot:768k(u-boot),128k(env),128k(envred),-(ubi0);" |
Heiko Schocher | 8f2fe0c | 2016-09-21 07:58:19 +0200 | [diff] [blame] | 124 | CONFIG_CMD_UBI=y |
Tom Rini | d56b4b1 | 2017-07-22 18:36:16 -0400 | [diff] [blame] | 125 | # CONFIG_CMD_UBIFS is not set |
Lukasz Majewski | d1ec946 | 2018-02-09 23:50:57 +0100 | [diff] [blame] | 126 | CONFIG_BOOTCOUNT_LIMIT=y |
Alex Kiernan | ca0d535 | 2018-07-21 20:25:33 +0000 | [diff] [blame] | 127 | CONFIG_BOOTCOUNT_BOOTLIMIT=3 |
Tom Rini | 39bcbb7 | 2018-02-24 16:50:41 -0500 | [diff] [blame] | 128 | CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8 |
Tom Rini | 8728c97 | 2017-03-13 13:48:42 -0400 | [diff] [blame] | 129 | # CONFIG_MMC is not set |
Masahiro Yamada | e856bdc | 2017-02-11 22:43:54 +0900 | [diff] [blame] | 130 | CONFIG_MTD_NOR_FLASH=y |
Adam Ford | 9c5b009 | 2018-07-07 22:18:22 -0500 | [diff] [blame] | 131 | CONFIG_MTD_DEVICE=y |
Adam Ford | 2fe88d4 | 2018-10-14 15:10:50 -0500 | [diff] [blame] | 132 | CONFIG_FLASH_CFI_DRIVER=y |
| 133 | CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y |
| 134 | CONFIG_FLASH_CFI_MTD=y |
| 135 | CONFIG_SYS_FLASH_PROTECTION=y |
| 136 | CONFIG_SYS_FLASH_CFI=y |
Tom Rini | af27382 | 2016-10-26 17:15:37 -0400 | [diff] [blame] | 137 | # CONFIG_PCI is not set |
Thomas Chou | 9e39003 | 2015-11-19 21:48:14 +0800 | [diff] [blame] | 138 | CONFIG_SYS_NS16550=y |
Simon Glass | 69e173e | 2016-02-22 22:55:42 -0700 | [diff] [blame] | 139 | CONFIG_OF_LIBFDT=y |
Mario Six | fe7d654 | 2019-01-21 09:18:03 +0100 | [diff] [blame] | 140 | CONFIG_ELBC_BR0_OR0=y |
| 141 | CONFIG_BR0_OR0_NAME="FLASH" |
| 142 | CONFIG_BR0_OR0_BASE=0xF0000000 |
| 143 | CONFIG_BR0_MACHINE_GPCM=y |
| 144 | CONFIG_BR0_PORTSIZE_16BIT=y |
| 145 | CONFIG_OR0_AM_256_MBYTES=y |
| 146 | CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y |
| 147 | CONFIG_OR0_CSNT_EARLIER=y |
| 148 | CONFIG_OR0_EAD_EXTRA=y |
| 149 | CONFIG_OR0_SCY_5=y |
| 150 | CONFIG_OR0_TRLX_RELAXED=y |
| 151 | CONFIG_ELBC_BR1_OR1=y |
| 152 | CONFIG_BR1_OR1_NAME="KMBEC_FPGA" |
| 153 | CONFIG_BR1_OR1_BASE=0xE8000000 |
| 154 | CONFIG_BR1_MACHINE_GPCM=y |
| 155 | CONFIG_BR1_PORTSIZE_8BIT=y |
| 156 | CONFIG_OR1_AM_128_MBYTES=y |
| 157 | CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y |
| 158 | CONFIG_OR1_CSNT_EARLIER=y |
| 159 | CONFIG_OR1_EAD_EXTRA=y |
| 160 | CONFIG_OR1_SCY_2=y |
| 161 | CONFIG_OR1_TRLX_RELAXED=y |
| 162 | CONFIG_ELBC_BR2_OR2=y |
| 163 | CONFIG_BR2_OR2_NAME="APP1" |
| 164 | CONFIG_BR2_OR2_BASE=0xA0000000 |
| 165 | CONFIG_BR2_MACHINE_GPCM=y |
| 166 | CONFIG_BR2_PORTSIZE_8BIT=y |
| 167 | CONFIG_OR2_AM_256_MBYTES=y |
| 168 | CONFIG_OR2_ACS_QUARTER_CYCLE_EARLIER=y |
| 169 | CONFIG_OR2_CSNT_EARLIER=y |
| 170 | CONFIG_OR2_EAD_EXTRA=y |
| 171 | CONFIG_OR2_SCY_2=y |
| 172 | CONFIG_OR2_TRLX_RELAXED=y |
| 173 | CONFIG_OR2_EHTR_4_CYCLE=y |
| 174 | CONFIG_ELBC_BR3_OR3=y |
| 175 | CONFIG_BR3_OR3_NAME="APP2" |
| 176 | CONFIG_BR3_OR3_BASE=0xB0000000 |
| 177 | CONFIG_BR3_MACHINE_GPCM=y |
| 178 | CONFIG_BR3_PORTSIZE_16BIT=y |
| 179 | CONFIG_OR3_AM_256_MBYTES=y |
| 180 | CONFIG_OR3_SCY_4=y |
| 181 | CONFIG_OR3_EHTR_NORMAL=y |
Mario Six | 7c2e535 | 2019-01-21 09:18:14 +0100 | [diff] [blame] | 182 | CONFIG_LCRR_DBYP_PLL_BYPASSED=y |
| 183 | CONFIG_LCRR_EADC_1=y |
| 184 | CONFIG_LCRR_CLKDIV_2=y |