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Shengzhou Liuc4d0e812013-11-22 17:39:11 +08001/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#ifndef __DDR_H__
8#define __DDR_H__
9struct board_specific_parameters {
10 u32 n_ranks;
11 u32 datarate_mhz_high;
12 u32 rank_gb;
13 u32 clk_adjust;
14 u32 wrlvl_start;
15 u32 wrlvl_ctl_2;
16 u32 wrlvl_ctl_3;
Shengzhou Liuc4d0e812013-11-22 17:39:11 +080017};
18
19/*
20 * These tables contain all valid speeds we want to override with board
21 * specific parameters. datarate_mhz_high values need to be in ascending order
22 * for each n_ranks group.
23 */
24
25static const struct board_specific_parameters udimm0[] = {
26 /*
27 * memory controller 0
Shengzhou Liu40483e12014-05-20 12:08:20 +080028 * num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
29 * ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
Shengzhou Liuc4d0e812013-11-22 17:39:11 +080030 */
Shengzhou Liue04f9d02016-05-04 10:20:22 +080031 {2, 1200, 0, 10, 7, 0x0708090a, 0x0b0c0d09},
32 {2, 1400, 0, 10, 7, 0x08090a0c, 0x0d0e0f0a},
33 {2, 1700, 0, 10, 8, 0x090a0b0c, 0x0e10110c},
34 {2, 1900, 0, 10, 8, 0x090b0c0f, 0x1012130d},
35 {2, 2140, 0, 10, 8, 0x090b0c0f, 0x1012130d},
36 {1, 1200, 0, 10, 7, 0x0808090a, 0x0b0c0c0a},
37 {1, 1500, 0, 10, 6, 0x07070809, 0x0a0b0b09},
38 {1, 1600, 0, 10, 8, 0x090b0b0d, 0x0d0e0f0b},
39 {1, 1700, 0, 8, 8, 0x080a0a0c, 0x0c0d0e0a},
40 {1, 1900, 0, 10, 8, 0x090a0c0d, 0x0e0f110c},
41 {1, 2140, 0, 8, 8, 0x090a0b0d, 0x0e0f110b},
Shengzhou Liuc4d0e812013-11-22 17:39:11 +080042 {}
43};
44
45static const struct board_specific_parameters rdimm0[] = {
46 /*
47 * memory controller 0
Shengzhou Liu3fdc8272014-01-13 13:01:06 +080048 * num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
49 * ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
Shengzhou Liuc4d0e812013-11-22 17:39:11 +080050 */
Shengzhou Liu3fdc8272014-01-13 13:01:06 +080051 /* TODO: need tuning these parameters if RDIMM is used */
Shengzhou Liue04f9d02016-05-04 10:20:22 +080052 {4, 1350, 0, 10, 9, 0x08070605, 0x06070806},
53 {4, 1666, 0, 10, 11, 0x0a080706, 0x07090906},
54 {4, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07},
55 {2, 1350, 0, 10, 9, 0x08070605, 0x06070806},
56 {2, 1666, 0, 10, 11, 0x0a090806, 0x08090a06},
57 {2, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07},
58 {1, 1350, 0, 10, 9, 0x08070605, 0x06070806},
59 {1, 1666, 0, 10, 11, 0x0a090806, 0x08090a06},
60 {1, 2140, 0, 8, 12, 0x0b090807, 0x080a0b07},
Shengzhou Liuc4d0e812013-11-22 17:39:11 +080061 {}
62};
63
Shengzhou Liuc4d0e812013-11-22 17:39:11 +080064static const struct board_specific_parameters *udimms[] = {
65 udimm0,
66};
67
Shengzhou Liuc4d0e812013-11-22 17:39:11 +080068static const struct board_specific_parameters *rdimms[] = {
69 rdimm0,
70};
Shengzhou Liuc4d0e812013-11-22 17:39:11 +080071#endif