blob: f0ed16cd93ff6f43a413158e9c4c737494605fd9 [file] [log] [blame]
wdenkafd7f3d2002-11-03 01:41:26 +00001/*
2 * (C) Copyright 2000
3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
5 *
6 * (C) Copyright 2001
7 * Advent Networks, Inc. <http://www.adventnetworks.com>
8 * Jay Monkman <jtm@smoothsmoothie.com>
9 *
10 * (C) Copyright 2001
11 * Advent Networks, Inc. <http://www.adventnetworks.com>
12 * Oliver Brown <oliverb@alumni.utexas.net>
13 *
Wolfgang Denk1a459662013-07-08 09:37:19 +020014 * SPDX-License-Identifier: GPL-2.0+
wdenkafd7f3d2002-11-03 01:41:26 +000015 */
16
17/*********************************************************************/
18/* DESCRIPTION:
19 * This file contains the board routines for the GW8260 board.
20 *
21 * MODULE DEPENDENCY:
22 * None
23 *
24 * RESTRICTIONS/LIMITATIONS:
25 * None
26 *
27 * Copyright (c) 2001, Advent Networks, Inc.
28 */
29/*********************************************************************/
30
31#include <common.h>
32#include <ioports.h>
33#include <mpc8260.h>
34
35/*
36 * I/O Port configuration table
37 *
38 */
39const iop_conf_t iop_conf_tab[4][32] = {
40
41 /* Port A configuration */
42 { /* conf ppar psor pdir podr pdat */
43 /* PA31 */ { 1, 0, 0, 1, 0, 0 }, /* TP14 */
44 /* PA30 */ { 1, 1, 1, 1, 0, 0 }, /* US_RTS */
45 /* PA29 */ { 1, 0, 0, 1, 0, 1 }, /* LSSI_DATA */
46 /* PA28 */ { 1, 0, 0, 1, 0, 1 }, /* LSSI_CLK */
47 /* PA27 */ { 1, 0, 0, 1, 0, 0 }, /* TP12 */
48 /* PA26 */ { 1, 0, 0, 0, 0, 0 }, /* IO_STATUS */
49 /* PA25 */ { 1, 0, 0, 0, 0, 0 }, /* IO_CLOCK */
50 /* PA24 */ { 1, 0, 0, 0, 0, 0 }, /* IO_CONFIG */
51 /* PA23 */ { 1, 0, 0, 0, 0, 0 }, /* IO_DONE */
52 /* PA22 */ { 1, 0, 0, 0, 0, 0 }, /* IO_DATA */
53 /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* US_TXD3 */
54 /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* US_TXD2 */
55 /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* US_TXD1 */
56 /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* US_TXD0 */
57 /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* DS_RXD0 */
58 /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* DS_RXD1 */
59 /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* DS_RXD2 */
60 /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* DS_RXD3 */
61 /* PA13 */ { 1, 0, 0, 1, 0, 0 }, /* SPARE7 */
62 /* PA12 */ { 1, 0, 0, 1, 0, 0 }, /* SPARE6 */
63 /* PA11 */ { 1, 0, 0, 1, 0, 0 }, /* SPARE5 */
64 /* PA10 */ { 1, 0, 0, 1, 0, 0 }, /* SPARE4 */
65 /* PA9 */ { 1, 0, 0, 1, 0, 0 }, /* SPARE3 */
66 /* PA8 */ { 1, 0, 0, 1, 0, 0 }, /* SPARE2 */
67 /* PA7 */ { 1, 0, 0, 0, 0, 0 }, /* LSSI_IN */
68 /* PA6 */ { 1, 0, 0, 1, 0, 0 }, /* SPARE0 */
69 /* PA5 */ { 1, 0, 0, 1, 0, 0 }, /* DEMOD_RESET_ */
70 /* PA4 */ { 1, 0, 0, 1, 0, 0 }, /* MOD_RESET_ */
71 /* PA3 */ { 1, 0, 0, 1, 0, 0 }, /* IO_RESET */
72 /* PA2 */ { 1, 0, 0, 1, 0, 0 }, /* TX_ENABLE */
73 /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* RX_LOCK */
74 /* PA0 */ { 1, 0, 0, 1, 0, 1 } /* MPC_RESET_ */
75 },
76
77 /* Port B configuration */
78 { /* conf ppar psor pdir podr pdat */
79 /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FETH0_TX_ER */
80 /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FETH0_RX_DV */
81 /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FETH0_TX_EN */
82 /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FETH0_RX_ER */
83 /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FETH0_COL */
84 /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FETH0_CRS */
85 /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FETH0_TXD3 */
86 /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FETH0_TXD2 */
87 /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FETH0_TXD1 */
88 /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FETH0_TXD0 */
89 /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FETH0_RXD0 */
90 /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FETH0_RXD1 */
91 /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FETH0_RXD2 */
92 /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FETH0_RXD3 */
93 /* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FETH1_RX_DV */
94 /* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FETH1_RX_ER */
95 /* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FETH1_TX_ER */
96 /* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FETH1_TX_EN */
97 /* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FETH1_COL */
98 /* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FETH1_CRS */
99 /* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FETH1_RXD3 */
100 /* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FETH1_RXD2 */
101 /* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FETH1_RXD1 */
102 /* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FETH1_RXD0 */
103 /* PB7 */ { 1, 1, 0, 1, 0, 0 }, /* FETH1_TXD0 */
104 /* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FETH1_TXD1 */
105 /* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FETH1_TXD2 */
106 /* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FETH1_TXD3 */
107 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
108 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
109 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
110 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
111 },
112
113 /* Port C */
114 { /* conf ppar psor pdir podr pdat */
115 /* PC31 */ { 1, 0, 0, 1, 0, 1 }, /* FAST_RESET_ */
116 /* PC30 */ { 1, 0, 0, 1, 0, 1 }, /* FAST_PAUSE_ */
117 /* PC29 */ { 1, 0, 0, 1, 0, 0 }, /* FAST_SLEW1 */
118 /* PC28 */ { 1, 0, 0, 1, 0, 0 }, /* FAST_SLEW0 */
119 /* PC27 */ { 1, 0, 0, 1, 0, 0 }, /* TP13 */
120 /* PC26 */ { 1, 0, 0, 0, 0, 0 }, /* RXDECDFLG */
121 /* PC25 */ { 1, 0, 0, 0, 0, 0 }, /* RXACQFAIL */
122 /* PC24 */ { 1, 0, 0, 0, 0, 0 }, /* RXACQFLG */
123 /* PC23 */ { 1, 0, 0, 1, 0, 0 }, /* WD_TCL */
124 /* PC22 */ { 1, 0, 0, 1, 0, 0 }, /* WD_EN */
125 /* PC21 */ { 1, 0, 0, 1, 0, 0 }, /* US_TXCLK */
126 /* PC20 */ { 1, 0, 0, 0, 0, 0 }, /* DS_RXCLK */
127 /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FETH0_RX_CLK */
128 /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FETH0_TX_CLK */
129 /* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* FETH1_RX_CLK */
130 /* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* FETH1_TX_CLK */
131 /* PC15 */ { 1, 0, 0, 1, 0, 0 }, /* TX_SHUTDOWN_ */
132 /* PC14 */ { 1, 0, 0, 0, 0, 0 }, /* RS_232_DTR_ */
133 /* PC13 */ { 1, 0, 0, 0, 0, 0 }, /* TXERR */
134 /* PC12 */ { 1, 0, 0, 1, 0, 1 }, /* FETH1_MDDIS */
135 /* PC11 */ { 1, 0, 0, 1, 0, 1 }, /* FETH0_MDDIS */
136 /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* MDC */
137 /* PC9 */ { 1, 0, 0, 1, 1, 1 }, /* MDIO */
138 /* PC8 */ { 1, 0, 0, 1, 1, 1 }, /* SER_NUM */
139 /* PC7 */ { 1, 1, 0, 0, 0, 0 }, /* US_CTS */
140 /* PC6 */ { 1, 1, 0, 0, 0, 0 }, /* DS_CD_ */
141 /* PC5 */ { 1, 0, 0, 1, 0, 0 }, /* FETH1_PWRDWN */
142 /* PC4 */ { 1, 0, 0, 1, 0, 0 }, /* FETH0_PWRDWN */
143 /* PC3 */ { 1, 0, 0, 1, 0, 0 }, /* MPULED3 */
144 /* PC2 */ { 1, 0, 0, 1, 0, 0 }, /* MPULED2 */
145 /* PC1 */ { 1, 0, 0, 1, 0, 0 }, /* MPULED1 */
146 /* PC0 */ { 1, 0, 0, 1, 0, 1 }, /* MPULED0 */
147 },
148
149 /* Port D */
150 { /* conf ppar psor pdir podr pdat */
151 /* PD31 */ { 1, 0, 0, 0, 0, 0 }, /* not used */
152 /* PD30 */ { 1, 0, 0, 0, 0, 0 }, /* not used */
153 /* PD29 */ { 1, 0, 0, 0, 0, 0 }, /* not used */
154 /* PD28 */ { 1, 0, 0, 0, 0, 0 }, /* not used */
155 /* PD27 */ { 1, 0, 0, 0, 0, 0 }, /* not used */
156 /* PD26 */ { 1, 0, 0, 0, 0, 0 }, /* not used */
157 /* PD25 */ { 1, 0, 0, 0, 0, 0 }, /* not used */
158 /* PD24 */ { 1, 0, 0, 0, 0, 0 }, /* not used */
159 /* PD23 */ { 1, 0, 0, 0, 0, 0 }, /* not used */
160 /* PD22 */ { 1, 0, 0, 0, 0, 0 }, /* not used */
161 /* PD21 */ { 1, 0, 0, 0, 0, 0 }, /* not used */
162 /* PD20 */ { 1, 0, 0, 0, 0, 0 }, /* not used */
163 /* PD19 */ { 1, 1, 1, 0, 0, 0 }, /* not used */
164 /* PD18 */ { 1, 1, 1, 0, 0, 0 }, /* not used */
165 /* PD17 */ { 1, 1, 1, 0, 0, 0 }, /* not used */
166 /* PD16 */ { 1, 1, 1, 0, 0, 0 }, /* not used */
167 /* PD15 */ { 1, 1, 1, 0, 1, 1 }, /* SDRAM_SDA */
168 /* PD14 */ { 1, 1, 1, 0, 1, 1 }, /* SDRAM_SCL */
169 /* PD13 */ { 1, 0, 0, 1, 0, 0 }, /* MPULED7 */
170 /* PD12 */ { 1, 0, 0, 1, 0, 0 }, /* MPULED6 */
171 /* PD11 */ { 1, 0, 0, 1, 0, 0 }, /* MPULED5 */
172 /* PD10 */ { 1, 0, 0, 1, 0, 0 }, /* MPULED4 */
173 /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* RS232_TXD */
174 /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* RD232_RXD */
175 /* PD7 */ { 1, 0, 0, 0, 0, 0 }, /* not used */
176 /* PD6 */ { 1, 0, 0, 0, 0, 0 }, /* not used */
177 /* PD5 */ { 1, 0, 0, 0, 0, 0 }, /* not used */
178 /* PD4 */ { 1, 0, 0, 0, 0, 0 }, /* not used */
179 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
180 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
181 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
182 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
183 }
184};
185
186/*********************************************************************/
187/* NAME: checkboard() - Displays the board type and serial number */
188/* */
189/* OUTPUTS: */
190/* Displays the board type and serial number */
191/* */
192/* RETURNS: */
193/* Always returns 1 */
194/* */
195/* RESTRICTIONS/LIMITATIONS: */
196/* */
197/* */
198/*********************************************************************/
wdenkbf9e3b32004-02-12 00:47:09 +0000199int checkboard (void)
wdenkafd7f3d2002-11-03 01:41:26 +0000200{
Wolfgang Denkf0c0b3a2011-05-04 10:32:28 +0000201 char buf[64];
202 int i = getenv_f("serial#", buf, sizeof(buf));
wdenkafd7f3d2002-11-03 01:41:26 +0000203
wdenkbf9e3b32004-02-12 00:47:09 +0000204 puts ("Board: Advent Networks gw8260\n");
205
Wolfgang Denkf0c0b3a2011-05-04 10:32:28 +0000206 if (i > 0) {
207 printf("SN: %s\n", buf);
wdenkbf9e3b32004-02-12 00:47:09 +0000208 }
209 return 0;
wdenkafd7f3d2002-11-03 01:41:26 +0000210}
211
212
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#if defined (CONFIG_SYS_DRAM_TEST)
wdenkafd7f3d2002-11-03 01:41:26 +0000214/*********************************************************************/
215/* NAME: move64() - moves a double word (64-bit) */
216/* */
217/* DESCRIPTION: */
218/* this function performs a double word move from the data at */
219/* the source pointer to the location at the destination pointer. */
220/* */
221/* INPUTS: */
222/* unsigned long long *src - pointer to data to move */
223/* */
224/* OUTPUTS: */
225/* unsigned long long *dest - pointer to locate to move data */
226/* */
227/* RETURNS: */
228/* None */
229/* */
230/* RESTRICTIONS/LIMITATIONS: */
231/* May cloober fr0. */
232/* */
233/*********************************************************************/
wdenkbf9e3b32004-02-12 00:47:09 +0000234static void move64 (unsigned long long *src, unsigned long long *dest)
wdenkafd7f3d2002-11-03 01:41:26 +0000235{
wdenkbf9e3b32004-02-12 00:47:09 +0000236 asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */
237 "stfd 0, 0(4)" /* *dest = fpr0 */
238 : : : "fr0"); /* Clobbers fr0 */
239 return;
wdenkafd7f3d2002-11-03 01:41:26 +0000240}
241
242
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243#if defined (CONFIG_SYS_DRAM_TEST_DATA)
wdenkafd7f3d2002-11-03 01:41:26 +0000244
wdenkbf9e3b32004-02-12 00:47:09 +0000245unsigned long long pattern[] = {
wdenkeedcd072004-09-08 22:03:11 +0000246 0xaaaaaaaaaaaaaaaaULL,
247 0xccccccccccccccccULL,
248 0xf0f0f0f0f0f0f0f0ULL,
249 0xff00ff00ff00ff00ULL,
250 0xffff0000ffff0000ULL,
251 0xffffffff00000000ULL,
252 0x00000000ffffffffULL,
253 0x0000ffff0000ffffULL,
254 0x00ff00ff00ff00ffULL,
255 0x0f0f0f0f0f0f0f0fULL,
256 0x3333333333333333ULL,
257 0x5555555555555555ULL,
wdenkbf9e3b32004-02-12 00:47:09 +0000258};
wdenkafd7f3d2002-11-03 01:41:26 +0000259
260/*********************************************************************/
261/* NAME: mem_test_data() - test data lines for shorts and opens */
262/* */
263/* DESCRIPTION: */
264/* Tests data lines for shorts and opens by forcing adjacent data */
265/* to opposite states. Because the data lines could be routed in */
266/* an arbitrary manner the must ensure test patterns ensure that */
267/* every case is tested. By using the following series of binary */
268/* patterns every combination of adjacent bits is test regardless */
269/* of routing. */
270/* */
271/* ...101010101010101010101010 */
272/* ...110011001100110011001100 */
273/* ...111100001111000011110000 */
274/* ...111111110000000011111111 */
275/* */
276/* Carrying this out, gives us six hex patterns as follows: */
277/* */
278/* 0xaaaaaaaaaaaaaaaa */
279/* 0xcccccccccccccccc */
280/* 0xf0f0f0f0f0f0f0f0 */
281/* 0xff00ff00ff00ff00 */
282/* 0xffff0000ffff0000 */
283/* 0xffffffff00000000 */
284/* */
285/* The number test patterns will always be given by: */
286/* */
287/* log(base 2)(number data bits) = log2 (64) = 6 */
288/* */
289/* To test for short and opens to other signals on our boards. we */
290/* simply */
291/* test with the 1's complemnt of the paterns as well. */
292/* */
293/* OUTPUTS: */
294/* Displays failing test pattern */
295/* */
296/* RETURNS: */
297/* 0 - Passed test */
298/* 1 - Failed test */
299/* */
300/* RESTRICTIONS/LIMITATIONS: */
301/* Assumes only one one SDRAM bank */
302/* */
303/*********************************************************************/
wdenkbf9e3b32004-02-12 00:47:09 +0000304int mem_test_data (void)
wdenkafd7f3d2002-11-03 01:41:26 +0000305{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200306 unsigned long long *pmem = (unsigned long long *) CONFIG_SYS_SDRAM_BASE;
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200307 unsigned long long temp64 = 0;
wdenkbf9e3b32004-02-12 00:47:09 +0000308 int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
309 int i;
310 unsigned int hi, lo;
wdenkafd7f3d2002-11-03 01:41:26 +0000311
wdenkbf9e3b32004-02-12 00:47:09 +0000312 for (i = 0; i < num_patterns; i++) {
313 move64 (&(pattern[i]), pmem);
314 move64 (pmem, &temp64);
wdenkafd7f3d2002-11-03 01:41:26 +0000315
wdenkbf9e3b32004-02-12 00:47:09 +0000316 /* hi = (temp64>>32) & 0xffffffff; */
317 /* lo = temp64 & 0xffffffff; */
318 /* printf("\ntemp64 = 0x%08x%08x", hi, lo); */
wdenkafd7f3d2002-11-03 01:41:26 +0000319
wdenkbf9e3b32004-02-12 00:47:09 +0000320 hi = (pattern[i] >> 32) & 0xffffffff;
321 lo = pattern[i] & 0xffffffff;
322 /* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo); */
wdenkafd7f3d2002-11-03 01:41:26 +0000323
wdenkbf9e3b32004-02-12 00:47:09 +0000324 if (temp64 != pattern[i]) {
325 printf ("\n Data Test Failed, pattern 0x%08x%08x",
326 hi, lo);
327 return 1;
328 }
wdenkafd7f3d2002-11-03 01:41:26 +0000329 }
wdenkafd7f3d2002-11-03 01:41:26 +0000330
wdenkbf9e3b32004-02-12 00:47:09 +0000331 return 0;
wdenkafd7f3d2002-11-03 01:41:26 +0000332}
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200333#endif /* CONFIG_SYS_DRAM_TEST_DATA */
wdenkafd7f3d2002-11-03 01:41:26 +0000334
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200335#if defined (CONFIG_SYS_DRAM_TEST_ADDRESS)
wdenkafd7f3d2002-11-03 01:41:26 +0000336/*********************************************************************/
337/* NAME: mem_test_address() - test address lines */
338/* */
339/* DESCRIPTION: */
340/* This function performs a test to verify that each word im */
341/* memory is uniquly addressable. The test sequence is as follows: */
342/* */
343/* 1) write the address of each word to each word. */
344/* 2) verify that each location equals its address */
345/* */
346/* OUTPUTS: */
347/* Displays failing test pattern and address */
348/* */
349/* RETURNS: */
350/* 0 - Passed test */
351/* 1 - Failed test */
352/* */
353/* RESTRICTIONS/LIMITATIONS: */
354/* */
355/* */
356/*********************************************************************/
wdenkbf9e3b32004-02-12 00:47:09 +0000357int mem_test_address (void)
wdenkafd7f3d2002-11-03 01:41:26 +0000358{
wdenkbf9e3b32004-02-12 00:47:09 +0000359 volatile unsigned int *pmem =
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200360 (volatile unsigned int *) CONFIG_SYS_SDRAM_BASE;
361 const unsigned int size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024) / 4;
wdenkbf9e3b32004-02-12 00:47:09 +0000362 unsigned int i;
wdenkafd7f3d2002-11-03 01:41:26 +0000363
wdenkbf9e3b32004-02-12 00:47:09 +0000364 /* write address to each location */
365 for (i = 0; i < size; i++) {
366 pmem[i] = i;
wdenkafd7f3d2002-11-03 01:41:26 +0000367 }
wdenkbf9e3b32004-02-12 00:47:09 +0000368
369 /* verify each loaction */
370 for (i = 0; i < size; i++) {
371 if (pmem[i] != i) {
372 printf ("\n Address Test Failed at 0x%x", i);
373 return 1;
374 }
375 }
376 return 0;
wdenkafd7f3d2002-11-03 01:41:26 +0000377}
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200378#endif /* CONFIG_SYS_DRAM_TEST_ADDRESS */
wdenkafd7f3d2002-11-03 01:41:26 +0000379
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200380#if defined (CONFIG_SYS_DRAM_TEST_WALK)
wdenkafd7f3d2002-11-03 01:41:26 +0000381/*********************************************************************/
382/* NAME: mem_march() - memory march */
383/* */
384/* DESCRIPTION: */
385/* Marches up through memory. At each location verifies rmask if */
386/* read = 1. At each location write wmask if write = 1. Displays */
387/* failing address and pattern. */
388/* */
389/* INPUTS: */
390/* volatile unsigned long long * base - start address of test */
391/* unsigned int size - number of dwords(64-bit) to test */
392/* unsigned long long rmask - read verify mask */
393/* unsigned long long wmask - wrtie verify mask */
394/* short read - verifies rmask if read = 1 */
395/* short write - writes wmask if write = 1 */
396/* */
397/* OUTPUTS: */
398/* Displays failing test pattern and address */
399/* */
400/* RETURNS: */
401/* 0 - Passed test */
402/* 1 - Failed test */
403/* */
404/* RESTRICTIONS/LIMITATIONS: */
405/* */
406/* */
407/*********************************************************************/
wdenkbf9e3b32004-02-12 00:47:09 +0000408int mem_march (volatile unsigned long long *base,
409 unsigned int size,
410 unsigned long long rmask,
411 unsigned long long wmask, short read, short write)
wdenkafd7f3d2002-11-03 01:41:26 +0000412{
wdenkbf9e3b32004-02-12 00:47:09 +0000413 unsigned int i;
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200414 unsigned long long temp = 0;
wdenkbf9e3b32004-02-12 00:47:09 +0000415 unsigned int hitemp, lotemp, himask, lomask;
wdenkafd7f3d2002-11-03 01:41:26 +0000416
wdenkbf9e3b32004-02-12 00:47:09 +0000417 for (i = 0; i < size; i++) {
418 if (read != 0) {
419 /* temp = base[i]; */
420 move64 ((unsigned long long *) &(base[i]), &temp);
421 if (rmask != temp) {
422 hitemp = (temp >> 32) & 0xffffffff;
423 lotemp = temp & 0xffffffff;
424 himask = (rmask >> 32) & 0xffffffff;
425 lomask = rmask & 0xffffffff;
wdenkafd7f3d2002-11-03 01:41:26 +0000426
wdenkbf9e3b32004-02-12 00:47:09 +0000427 printf ("\n Walking one's test failed: address = 0x%08x," "\n\texpected 0x%08x%08x, found 0x%08x%08x", i << 3, himask, lomask, hitemp, lotemp);
428 return 1;
429 }
430 }
431 if (write != 0) {
432 /* base[i] = wmask; */
433 move64 (&wmask, (unsigned long long *) &(base[i]));
434 }
wdenkafd7f3d2002-11-03 01:41:26 +0000435 }
wdenkbf9e3b32004-02-12 00:47:09 +0000436 return 0;
wdenkafd7f3d2002-11-03 01:41:26 +0000437}
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200438#endif /* CONFIG_SYS_DRAM_TEST_WALK */
wdenkafd7f3d2002-11-03 01:41:26 +0000439
440/*********************************************************************/
441/* NAME: mem_test_walk() - a simple walking ones test */
442/* */
443/* DESCRIPTION: */
444/* Performs a walking ones through entire physical memory. The */
445/* test uses as series of memory marches, mem_march(), to verify */
446/* and write the test patterns to memory. The test sequence is as */
447/* follows: */
448/* 1) march writing 0000...0001 */
449/* 2) march verifying 0000...0001 , writing 0000...0010 */
450/* 3) repeat step 2 shifting masks left 1 bit each time unitl */
451/* the write mask equals 1000...0000 */
452/* 4) march verifying 1000...0000 */
453/* The test fails if any of the memory marches return a failure. */
454/* */
455/* OUTPUTS: */
456/* Displays which pass on the memory test is executing */
457/* */
458/* RETURNS: */
459/* 0 - Passed test */
460/* 1 - Failed test */
461/* */
462/* RESTRICTIONS/LIMITATIONS: */
463/* */
464/* */
465/*********************************************************************/
wdenkbf9e3b32004-02-12 00:47:09 +0000466int mem_test_walk (void)
wdenkafd7f3d2002-11-03 01:41:26 +0000467{
wdenkbf9e3b32004-02-12 00:47:09 +0000468 unsigned long long mask;
469 volatile unsigned long long *pmem =
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200470 (volatile unsigned long long *) CONFIG_SYS_SDRAM_BASE;
471 const unsigned long size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024) / 8;
wdenkafd7f3d2002-11-03 01:41:26 +0000472
wdenkbf9e3b32004-02-12 00:47:09 +0000473 unsigned int i;
wdenkafd7f3d2002-11-03 01:41:26 +0000474
wdenkbf9e3b32004-02-12 00:47:09 +0000475 mask = 0x01;
wdenkafd7f3d2002-11-03 01:41:26 +0000476
wdenkbf9e3b32004-02-12 00:47:09 +0000477 printf ("Initial Pass");
478 mem_march (pmem, size, 0x0, 0x1, 0, 1);
wdenkafd7f3d2002-11-03 01:41:26 +0000479
wdenkbf9e3b32004-02-12 00:47:09 +0000480 printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
481 printf (" ");
482 printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
483
484 for (i = 0; i < 63; i++) {
485 printf ("Pass %2d", i + 2);
486 if (mem_march (pmem, size, mask, mask << 1, 1, 1) != 0) {
487 /*printf("mask: 0x%x, pass: %d, ", mask, i); */
488 return 1;
489 }
490 mask = mask << 1;
491 printf ("\b\b\b\b\b\b\b");
wdenkafd7f3d2002-11-03 01:41:26 +0000492 }
wdenkafd7f3d2002-11-03 01:41:26 +0000493
wdenkbf9e3b32004-02-12 00:47:09 +0000494 printf ("Last Pass");
495 if (mem_march (pmem, size, 0, mask, 0, 1) != 0) {
496 /* printf("mask: 0x%x", mask); */
497 return 1;
498 }
499 printf ("\b\b\b\b\b\b\b\b\b");
500 printf (" ");
501 printf ("\b\b\b\b\b\b\b\b\b");
wdenkafd7f3d2002-11-03 01:41:26 +0000502
wdenkbf9e3b32004-02-12 00:47:09 +0000503 return 0;
wdenkafd7f3d2002-11-03 01:41:26 +0000504}
505
506/*********************************************************************/
507/* NAME: testdram() - calls any enabled memory tests */
508/* */
509/* DESCRIPTION: */
510/* Runs memory tests if the environment test variables are set to */
511/* 'y'. */
512/* */
513/* INPUTS: */
514/* testdramdata - If set to 'y', data test is run. */
515/* testdramaddress - If set to 'y', address test is run. */
516/* testdramwalk - If set to 'y', walking ones test is run */
517/* */
518/* OUTPUTS: */
519/* None */
520/* */
521/* RETURNS: */
522/* 0 - Passed test */
523/* 1 - Failed test */
524/* */
525/* RESTRICTIONS/LIMITATIONS: */
526/* */
527/* */
528/*********************************************************************/
wdenkbf9e3b32004-02-12 00:47:09 +0000529int testdram (void)
wdenkafd7f3d2002-11-03 01:41:26 +0000530{
wdenkbf9e3b32004-02-12 00:47:09 +0000531 int rundata, runaddress, runwalk;
wdenkafd7f3d2002-11-03 01:41:26 +0000532
Joe Hershbergerec8a2522012-12-11 22:16:22 -0600533 rundata = getenv_yesno("testdramdata") == 1;
534 runaddress = getenv_yesno("testdramaddress") == 1;
535 runwalk = getenv_yesno("testdramwalk") == 1;
wdenkafd7f3d2002-11-03 01:41:26 +0000536
wdenkbf9e3b32004-02-12 00:47:09 +0000537 if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
538 printf ("Testing RAM ... ");
wdenkafd7f3d2002-11-03 01:41:26 +0000539 }
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200540#ifdef CONFIG_SYS_DRAM_TEST_DATA
wdenkbf9e3b32004-02-12 00:47:09 +0000541 if (rundata == 1) {
542 if (mem_test_data () == 1) {
543 return 1;
544 }
545 }
wdenkafd7f3d2002-11-03 01:41:26 +0000546#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200547#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS
wdenkbf9e3b32004-02-12 00:47:09 +0000548 if (runaddress == 1) {
549 if (mem_test_address () == 1) {
550 return 1;
551 }
wdenkafd7f3d2002-11-03 01:41:26 +0000552 }
wdenkafd7f3d2002-11-03 01:41:26 +0000553#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200554#ifdef CONFIG_SYS_DRAM_TEST_WALK
wdenkbf9e3b32004-02-12 00:47:09 +0000555 if (runwalk == 1) {
556 if (mem_test_walk () == 1) {
557 return 1;
558 }
wdenkafd7f3d2002-11-03 01:41:26 +0000559 }
wdenkafd7f3d2002-11-03 01:41:26 +0000560#endif
wdenkbf9e3b32004-02-12 00:47:09 +0000561 if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
562 printf ("passed");
563 }
564 return 0;
wdenkafd7f3d2002-11-03 01:41:26 +0000565
566}
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200567#endif /* CONFIG_SYS_DRAM_TEST */
wdenkafd7f3d2002-11-03 01:41:26 +0000568
569/*********************************************************************/
570/* NAME: initdram() - initializes SDRAM controller */
571/* */
572/* DESCRIPTION: */
573/* Initializes the MPC8260's SDRAM controller. */
574/* */
575/* INPUTS: */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200576/* CONFIG_SYS_IMMR - MPC8260 Internal memory map */
577/* CONFIG_SYS_SDRAM_BASE - Physical start address of SDRAM */
578/* CONFIG_SYS_PSDMR - SDRAM mode register */
579/* CONFIG_SYS_MPTPR - Memory refresh timer prescaler register */
580/* CONFIG_SYS_SDRAM0_SIZE - SDRAM size */
wdenkafd7f3d2002-11-03 01:41:26 +0000581/* */
582/* RETURNS: */
583/* SDRAM size in bytes */
584/* */
585/* RESTRICTIONS/LIMITATIONS: */
586/* */
587/* */
588/*********************************************************************/
Becky Bruce9973e3c2008-06-09 16:03:40 -0500589phys_size_t initdram (int board_type)
wdenkafd7f3d2002-11-03 01:41:26 +0000590{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200591 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
wdenkbf9e3b32004-02-12 00:47:09 +0000592 volatile memctl8260_t *memctl = &immap->im_memctl;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200593 volatile uchar c = 0, *ramaddr = (uchar *) (CONFIG_SYS_SDRAM_BASE + 0x8);
594 ulong psdmr = CONFIG_SYS_PSDMR;
wdenkbf9e3b32004-02-12 00:47:09 +0000595 int i;
wdenkafd7f3d2002-11-03 01:41:26 +0000596
wdenkbf9e3b32004-02-12 00:47:09 +0000597 /*
598 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
599 *
600 * "At system reset, initialization software must set up the
601 * programmable parameters in the memory controller banks registers
602 * (ORx, BRx, P/LSDMR). After all memory parameters are configured,
603 * system software should execute the following initialization sequence
604 * for each SDRAM device.
605 *
606 * 1. Issue a PRECHARGE-ALL-BANKS command
607 * 2. Issue eight CBR REFRESH commands
608 * 3. Issue a MODE-SET command to initialize the mode register
609 *
610 * The initial commands are executed by setting P/LSDMR[OP] and
611 * accessing the SDRAM with a single-byte transaction."
612 *
613 * The appropriate BRx/ORx registers have already been set when we
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200614 * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
wdenkbf9e3b32004-02-12 00:47:09 +0000615 */
wdenkafd7f3d2002-11-03 01:41:26 +0000616
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200617 memctl->memc_psrt = CONFIG_SYS_PSRT;
618 memctl->memc_mptpr = CONFIG_SYS_MPTPR;
wdenkafd7f3d2002-11-03 01:41:26 +0000619
wdenkbf9e3b32004-02-12 00:47:09 +0000620 memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
wdenkafd7f3d2002-11-03 01:41:26 +0000621 *ramaddr = c;
wdenkafd7f3d2002-11-03 01:41:26 +0000622
wdenkbf9e3b32004-02-12 00:47:09 +0000623 memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
624 for (i = 0; i < 8; i++) {
625 *ramaddr = c;
626 }
627 memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
628 *ramaddr = c;
wdenkafd7f3d2002-11-03 01:41:26 +0000629
wdenkbf9e3b32004-02-12 00:47:09 +0000630 memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
631 *ramaddr = c;
632
633 /* return total ram size */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200634 return (CONFIG_SYS_SDRAM0_SIZE * 1024 * 1024);
wdenkafd7f3d2002-11-03 01:41:26 +0000635}
636
637/*********************************************************************/
638/* End of gw8260.c */
639/*********************************************************************/