blob: e2093d1bbc526af5a776af25966bb9eb5b87f314 [file] [log] [blame]
wdenk03f5c552004-10-10 21:21:55 +00001/*
chenhui zhao568336e2011-09-15 14:52:34 +08002 * Copyright 2004, 2011 Freescale Semiconductor.
wdenk03f5c552004-10-10 21:21:55 +00003 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02004 * SPDX-License-Identifier: GPL-2.0+
wdenk03f5c552004-10-10 21:21:55 +00005 */
6
wdenk03f5c552004-10-10 21:21:55 +00007#include <common.h>
8#include <pci.h>
9#include <asm/processor.h>
Jon Loeliger2b40edb2008-03-18 11:12:42 -050010#include <asm/mmu.h>
wdenk03f5c552004-10-10 21:21:55 +000011#include <asm/immap_85xx.h>
Jon Loeliger2b40edb2008-03-18 11:12:42 -050012#include <asm/fsl_ddr_sdram.h>
Wolfgang Denk2d5df632005-07-21 16:14:36 +020013#include <ioports.h>
Jon Loeligera30a5492008-03-04 10:03:03 -060014#include <spd_sdram.h>
Kumar Galab90d2542007-11-29 00:11:44 -060015#include <libfdt.h>
16#include <fdt_support.h>
wdenk03f5c552004-10-10 21:21:55 +000017
18#include "../common/cadmus.h"
19#include "../common/eeprom.h"
Matthew McClintockcbfc7ce2006-06-28 10:46:13 -050020#include "../common/via.h"
wdenk03f5c552004-10-10 21:21:55 +000021
Jon Loeligerd9b94f22005-07-25 14:05:07 -050022#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
wdenk03f5c552004-10-10 21:21:55 +000023extern void ddr_enable_ecc(unsigned int dram_size);
24#endif
25
wdenk03f5c552004-10-10 21:21:55 +000026void local_bus_init(void);
wdenk03f5c552004-10-10 21:21:55 +000027
Wolfgang Denk2d5df632005-07-21 16:14:36 +020028/*
29 * I/O Port configuration table
30 *
31 * if conf is 1, then that port pin will be configured at boot time
32 * according to the five values podr/pdir/ppar/psor/pdat for that entry
33 */
34
35const iop_conf_t iop_conf_tab[4][32] = {
36
37 /* Port A configuration */
38 { /* conf ppar psor pdir podr pdat */
39 /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
40 /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
41 /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
42 /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
43 /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
44 /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
45 /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
46 /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
47 /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
48 /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
49 /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
50 /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
51 /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
52 /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
53 /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
54 /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
55 /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
56 /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
57 /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
58 /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
59 /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
60 /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
61 /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
62 /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
63 /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
64 /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
65 /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
66 /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
67 /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
68 /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
69 /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
70 /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
71 },
72
73 /* Port B configuration */
74 { /* conf ppar psor pdir podr pdat */
75 /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
76 /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
77 /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
78 /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
79 /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
80 /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
81 /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
82 /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
83 /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
84 /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
85 /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
86 /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
87 /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
88 /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
89 /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
90 /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
91 /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
92 /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
93 /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
94 /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
95 /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
96 /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
97 /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
98 /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
99 /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
100 /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
101 /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
102 /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
103 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
104 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
105 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
106 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
107 },
108
109 /* Port C */
110 { /* conf ppar psor pdir podr pdat */
111 /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
112 /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
113 /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
114 /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
115 /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
116 /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
117 /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
118 /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
119 /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
120 /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
121 /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
122 /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
123 /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
124 /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
125 /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
126 /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
127 /* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */
128 /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
129 /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
130 /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
131 /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
132 /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
133 /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
134 /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
135 /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
136 /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
137 /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
138 /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
139 /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
140 /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
141 /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
142 /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
143 },
144
145 /* Port D */
146 { /* conf ppar psor pdir podr pdat */
147 /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
148 /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
149 /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
150 /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
151 /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
152 /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
153 /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
154 /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
155 /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
156 /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
157 /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
158 /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
159 /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
160 /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
161 /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
162 /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
163 /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
164 /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */
165 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
166 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
167 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
168 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
169 /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
170 /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
171 /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
172 /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
173 /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
174 /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
175 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
176 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
177 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
178 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
179 }
180};
181
wdenk5c952cf2004-10-10 21:27:30 +0000182int checkboard (void)
wdenk03f5c552004-10-10 21:21:55 +0000183{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
chenhui zhao568336e2011-09-15 14:52:34 +0800185 char buf[32];
wdenk03f5c552004-10-10 21:21:55 +0000186
wdenk5c952cf2004-10-10 21:27:30 +0000187 /* PCI slot in USER bits CSR[6:7] by convention. */
188 uint pci_slot = get_pci_slot ();
wdenk03f5c552004-10-10 21:21:55 +0000189
wdenk5c952cf2004-10-10 21:27:30 +0000190 uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
191 uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */
192 uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */
193 uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */
wdenk03f5c552004-10-10 21:21:55 +0000194
wdenk5c952cf2004-10-10 21:27:30 +0000195 uint pci1_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
wdenk03f5c552004-10-10 21:21:55 +0000196
wdenk5c952cf2004-10-10 21:27:30 +0000197 uint cpu_board_rev = get_cpu_board_revision ();
wdenk03f5c552004-10-10 21:21:55 +0000198
wdenk5c952cf2004-10-10 21:27:30 +0000199 printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
200 get_board_version (), pci_slot);
wdenk03f5c552004-10-10 21:21:55 +0000201
wdenk5c952cf2004-10-10 21:27:30 +0000202 printf ("CPU Board Revision %d.%d (0x%04x)\n",
203 MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
204 MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
wdenk03f5c552004-10-10 21:21:55 +0000205
Peter Tyser8ca78f22010-10-29 17:59:24 -0500206 printf("PCI1: %d bit, %s MHz, %s\n",
wdenk5c952cf2004-10-10 21:27:30 +0000207 (pci1_32) ? 32 : 64,
chenhui zhao568336e2011-09-15 14:52:34 +0800208 strmhz(buf, pci1_speed),
wdenk5c952cf2004-10-10 21:27:30 +0000209 pci1_clk_sel ? "sync" : "async");
wdenk03f5c552004-10-10 21:21:55 +0000210
wdenk5c952cf2004-10-10 21:27:30 +0000211 if (pci_dual) {
Peter Tyser8ca78f22010-10-29 17:59:24 -0500212 printf("PCI2: 32 bit, 66 MHz, %s\n",
wdenk5c952cf2004-10-10 21:27:30 +0000213 pci2_clk_sel ? "sync" : "async");
214 } else {
Peter Tyser8ca78f22010-10-29 17:59:24 -0500215 printf("PCI2: disabled\n");
wdenk5c952cf2004-10-10 21:27:30 +0000216 }
wdenk03f5c552004-10-10 21:21:55 +0000217
wdenk5c952cf2004-10-10 21:27:30 +0000218 /*
219 * Initialize local bus.
220 */
221 local_bus_init ();
wdenk03f5c552004-10-10 21:21:55 +0000222
wdenk5c952cf2004-10-10 21:27:30 +0000223 return 0;
wdenk03f5c552004-10-10 21:21:55 +0000224}
225
wdenk03f5c552004-10-10 21:21:55 +0000226/*
227 * Initialize Local Bus
228 */
wdenk03f5c552004-10-10 21:21:55 +0000229void
230local_bus_init(void)
231{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
Becky Brucef51cdaf2010-06-17 11:37:20 -0500233 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
wdenk03f5c552004-10-10 21:21:55 +0000234
235 uint clkdiv;
236 uint lbc_hz;
237 sys_info_t sysinfo;
238 uint temp_lbcdll;
239
240 /*
241 * Errata LBC11.
242 * Fix Local Bus clock glitch when DLL is enabled.
243 *
Wolfgang Denk8ed44d92008-10-19 02:35:50 +0200244 * If localbus freq is < 66MHz, DLL bypass mode must be used.
245 * If localbus freq is > 133MHz, DLL can be safely enabled.
wdenk03f5c552004-10-10 21:21:55 +0000246 * Between 66 and 133, the DLL is enabled with an override workaround.
247 */
248
249 get_sys_info(&sysinfo);
Trent Piephoa5d212a2008-12-03 15:16:34 -0800250 clkdiv = lbc->lcrr & LCRR_CLKDIV;
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530251 lbc_hz = sysinfo.freq_systembus / 1000000 / clkdiv;
wdenk03f5c552004-10-10 21:21:55 +0000252
253 if (lbc_hz < 66) {
Paul Gortmakera2af6a72012-08-13 13:48:57 +0000254 lbc->lcrr |= LCRR_DBYP; /* DLL Bypass */
wdenk03f5c552004-10-10 21:21:55 +0000255
256 } else if (lbc_hz >= 133) {
Paul Gortmakera2af6a72012-08-13 13:48:57 +0000257 lbc->lcrr &= (~LCRR_DBYP); /* DLL Enabled */
wdenk03f5c552004-10-10 21:21:55 +0000258
259 } else {
Paul Gortmakera2af6a72012-08-13 13:48:57 +0000260 lbc->lcrr &= (~LCRR_DBYP); /* DLL Enabled */
wdenk03f5c552004-10-10 21:21:55 +0000261 udelay(200);
262
263 /*
264 * Sample LBC DLL ctrl reg, upshift it to set the
265 * override bits.
266 */
267 temp_lbcdll = gur->lbcdllcr;
268 gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
269 asm("sync;isync;msync");
270 }
271}
272
wdenk03f5c552004-10-10 21:21:55 +0000273/*
274 * Initialize SDRAM memory on the Local Bus.
275 */
Becky Bruce70961ba2010-12-17 17:17:57 -0600276void lbc_sdram_init(void)
wdenk03f5c552004-10-10 21:21:55 +0000277{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200278#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
wdenk03f5c552004-10-10 21:21:55 +0000279
280 uint idx;
Becky Brucef51cdaf2010-06-17 11:37:20 -0500281 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200282 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
wdenk03f5c552004-10-10 21:21:55 +0000283 uint cpu_board_rev;
284 uint lsdmr_common;
285
Becky Bruce7ea38712010-12-17 17:17:59 -0600286 puts("LBC SDRAM: ");
287 print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
288 "\n ");
wdenk03f5c552004-10-10 21:21:55 +0000289
290 /*
291 * Setup SDRAM Base and Option Registers
292 */
Becky Brucef51cdaf2010-06-17 11:37:20 -0500293 set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
294 set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200295 lbc->lbcr = CONFIG_SYS_LBC_LBCR;
wdenk03f5c552004-10-10 21:21:55 +0000296 asm("msync");
297
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200298 lbc->lsrt = CONFIG_SYS_LBC_LSRT;
299 lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
wdenk03f5c552004-10-10 21:21:55 +0000300 asm("msync");
301
302 /*
303 * Determine which address lines to use baed on CPU board rev.
304 */
305 cpu_board_rev = get_cpu_board_revision();
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200306 lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
wdenk03f5c552004-10-10 21:21:55 +0000307 if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) {
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500308 lsdmr_common |= LSDMR_BSMA1617;
wdenk03f5c552004-10-10 21:21:55 +0000309 } else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) {
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500310 lsdmr_common |= LSDMR_BSMA1516;
wdenk03f5c552004-10-10 21:21:55 +0000311 } else {
312 /*
313 * Assume something unable to identify itself is
314 * really old, and likely has lines 16/17 mapped.
315 */
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500316 lsdmr_common |= LSDMR_BSMA1617;
wdenk03f5c552004-10-10 21:21:55 +0000317 }
318
319 /*
320 * Issue PRECHARGE ALL command.
321 */
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500322 lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
wdenk03f5c552004-10-10 21:21:55 +0000323 asm("sync;msync");
324 *sdram_addr = 0xff;
325 ppcDcbf((unsigned long) sdram_addr);
326 udelay(100);
327
328 /*
329 * Issue 8 AUTO REFRESH commands.
330 */
331 for (idx = 0; idx < 8; idx++) {
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500332 lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
wdenk03f5c552004-10-10 21:21:55 +0000333 asm("sync;msync");
334 *sdram_addr = 0xff;
335 ppcDcbf((unsigned long) sdram_addr);
336 udelay(100);
337 }
338
339 /*
340 * Issue 8 MODE-set command.
341 */
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500342 lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
wdenk03f5c552004-10-10 21:21:55 +0000343 asm("sync;msync");
344 *sdram_addr = 0xff;
345 ppcDcbf((unsigned long) sdram_addr);
346 udelay(100);
347
348 /*
349 * Issue NORMAL OP command.
350 */
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500351 lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
wdenk03f5c552004-10-10 21:21:55 +0000352 asm("sync;msync");
353 *sdram_addr = 0xff;
354 ppcDcbf((unsigned long) sdram_addr);
355 udelay(200); /* Overkill. Must wait > 200 bus cycles */
356
357#endif /* enable SDRAM init */
358}
359
Matthew McClintockcbfc7ce2006-06-28 10:46:13 -0500360#ifdef CONFIG_PCI
361/* For some reason the Tundra PCI bridge shows up on itself as a
362 * different device. Work around that by refusing to configure it
wdenk03f5c552004-10-10 21:21:55 +0000363 */
Matthew McClintockcbfc7ce2006-06-28 10:46:13 -0500364void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
wdenk03f5c552004-10-10 21:21:55 +0000365
wdenk03f5c552004-10-10 21:21:55 +0000366static struct pci_config_table pci_mpc85xxcds_config_table[] = {
Matthew McClintockcbfc7ce2006-06-28 10:46:13 -0500367 {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
Randy Vinson7f3f2bd2007-02-27 19:42:22 -0700368 {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
369 {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
Andy Flemingffa621a2007-02-24 01:08:13 -0600370 mpc85xx_config_via_usbide, {0,0,0}},
Randy Vinson7f3f2bd2007-02-27 19:42:22 -0700371 {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
372 mpc85xx_config_via_usb, {0,0,0}},
373 {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
374 mpc85xx_config_via_usb2, {0,0,0}},
375 {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
Andy Flemingffa621a2007-02-24 01:08:13 -0600376 mpc85xx_config_via_power, {0,0,0}},
Randy Vinson7f3f2bd2007-02-27 19:42:22 -0700377 {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
378 mpc85xx_config_via_ac97, {0,0,0}},
Andy Flemingffa621a2007-02-24 01:08:13 -0600379 {},
wdenk03f5c552004-10-10 21:21:55 +0000380};
wdenk03f5c552004-10-10 21:21:55 +0000381
Matthew McClintockcbfc7ce2006-06-28 10:46:13 -0500382
383static struct pci_controller hose[] = {
384 {
wdenk03f5c552004-10-10 21:21:55 +0000385 config_table: pci_mpc85xxcds_config_table,
Matthew McClintockcbfc7ce2006-06-28 10:46:13 -0500386 },
387#ifdef CONFIG_MPC85XX_PCI2
Andy Flemingffa621a2007-02-24 01:08:13 -0600388 {},
wdenk03f5c552004-10-10 21:21:55 +0000389#endif
390};
391
Matthew McClintockcbfc7ce2006-06-28 10:46:13 -0500392#endif
wdenk03f5c552004-10-10 21:21:55 +0000393
wdenk03f5c552004-10-10 21:21:55 +0000394void
395pci_init_board(void)
396{
397#ifdef CONFIG_PCI
Matthew McClintocke4c2a0e2006-06-28 10:46:35 -0500398 pci_mpc85xx_init(hose);
wdenk03f5c552004-10-10 21:21:55 +0000399#endif
400}
Kumar Galab90d2542007-11-29 00:11:44 -0600401
402#if defined(CONFIG_OF_BOARD_SETUP)
403void
404ft_pci_setup(void *blob, bd_t *bd)
405{
406 int node, tmp[2];
407 const char *path;
408
409 node = fdt_path_offset(blob, "/aliases");
410 tmp[0] = 0;
411 if (node >= 0) {
412#ifdef CONFIG_PCI1
413 path = fdt_getprop(blob, node, "pci0", NULL);
414 if (path) {
415 tmp[1] = hose[0].last_busno - hose[0].first_busno;
416 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
417 }
418#endif
419#ifdef CONFIG_MPC85XX_PCI2
420 path = fdt_getprop(blob, node, "pci1", NULL);
421 if (path) {
422 tmp[1] = hose[1].last_busno - hose[1].first_busno;
423 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
424 }
425#endif
426 }
427}
428#endif