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Patrick Delaunay1a4f57c2020-03-06 17:54:41 +01001// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
4 * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
5 */
6
7#include "stm32mp153.dtsi"
8
9/ {
10 soc {
11 gpu: gpu@59000000 {
12 compatible = "vivante,gc";
13 reg = <0x59000000 0x800>;
14 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
15 clocks = <&rcc GPU>, <&rcc GPU_K>;
16 clock-names = "bus" ,"core";
17 resets = <&rcc GPU_R>;
Patrick Delaunay1a4f57c2020-03-06 17:54:41 +010018 };
19
20 dsi: dsi@5a000000 {
21 compatible = "st,stm32-dsi";
22 reg = <0x5a000000 0x800>;
23 clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>;
24 clock-names = "pclk", "ref", "px_clk";
Patrice Chotardf9591182023-09-26 17:09:18 +020025 phy-dsi-supply = <&reg18>;
Patrick Delaunay1a4f57c2020-03-06 17:54:41 +010026 resets = <&rcc DSI_R>;
27 reset-names = "apb";
28 status = "disabled";
Patrick Delaunay500327e2020-07-06 13:26:53 +020029
30 ports {
31 #address-cells = <1>;
32 #size-cells = <0>;
Patrice Chotardf9591182023-09-26 17:09:18 +020033
34 port@0 {
35 reg = <0>;
36 dsi_in: endpoint {
37 };
38 };
39
40 port@1 {
41 reg = <1>;
42 dsi_out: endpoint {
43 };
44 };
Patrick Delaunay500327e2020-07-06 13:26:53 +020045 };
Patrick Delaunay1a4f57c2020-03-06 17:54:41 +010046 };
47 };
48};