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Jon Smirlc9969942009-06-14 18:21:28 -04001/*
2 * (C) Copyright 2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2004
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
7 *
8 * (C) Copyright 2006
9 * Eric Schumann, Phytec Messtechnik GmbH
10 *
11 * See file CREDITS for list of people who contributed to this
12 * project.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 */
29
30#include <common.h>
31#include <mpc5xxx.h>
32#include <pci.h>
Peter Tyser61f2b382010-04-12 22:28:07 -050033#include <asm/io.h>
Jon Smirlc9969942009-06-14 18:21:28 -040034
35#include "mt46v32m16-75.h"
36
37#ifndef CONFIG_SYS_RAMBOOT
38static void sdram_start(int hi_addr)
39{
40 volatile struct mpc5xxx_cdm *cdm =
41 (struct mpc5xxx_cdm *)MPC5XXX_CDM;
42 volatile struct mpc5xxx_sdram *sdram =
43 (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
44
45 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
46
47 /* unlock mode register */
48 out_be32 (&sdram->ctrl,
49 (SDRAM_CONTROL | 0x80000000 | hi_addr_bit));
50
51 /* precharge all banks */
52 out_be32 (&sdram->ctrl,
53 (SDRAM_CONTROL | 0x80000002 | hi_addr_bit));
54
55#ifdef SDRAM_DDR
56 /* set mode register: extended mode */
57 out_be32 (&sdram->mode, (SDRAM_EMODE));
58
59 /* set mode register: reset DLL */
60 out_be32 (&sdram->mode,
61 (SDRAM_MODE | 0x04000000));
62#endif
63
64 /* precharge all banks */
65 out_be32 (&sdram->ctrl,
66 (SDRAM_CONTROL | 0x80000002 | hi_addr_bit));
67
68 /* auto refresh */
69 out_be32 (&sdram->ctrl,
70 (SDRAM_CONTROL | 0x80000004 | hi_addr_bit));
71
72 /* set mode register */
73 out_be32 (&sdram->mode, (SDRAM_MODE));
74
75 /* normal operation */
76 out_be32 (&sdram->ctrl,
77 (SDRAM_CONTROL | hi_addr_bit));
78
79 /* set CDM clock enable register, set MPC5200B SDRAM bus */
80 /* to reduced driver strength */
81 out_be32 (&cdm->clock_enable, (0x00CFFFFF));
82}
83#endif
84
85/*
86 * ATTENTION: Although partially referenced initdram does NOT make
87 * real use of CONFIG_SYS_SDRAM_BASE. The code does not
88 * work if CONFIG_SYS_SDRAM_BASE
89 * is something else than 0x00000000.
90 */
91
92phys_size_t initdram(int board_type)
93{
94 volatile struct mpc5xxx_mmap_ctl *mm =
95 (struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
96 volatile struct mpc5xxx_cdm *cdm =
97 (struct mpc5xxx_cdm *)MPC5XXX_CDM;
98 volatile struct mpc5xxx_sdram *sdram =
99 (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
100 ulong dramsize = 0;
101 ulong dramsize2 = 0;
102#ifndef CONFIG_SYS_RAMBOOT
103 ulong test1, test2;
104
105 /* setup SDRAM chip selects */
106 /* 256MB at 0x0 */
107 out_be32 (&mm->sdram0, 0x0000001b);
108 /* disabled */
109 out_be32 (&mm->sdram1, 0x10000000);
110
111 /* setup config registers */
112 out_be32 (&sdram->config1, SDRAM_CONFIG1);
113 out_be32 (&sdram->config2, SDRAM_CONFIG2);
114
115#if defined(SDRAM_DDR) && defined(SDRAM_TAPDELAY)
116 /* set tap delay */
117 out_be32 (&cdm->porcfg, SDRAM_TAPDELAY);
118#endif
119
120 /* find RAM size using SDRAM CS0 only */
121 sdram_start(0);
122 test1 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x10000000);
123 sdram_start(1);
124 test2 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x10000000);
125 if (test1 > test2) {
126 sdram_start(0);
127 dramsize = test1;
128 } else
129 dramsize = test2;
130
131 /* memory smaller than 1MB is impossible */
132 if (dramsize < (1 << 20))
133 dramsize = 0;
134
135 /* set SDRAM CS0 size according to the amount of RAM found */
136 if (dramsize > 0) {
137 out_be32 (&mm->sdram0,
138 (0x13 + __builtin_ffs(dramsize >> 20) - 1));
139 } else {
140 /* disabled */
141 out_be32 (&mm->sdram0, 0);
142 }
143
144#else /* CONFIG_SYS_RAMBOOT */
145
146 /* retrieve size of memory connected to SDRAM CS0 */
147 dramsize = in_be32(&mm->sdram0) & 0xFF;
148 if (dramsize >= 0x13)
149 dramsize = (1 << (dramsize - 0x13)) << 20;
150 else
151 dramsize = 0;
152
153 /* retrieve size of memory connected to SDRAM CS1 */
154 dramsize2 = in_be32(&mm->sdram1) & 0xFF;
155 if (dramsize2 >= 0x13)
156 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
157 else
158 dramsize2 = 0;
159
160#endif /* CONFIG_SYS_RAMBOOT */
161
162 return dramsize + dramsize2;
163}
164
165int checkboard(void)
166{
167 puts("Board: phyCORE-MPC5200B-tiny\n");
168 return 0;
169}
170
171#ifdef CONFIG_PCI
172static struct pci_controller hose;
173
174extern void pci_mpc5xxx_init(struct pci_controller *);
175
176void pci_init_board(void)
177{
178 pci_mpc5xxx_init(&hose);
179}
180#endif
181
182#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
183void ft_board_setup(void *blob, bd_t * bd)
184{
185 ft_cpu_setup(blob, bd);
186}
187#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
188
189#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
190
191#define GPIO_PSC2_4 0x02000000UL
192
193void init_ide_reset(void)
194{
195 volatile struct mpc5xxx_wu_gpio *wu_gpio =
196 (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
197 debug("init_ide_reset\n");
198
199 /* Configure PSC2_4 as GPIO output for ATA reset */
200 setbits_be32(&wu_gpio->enable, GPIO_PSC2_4);
201 setbits_be32(&wu_gpio->ddr, GPIO_PSC2_4);
202 /* Deassert reset */
203 setbits_be32(&wu_gpio->dvo, GPIO_PSC2_4);
204}
205
206void ide_set_reset(int idereset)
207{
208 volatile struct mpc5xxx_wu_gpio *wu_gpio =
209 (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
210 debug("ide_reset(%d)\n", idereset);
211
212 if (idereset) {
213 clrbits_be32(&wu_gpio->dvo, GPIO_PSC2_4);
214 /* Make a delay. MPC5200 spec says 25 usec min */
215 udelay(500000);
216 } else
217 setbits_be32(&wu_gpio->dvo, GPIO_PSC2_4);
218}
219#endif /* defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) */