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Michal Simek78d19a32009-09-07 09:08:02 +02001/*
2 * (C) Copyright 2007-2009 Michal Simek
3 * (C) Copyright 2003 Xilinx Inc.
Michal Simek89c53892008-03-28 12:41:56 +01004 *
Michal Simek89c53892008-03-28 12:41:56 +01005 * Michal SIMEK <monstr@monstr.eu>
6 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02007 * SPDX-License-Identifier: GPL-2.0+
Michal Simek78d19a32009-09-07 09:08:02 +02008 */
Michal Simek89c53892008-03-28 12:41:56 +01009
10#include <common.h>
11#include <net.h>
12#include <config.h>
Michal Simekd538ee12015-12-10 17:15:52 +010013#include <dm.h>
Michal Simekd722e862015-12-10 13:33:20 +010014#include <console.h>
Michal Simek042272a2010-10-11 11:41:47 +100015#include <malloc.h>
Michal Simek89c53892008-03-28 12:41:56 +010016#include <asm/io.h>
Michal Simekd722e862015-12-10 13:33:20 +010017#include <phy.h>
18#include <miiphy.h>
Michal Simek7fd70822012-06-28 21:37:57 +000019#include <fdtdec.h>
Michal Simekd722e862015-12-10 13:33:20 +010020#include <asm-generic/errno.h>
Michal Simek4d2749b2015-12-10 16:31:38 +010021#include <linux/kernel.h>
Michal Simek7fd70822012-06-28 21:37:57 +000022
Michal Simekd538ee12015-12-10 17:15:52 +010023DECLARE_GLOBAL_DATA_PTR;
Michal Simek89c53892008-03-28 12:41:56 +010024
Michal Simek89c53892008-03-28 12:41:56 +010025#define ENET_ADDR_LENGTH 6
Michal Simek4d2749b2015-12-10 16:31:38 +010026#define ETH_FCS_LEN 4 /* Octets in the FCS */
Michal Simek89c53892008-03-28 12:41:56 +010027
28/* Xmit complete */
29#define XEL_TSR_XMIT_BUSY_MASK 0x00000001UL
30/* Xmit interrupt enable bit */
31#define XEL_TSR_XMIT_IE_MASK 0x00000008UL
Michal Simek89c53892008-03-28 12:41:56 +010032/* Program the MAC address */
33#define XEL_TSR_PROGRAM_MASK 0x00000002UL
34/* define for programming the MAC address into the EMAC Lite */
35#define XEL_TSR_PROG_MAC_ADDR (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK)
36
37/* Transmit packet length upper byte */
38#define XEL_TPLR_LENGTH_MASK_HI 0x0000FF00UL
39/* Transmit packet length lower byte */
40#define XEL_TPLR_LENGTH_MASK_LO 0x000000FFUL
41
42/* Recv complete */
43#define XEL_RSR_RECV_DONE_MASK 0x00000001UL
44/* Recv interrupt enable bit */
45#define XEL_RSR_RECV_IE_MASK 0x00000008UL
46
Michal Simekd722e862015-12-10 13:33:20 +010047/* MDIO Address Register Bit Masks */
48#define XEL_MDIOADDR_REGADR_MASK 0x0000001F /* Register Address */
49#define XEL_MDIOADDR_PHYADR_MASK 0x000003E0 /* PHY Address */
50#define XEL_MDIOADDR_PHYADR_SHIFT 5
51#define XEL_MDIOADDR_OP_MASK 0x00000400 /* RD/WR Operation */
52
53/* MDIO Write Data Register Bit Masks */
54#define XEL_MDIOWR_WRDATA_MASK 0x0000FFFF /* Data to be Written */
55
56/* MDIO Read Data Register Bit Masks */
57#define XEL_MDIORD_RDDATA_MASK 0x0000FFFF /* Data to be Read */
58
59/* MDIO Control Register Bit Masks */
60#define XEL_MDIOCTRL_MDIOSTS_MASK 0x00000001 /* MDIO Status Mask */
61#define XEL_MDIOCTRL_MDIOEN_MASK 0x00000008 /* MDIO Enable */
62
Michal Simek9a23c492015-12-10 14:18:15 +010063struct emaclite_regs {
64 u32 tx_ping; /* 0x0 - TX Ping buffer */
65 u32 reserved1[504];
66 u32 mdioaddr; /* 0x7e4 - MDIO Address Register */
67 u32 mdiowr; /* 0x7e8 - MDIO Write Data Register */
68 u32 mdiord;/* 0x7ec - MDIO Read Data Register */
69 u32 mdioctrl; /* 0x7f0 - MDIO Control Register */
70 u32 tx_ping_tplr; /* 0x7f4 - Tx packet length */
71 u32 global_interrupt; /* 0x7f8 - Global interrupt enable */
72 u32 tx_ping_tsr; /* 0x7fc - Tx status */
73 u32 tx_pong; /* 0x800 - TX Pong buffer */
74 u32 reserved2[508];
75 u32 tx_pong_tplr; /* 0xff4 - Tx packet length */
76 u32 reserved3; /* 0xff8 */
77 u32 tx_pong_tsr; /* 0xffc - Tx status */
78 u32 rx_ping; /* 0x1000 - Receive Buffer */
79 u32 reserved4[510];
80 u32 rx_ping_rsr; /* 0x17fc - Rx status */
81 u32 rx_pong; /* 0x1800 - Receive Buffer */
82 u32 reserved5[510];
83 u32 rx_pong_rsr; /* 0x1ffc - Rx status */
84};
85
Michal Simek773cfa82011-08-25 12:47:56 +020086struct xemaclite {
Michal Simek4d2749b2015-12-10 16:31:38 +010087 bool use_rx_pong_buffer_next; /* Next RX buffer to read from */
Michal Simek947324b2011-09-12 21:10:01 +000088 u32 txpp; /* TX ping pong buffer */
89 u32 rxpp; /* RX ping pong buffer */
Michal Simekd722e862015-12-10 13:33:20 +010090 int phyaddr;
Michal Simek9a23c492015-12-10 14:18:15 +010091 struct emaclite_regs *regs;
Michal Simekd722e862015-12-10 13:33:20 +010092 struct phy_device *phydev;
93 struct mii_dev *bus;
Michal Simek773cfa82011-08-25 12:47:56 +020094};
Michal Simek89c53892008-03-28 12:41:56 +010095
Michal Simekf412b6a2015-12-16 10:52:39 +010096static uchar etherrxbuff[PKTSIZE_ALIGN]; /* Receive buffer */
Michal Simek89c53892008-03-28 12:41:56 +010097
Michal Simek5ac83802011-09-12 21:10:05 +000098static void xemaclite_alignedread(u32 *srcptr, void *destptr, u32 bytecount)
Michal Simek89c53892008-03-28 12:41:56 +010099{
Michal Simek042272a2010-10-11 11:41:47 +1000100 u32 i;
Michal Simek89c53892008-03-28 12:41:56 +0100101 u32 alignbuffer;
102 u32 *to32ptr;
103 u32 *from32ptr;
104 u8 *to8ptr;
105 u8 *from8ptr;
106
107 from32ptr = (u32 *) srcptr;
108
109 /* Word aligned buffer, no correction needed. */
110 to32ptr = (u32 *) destptr;
111 while (bytecount > 3) {
112 *to32ptr++ = *from32ptr++;
113 bytecount -= 4;
114 }
115 to8ptr = (u8 *) to32ptr;
116
117 alignbuffer = *from32ptr++;
Michal Simek5ac83802011-09-12 21:10:05 +0000118 from8ptr = (u8 *) &alignbuffer;
Michal Simek89c53892008-03-28 12:41:56 +0100119
Michal Simek5ac83802011-09-12 21:10:05 +0000120 for (i = 0; i < bytecount; i++)
Michal Simek89c53892008-03-28 12:41:56 +0100121 *to8ptr++ = *from8ptr++;
Michal Simek89c53892008-03-28 12:41:56 +0100122}
123
Michal Simek00702512015-12-10 16:01:50 +0100124static void xemaclite_alignedwrite(void *srcptr, u32 *destptr, u32 bytecount)
Michal Simek89c53892008-03-28 12:41:56 +0100125{
Michal Simek042272a2010-10-11 11:41:47 +1000126 u32 i;
Michal Simek89c53892008-03-28 12:41:56 +0100127 u32 alignbuffer;
128 u32 *to32ptr = (u32 *) destptr;
129 u32 *from32ptr;
130 u8 *to8ptr;
131 u8 *from8ptr;
132
133 from32ptr = (u32 *) srcptr;
134 while (bytecount > 3) {
135
136 *to32ptr++ = *from32ptr++;
137 bytecount -= 4;
138 }
139
140 alignbuffer = 0;
Michal Simek5ac83802011-09-12 21:10:05 +0000141 to8ptr = (u8 *) &alignbuffer;
Michal Simek89c53892008-03-28 12:41:56 +0100142 from8ptr = (u8 *) from32ptr;
143
Michal Simek5ac83802011-09-12 21:10:05 +0000144 for (i = 0; i < bytecount; i++)
Michal Simek89c53892008-03-28 12:41:56 +0100145 *to8ptr++ = *from8ptr++;
Michal Simek89c53892008-03-28 12:41:56 +0100146
147 *to32ptr++ = alignbuffer;
148}
149
Michal Simekd722e862015-12-10 13:33:20 +0100150static int wait_for_bit(const char *func, u32 *reg, const u32 mask,
151 bool set, unsigned int timeout)
152{
153 u32 val;
154 unsigned long start = get_timer(0);
155
156 while (1) {
157 val = readl(reg);
158
159 if (!set)
160 val = ~val;
161
162 if ((val & mask) == mask)
163 return 0;
164
165 if (get_timer(start) > timeout)
166 break;
167
168 if (ctrlc()) {
169 puts("Abort\n");
170 return -EINTR;
171 }
172
173 udelay(1);
174 }
175
176 debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
177 func, reg, mask, set);
178
179 return -ETIMEDOUT;
180}
181
Michal Simek9a23c492015-12-10 14:18:15 +0100182static int mdio_wait(struct emaclite_regs *regs)
Michal Simekd722e862015-12-10 13:33:20 +0100183{
Michal Simek9a23c492015-12-10 14:18:15 +0100184 return wait_for_bit(__func__, &regs->mdioctrl,
Michal Simekd722e862015-12-10 13:33:20 +0100185 XEL_MDIOCTRL_MDIOSTS_MASK, false, 2000);
186}
187
Michal Simek9a23c492015-12-10 14:18:15 +0100188static u32 phyread(struct xemaclite *emaclite, u32 phyaddress, u32 registernum,
Michal Simekd722e862015-12-10 13:33:20 +0100189 u16 *data)
190{
Michal Simek9a23c492015-12-10 14:18:15 +0100191 struct emaclite_regs *regs = emaclite->regs;
192
193 if (mdio_wait(regs))
Michal Simekd722e862015-12-10 13:33:20 +0100194 return 1;
195
Michal Simek9a23c492015-12-10 14:18:15 +0100196 u32 ctrl_reg = in_be32(&regs->mdioctrl);
197 out_be32(&regs->mdioaddr, XEL_MDIOADDR_OP_MASK |
Michal Simekd722e862015-12-10 13:33:20 +0100198 ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT) | registernum));
Michal Simek9a23c492015-12-10 14:18:15 +0100199 out_be32(&regs->mdioctrl, ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK);
Michal Simekd722e862015-12-10 13:33:20 +0100200
Michal Simek9a23c492015-12-10 14:18:15 +0100201 if (mdio_wait(regs))
Michal Simekd722e862015-12-10 13:33:20 +0100202 return 1;
203
204 /* Read data */
Michal Simek9a23c492015-12-10 14:18:15 +0100205 *data = in_be32(&regs->mdiord);
Michal Simekd722e862015-12-10 13:33:20 +0100206 return 0;
207}
208
Michal Simek9a23c492015-12-10 14:18:15 +0100209static u32 phywrite(struct xemaclite *emaclite, u32 phyaddress, u32 registernum,
Michal Simekd722e862015-12-10 13:33:20 +0100210 u16 data)
211{
Michal Simek9a23c492015-12-10 14:18:15 +0100212 struct emaclite_regs *regs = emaclite->regs;
213
214 if (mdio_wait(regs))
Michal Simekd722e862015-12-10 13:33:20 +0100215 return 1;
216
217 /*
218 * Write the PHY address, register number and clear the OP bit in the
219 * MDIO Address register and then write the value into the MDIO Write
220 * Data register. Finally, set the Status bit in the MDIO Control
221 * register to start a MDIO write transaction.
222 */
Michal Simek9a23c492015-12-10 14:18:15 +0100223 u32 ctrl_reg = in_be32(&regs->mdioctrl);
224 out_be32(&regs->mdioaddr, ~XEL_MDIOADDR_OP_MASK &
Michal Simekd722e862015-12-10 13:33:20 +0100225 ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT) | registernum));
Michal Simek9a23c492015-12-10 14:18:15 +0100226 out_be32(&regs->mdiowr, data);
227 out_be32(&regs->mdioctrl, ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK);
Michal Simekd722e862015-12-10 13:33:20 +0100228
Michal Simek9a23c492015-12-10 14:18:15 +0100229 if (mdio_wait(regs))
Michal Simekd722e862015-12-10 13:33:20 +0100230 return 1;
231
232 return 0;
233}
Michal Simekd722e862015-12-10 13:33:20 +0100234
Michal Simekf03ec012015-12-16 10:40:05 +0100235static void emaclite_stop(struct udevice *dev)
Michal Simek89c53892008-03-28 12:41:56 +0100236{
Michal Simekf03ec012015-12-16 10:40:05 +0100237 debug("eth_stop\n");
Michal Simek89c53892008-03-28 12:41:56 +0100238}
239
Michal Simekd722e862015-12-10 13:33:20 +0100240/* Use MII register 1 (MII status register) to detect PHY */
241#define PHY_DETECT_REG 1
242
243/* Mask used to verify certain PHY features (or register contents)
244 * in the register above:
245 * 0x1000: 10Mbps full duplex support
246 * 0x0800: 10Mbps half duplex support
247 * 0x0008: Auto-negotiation support
248 */
249#define PHY_DETECT_MASK 0x1808
250
Michal Simekd538ee12015-12-10 17:15:52 +0100251static int setup_phy(struct udevice *dev)
Michal Simekd722e862015-12-10 13:33:20 +0100252{
Michal Simek55259e72016-05-18 12:37:22 +0200253 int i, ret;
Michal Simekd722e862015-12-10 13:33:20 +0100254 u16 phyreg;
Michal Simekd538ee12015-12-10 17:15:52 +0100255 struct xemaclite *emaclite = dev_get_priv(dev);
Michal Simekd722e862015-12-10 13:33:20 +0100256 struct phy_device *phydev;
257
258 u32 supported = SUPPORTED_10baseT_Half |
259 SUPPORTED_10baseT_Full |
260 SUPPORTED_100baseT_Half |
261 SUPPORTED_100baseT_Full;
262
263 if (emaclite->phyaddr != -1) {
Michal Simek9a23c492015-12-10 14:18:15 +0100264 phyread(emaclite, emaclite->phyaddr, PHY_DETECT_REG, &phyreg);
Michal Simekd722e862015-12-10 13:33:20 +0100265 if ((phyreg != 0xFFFF) &&
266 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
267 /* Found a valid PHY address */
268 debug("Default phy address %d is valid\n",
269 emaclite->phyaddr);
270 } else {
271 debug("PHY address is not setup correctly %d\n",
272 emaclite->phyaddr);
273 emaclite->phyaddr = -1;
274 }
275 }
276
277 if (emaclite->phyaddr == -1) {
278 /* detect the PHY address */
279 for (i = 31; i >= 0; i--) {
Michal Simek9a23c492015-12-10 14:18:15 +0100280 phyread(emaclite, i, PHY_DETECT_REG, &phyreg);
Michal Simekd722e862015-12-10 13:33:20 +0100281 if ((phyreg != 0xFFFF) &&
282 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
283 /* Found a valid PHY address */
284 emaclite->phyaddr = i;
285 debug("emaclite: Found valid phy address, %d\n",
286 i);
287 break;
288 }
289 }
290 }
291
292 /* interface - look at tsec */
293 phydev = phy_connect(emaclite->bus, emaclite->phyaddr, dev,
294 PHY_INTERFACE_MODE_MII);
295 /*
296 * Phy can support 1000baseT but device NOT that's why phydev->supported
297 * must be setup for 1000baseT. phydev->advertising setups what speeds
298 * will be used for autonegotiation where 1000baseT must be disabled.
299 */
300 phydev->supported = supported | SUPPORTED_1000baseT_Half |
301 SUPPORTED_1000baseT_Full;
302 phydev->advertising = supported;
303 emaclite->phydev = phydev;
304 phy_config(phydev);
Michal Simek55259e72016-05-18 12:37:22 +0200305 ret = phy_startup(phydev);
306 if (ret)
307 return ret;
Michal Simekd722e862015-12-10 13:33:20 +0100308
309 if (!phydev->link) {
310 printf("%s: No link.\n", phydev->dev->name);
311 return 0;
312 }
313
314 /* Do not setup anything */
315 return 1;
316}
Michal Simekd722e862015-12-10 13:33:20 +0100317
Michal Simekf03ec012015-12-16 10:40:05 +0100318static int emaclite_start(struct udevice *dev)
Michal Simek89c53892008-03-28 12:41:56 +0100319{
Michal Simekd538ee12015-12-10 17:15:52 +0100320 struct xemaclite *emaclite = dev_get_priv(dev);
321 struct eth_pdata *pdata = dev_get_platdata(dev);
Michal Simek9a23c492015-12-10 14:18:15 +0100322 struct emaclite_regs *regs = emaclite->regs;
323
Michal Simek5ac83802011-09-12 21:10:05 +0000324 debug("EmacLite Initialization Started\n");
Michal Simek89c53892008-03-28 12:41:56 +0100325
326/*
327 * TX - TX_PING & TX_PONG initialization
328 */
329 /* Restart PING TX */
Michal Simeka0b2bfb2015-12-10 15:22:21 +0100330 out_be32(&regs->tx_ping_tsr, 0);
Michal Simek89c53892008-03-28 12:41:56 +0100331 /* Copy MAC address */
Michal Simekd538ee12015-12-10 17:15:52 +0100332 xemaclite_alignedwrite(pdata->enetaddr, &regs->tx_ping,
Michal Simeka0b2bfb2015-12-10 15:22:21 +0100333 ENET_ADDR_LENGTH);
Michal Simek89c53892008-03-28 12:41:56 +0100334 /* Set the length */
Michal Simeka0b2bfb2015-12-10 15:22:21 +0100335 out_be32(&regs->tx_ping_tplr, ENET_ADDR_LENGTH);
Michal Simek89c53892008-03-28 12:41:56 +0100336 /* Update the MAC address in the EMAC Lite */
Michal Simeka0b2bfb2015-12-10 15:22:21 +0100337 out_be32(&regs->tx_ping_tsr, XEL_TSR_PROG_MAC_ADDR);
Michal Simek89c53892008-03-28 12:41:56 +0100338 /* Wait for EMAC Lite to finish with the MAC address update */
Michal Simeka0b2bfb2015-12-10 15:22:21 +0100339 while ((in_be32 (&regs->tx_ping_tsr) &
Michal Simek8d95ddb2011-08-25 12:36:39 +0200340 XEL_TSR_PROG_MAC_ADDR) != 0)
341 ;
Michal Simek89c53892008-03-28 12:41:56 +0100342
Michal Simek947324b2011-09-12 21:10:01 +0000343 if (emaclite->txpp) {
344 /* The same operation with PONG TX */
Michal Simeka0b2bfb2015-12-10 15:22:21 +0100345 out_be32(&regs->tx_pong_tsr, 0);
Michal Simekd538ee12015-12-10 17:15:52 +0100346 xemaclite_alignedwrite(pdata->enetaddr, &regs->tx_pong,
Michal Simeka0b2bfb2015-12-10 15:22:21 +0100347 ENET_ADDR_LENGTH);
348 out_be32(&regs->tx_pong_tplr, ENET_ADDR_LENGTH);
349 out_be32(&regs->tx_pong_tsr, XEL_TSR_PROG_MAC_ADDR);
350 while ((in_be32(&regs->tx_pong_tsr) &
351 XEL_TSR_PROG_MAC_ADDR) != 0)
Michal Simek947324b2011-09-12 21:10:01 +0000352 ;
353 }
Michal Simek89c53892008-03-28 12:41:56 +0100354
355/*
356 * RX - RX_PING & RX_PONG initialization
357 */
358 /* Write out the value to flush the RX buffer */
Michal Simek3af70902015-12-10 15:24:23 +0100359 out_be32(&regs->rx_ping_rsr, XEL_RSR_RECV_IE_MASK);
Michal Simek947324b2011-09-12 21:10:01 +0000360
361 if (emaclite->rxpp)
Michal Simek3af70902015-12-10 15:24:23 +0100362 out_be32(&regs->rx_pong_rsr, XEL_RSR_RECV_IE_MASK);
Michal Simek89c53892008-03-28 12:41:56 +0100363
Michal Simek9a23c492015-12-10 14:18:15 +0100364 out_be32(&regs->mdioctrl, XEL_MDIOCTRL_MDIOEN_MASK);
365 if (in_be32(&regs->mdioctrl) & XEL_MDIOCTRL_MDIOEN_MASK)
Michal Simekd722e862015-12-10 13:33:20 +0100366 if (!setup_phy(dev))
367 return -1;
Michal Simekd538ee12015-12-10 17:15:52 +0100368
Michal Simek5ac83802011-09-12 21:10:05 +0000369 debug("EmacLite Initialization complete\n");
Michal Simek89c53892008-03-28 12:41:56 +0100370 return 0;
371}
372
Michal Simek26c79452015-12-10 15:42:01 +0100373static int xemaclite_txbufferavailable(struct xemaclite *emaclite)
Michal Simek89c53892008-03-28 12:41:56 +0100374{
Michal Simek26c79452015-12-10 15:42:01 +0100375 u32 tmp;
376 struct emaclite_regs *regs = emaclite->regs;
Michal Simek773cfa82011-08-25 12:47:56 +0200377
Michal Simek89c53892008-03-28 12:41:56 +0100378 /*
379 * Read the other buffer register
380 * and determine if the other buffer is available
381 */
Michal Simek26c79452015-12-10 15:42:01 +0100382 tmp = ~in_be32(&regs->tx_ping_tsr);
383 if (emaclite->txpp)
384 tmp |= ~in_be32(&regs->tx_pong_tsr);
Michal Simek89c53892008-03-28 12:41:56 +0100385
Michal Simek26c79452015-12-10 15:42:01 +0100386 return !(tmp & XEL_TSR_XMIT_BUSY_MASK);
Michal Simek89c53892008-03-28 12:41:56 +0100387}
388
Michal Simekd538ee12015-12-10 17:15:52 +0100389static int emaclite_send(struct udevice *dev, void *ptr, int len)
Michal Simek042272a2010-10-11 11:41:47 +1000390{
391 u32 reg;
Michal Simekd538ee12015-12-10 17:15:52 +0100392 struct xemaclite *emaclite = dev_get_priv(dev);
Michal Simek5a4baa32015-12-10 15:32:11 +0100393 struct emaclite_regs *regs = emaclite->regs;
Michal Simek89c53892008-03-28 12:41:56 +0100394
Michal Simek042272a2010-10-11 11:41:47 +1000395 u32 maxtry = 1000;
Michal Simek89c53892008-03-28 12:41:56 +0100396
Michal Simek80439252011-09-12 21:10:04 +0000397 if (len > PKTSIZE)
398 len = PKTSIZE;
Michal Simek89c53892008-03-28 12:41:56 +0100399
Michal Simek26c79452015-12-10 15:42:01 +0100400 while (xemaclite_txbufferavailable(emaclite) && maxtry) {
Michal Simek5ac83802011-09-12 21:10:05 +0000401 udelay(10);
Michal Simek89c53892008-03-28 12:41:56 +0100402 maxtry--;
403 }
404
405 if (!maxtry) {
Michal Simek5ac83802011-09-12 21:10:05 +0000406 printf("Error: Timeout waiting for ethernet TX buffer\n");
Michal Simek89c53892008-03-28 12:41:56 +0100407 /* Restart PING TX */
Michal Simek5a4baa32015-12-10 15:32:11 +0100408 out_be32(&regs->tx_ping_tsr, 0);
Michal Simek947324b2011-09-12 21:10:01 +0000409 if (emaclite->txpp) {
Michal Simek5a4baa32015-12-10 15:32:11 +0100410 out_be32(&regs->tx_pong_tsr, 0);
Michal Simek947324b2011-09-12 21:10:01 +0000411 }
Michal Simek95efa792011-03-08 04:25:53 +0000412 return -1;
Michal Simek89c53892008-03-28 12:41:56 +0100413 }
414
Michal Simek89c53892008-03-28 12:41:56 +0100415 /* Determine if the expected buffer address is empty */
Michal Simek00702512015-12-10 16:01:50 +0100416 reg = in_be32(&regs->tx_ping_tsr);
Michal Simek15c239c2015-12-10 16:06:07 +0100417 if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) {
Michal Simek00702512015-12-10 16:01:50 +0100418 debug("Send packet from tx_ping buffer\n");
Michal Simek89c53892008-03-28 12:41:56 +0100419 /* Write the frame to the buffer */
Michal Simek00702512015-12-10 16:01:50 +0100420 xemaclite_alignedwrite(ptr, &regs->tx_ping, len);
421 out_be32(&regs->tx_ping_tplr, len &
422 (XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO));
423 reg = in_be32(&regs->tx_ping_tsr);
Michal Simek89c53892008-03-28 12:41:56 +0100424 reg |= XEL_TSR_XMIT_BUSY_MASK;
Michal Simek00702512015-12-10 16:01:50 +0100425 out_be32(&regs->tx_ping_tsr, reg);
Michal Simek95efa792011-03-08 04:25:53 +0000426 return 0;
Michal Simek89c53892008-03-28 12:41:56 +0100427 }
Michal Simek947324b2011-09-12 21:10:01 +0000428
429 if (emaclite->txpp) {
Michal Simek947324b2011-09-12 21:10:01 +0000430 /* Determine if the expected buffer address is empty */
Michal Simek00702512015-12-10 16:01:50 +0100431 reg = in_be32(&regs->tx_pong_tsr);
Michal Simek15c239c2015-12-10 16:06:07 +0100432 if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) {
Michal Simek00702512015-12-10 16:01:50 +0100433 debug("Send packet from tx_pong buffer\n");
Michal Simek947324b2011-09-12 21:10:01 +0000434 /* Write the frame to the buffer */
Michal Simek00702512015-12-10 16:01:50 +0100435 xemaclite_alignedwrite(ptr, &regs->tx_pong, len);
436 out_be32(&regs->tx_pong_tplr, len &
437 (XEL_TPLR_LENGTH_MASK_HI |
438 XEL_TPLR_LENGTH_MASK_LO));
439 reg = in_be32(&regs->tx_pong_tsr);
Michal Simek947324b2011-09-12 21:10:01 +0000440 reg |= XEL_TSR_XMIT_BUSY_MASK;
Michal Simek00702512015-12-10 16:01:50 +0100441 out_be32(&regs->tx_pong_tsr, reg);
Michal Simek947324b2011-09-12 21:10:01 +0000442 return 0;
Michal Simek89c53892008-03-28 12:41:56 +0100443 }
Michal Simek89c53892008-03-28 12:41:56 +0100444 }
Michal Simek947324b2011-09-12 21:10:01 +0000445
Michal Simek5ac83802011-09-12 21:10:05 +0000446 puts("Error while sending frame\n");
Michal Simek95efa792011-03-08 04:25:53 +0000447 return -1;
Michal Simek89c53892008-03-28 12:41:56 +0100448}
449
Michal Simekd538ee12015-12-10 17:15:52 +0100450static int emaclite_recv(struct udevice *dev, int flags, uchar **packetp)
Michal Simek89c53892008-03-28 12:41:56 +0100451{
Michal Simek4d2749b2015-12-10 16:31:38 +0100452 u32 length, first_read, reg, attempt = 0;
453 void *addr, *ack;
Michal Simek773cfa82011-08-25 12:47:56 +0200454 struct xemaclite *emaclite = dev->priv;
Michal Simek4d2749b2015-12-10 16:31:38 +0100455 struct emaclite_regs *regs = emaclite->regs;
456 struct ethernet_hdr *eth;
457 struct ip_udp_hdr *ip;
Michal Simek89c53892008-03-28 12:41:56 +0100458
Michal Simek4d2749b2015-12-10 16:31:38 +0100459try_again:
460 if (!emaclite->use_rx_pong_buffer_next) {
461 reg = in_be32(&regs->rx_ping_rsr);
462 debug("Testing data at rx_ping\n");
463 if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
464 debug("Data found in rx_ping buffer\n");
465 addr = &regs->rx_ping;
466 ack = &regs->rx_ping_rsr;
Michal Simek947324b2011-09-12 21:10:01 +0000467 } else {
Michal Simek4d2749b2015-12-10 16:31:38 +0100468 debug("Data not found in rx_ping buffer\n");
469 /* Pong buffer is not available - return immediately */
470 if (!emaclite->rxpp)
471 return -1;
472
473 /* Try pong buffer if this is first attempt */
474 if (attempt++)
475 return -1;
476 emaclite->use_rx_pong_buffer_next =
477 !emaclite->use_rx_pong_buffer_next;
478 goto try_again;
479 }
480 } else {
481 reg = in_be32(&regs->rx_pong_rsr);
482 debug("Testing data at rx_pong\n");
483 if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
484 debug("Data found in rx_pong buffer\n");
485 addr = &regs->rx_pong;
486 ack = &regs->rx_pong_rsr;
487 } else {
488 debug("Data not found in rx_pong buffer\n");
489 /* Try ping buffer if this is first attempt */
490 if (attempt++)
491 return -1;
492 emaclite->use_rx_pong_buffer_next =
493 !emaclite->use_rx_pong_buffer_next;
494 goto try_again;
Michal Simek89c53892008-03-28 12:41:56 +0100495 }
Michal Simek89c53892008-03-28 12:41:56 +0100496 }
Michal Simek4d2749b2015-12-10 16:31:38 +0100497
498 /* Read all bytes for ARP packet with 32bit alignment - 48bytes */
499 first_read = ALIGN(ETHER_HDR_SIZE + ARP_HDR_SIZE + ETH_FCS_LEN, 4);
500 xemaclite_alignedread(addr, etherrxbuff, first_read);
501
502 /* Detect real packet size */
503 eth = (struct ethernet_hdr *)etherrxbuff;
504 switch (ntohs(eth->et_protlen)) {
505 case PROT_ARP:
506 length = first_read;
507 debug("ARP Packet %x\n", length);
508 break;
509 case PROT_IP:
510 ip = (struct ip_udp_hdr *)(etherrxbuff + ETHER_HDR_SIZE);
511 length = ntohs(ip->ip_len);
512 length += ETHER_HDR_SIZE + ETH_FCS_LEN;
513 debug("IP Packet %x\n", length);
514 break;
515 default:
516 debug("Other Packet\n");
517 length = PKTSIZE;
518 break;
Michal Simek89c53892008-03-28 12:41:56 +0100519 }
520
Michal Simek4d2749b2015-12-10 16:31:38 +0100521 /* Read the rest of the packet which is longer then first read */
522 if (length != first_read)
523 xemaclite_alignedread(addr + first_read,
524 etherrxbuff + first_read,
525 length - first_read);
Michal Simek89c53892008-03-28 12:41:56 +0100526
527 /* Acknowledge the frame */
Michal Simek4d2749b2015-12-10 16:31:38 +0100528 reg = in_be32(ack);
Michal Simek89c53892008-03-28 12:41:56 +0100529 reg &= ~XEL_RSR_RECV_DONE_MASK;
Michal Simek4d2749b2015-12-10 16:31:38 +0100530 out_be32(ack, reg);
Michal Simek89c53892008-03-28 12:41:56 +0100531
Michal Simek4d2749b2015-12-10 16:31:38 +0100532 debug("Packet receive from 0x%p, length %dB\n", addr, length);
Michal Simekf412b6a2015-12-16 10:52:39 +0100533 *packetp = etherrxbuff;
534 return length;
Michal Simek89c53892008-03-28 12:41:56 +0100535}
Michal Simek042272a2010-10-11 11:41:47 +1000536
Michal Simekd538ee12015-12-10 17:15:52 +0100537static int emaclite_miiphy_read(struct mii_dev *bus, int addr,
538 int devad, int reg)
Michal Simekd722e862015-12-10 13:33:20 +0100539{
540 u32 ret;
Michal Simekd538ee12015-12-10 17:15:52 +0100541 u16 val = 0;
Michal Simekd722e862015-12-10 13:33:20 +0100542
Michal Simekd538ee12015-12-10 17:15:52 +0100543 ret = phyread(bus->priv, addr, reg, &val);
544 debug("emaclite: Read MII 0x%x, 0x%x, 0x%x, %d\n", addr, reg, val, ret);
545 return val;
Michal Simekd722e862015-12-10 13:33:20 +0100546}
547
Michal Simekd538ee12015-12-10 17:15:52 +0100548static int emaclite_miiphy_write(struct mii_dev *bus, int addr, int devad,
549 int reg, u16 value)
Michal Simekd722e862015-12-10 13:33:20 +0100550{
Michal Simekd538ee12015-12-10 17:15:52 +0100551 debug("emaclite: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, value);
552 return phywrite(bus->priv, addr, reg, value);
Michal Simekd722e862015-12-10 13:33:20 +0100553}
Michal Simekd722e862015-12-10 13:33:20 +0100554
Michal Simekd538ee12015-12-10 17:15:52 +0100555static int emaclite_probe(struct udevice *dev)
Michal Simek042272a2010-10-11 11:41:47 +1000556{
Michal Simekd538ee12015-12-10 17:15:52 +0100557 struct xemaclite *emaclite = dev_get_priv(dev);
558 int ret;
Michal Simek042272a2010-10-11 11:41:47 +1000559
Michal Simekd538ee12015-12-10 17:15:52 +0100560 emaclite->bus = mdio_alloc();
561 emaclite->bus->read = emaclite_miiphy_read;
562 emaclite->bus->write = emaclite_miiphy_write;
563 emaclite->bus->priv = emaclite;
564 strcpy(emaclite->bus->name, "emaclite");
Michal Simek042272a2010-10-11 11:41:47 +1000565
Michal Simekd538ee12015-12-10 17:15:52 +0100566 ret = mdio_register(emaclite->bus);
567 if (ret)
568 return ret;
Michal Simek773cfa82011-08-25 12:47:56 +0200569
Michal Simekd538ee12015-12-10 17:15:52 +0100570 return 0;
571}
Michal Simek773cfa82011-08-25 12:47:56 +0200572
Michal Simekd538ee12015-12-10 17:15:52 +0100573static int emaclite_remove(struct udevice *dev)
574{
575 struct xemaclite *emaclite = dev_get_priv(dev);
Michal Simek947324b2011-09-12 21:10:01 +0000576
Michal Simekd538ee12015-12-10 17:15:52 +0100577 free(emaclite->phydev);
578 mdio_unregister(emaclite->bus);
579 mdio_free(emaclite->bus);
Michal Simek042272a2010-10-11 11:41:47 +1000580
Michal Simekd538ee12015-12-10 17:15:52 +0100581 return 0;
582}
Michal Simek042272a2010-10-11 11:41:47 +1000583
Michal Simekd538ee12015-12-10 17:15:52 +0100584static const struct eth_ops emaclite_ops = {
Michal Simekf03ec012015-12-16 10:40:05 +0100585 .start = emaclite_start,
Michal Simekd538ee12015-12-10 17:15:52 +0100586 .send = emaclite_send,
587 .recv = emaclite_recv,
Michal Simekf03ec012015-12-16 10:40:05 +0100588 .stop = emaclite_stop,
Michal Simekd538ee12015-12-10 17:15:52 +0100589};
590
591static int emaclite_ofdata_to_platdata(struct udevice *dev)
592{
593 struct eth_pdata *pdata = dev_get_platdata(dev);
594 struct xemaclite *emaclite = dev_get_priv(dev);
595 int offset = 0;
596
597 pdata->iobase = (phys_addr_t)dev_get_addr(dev);
598 emaclite->regs = (struct emaclite_regs *)pdata->iobase;
599
Michal Simekd722e862015-12-10 13:33:20 +0100600 emaclite->phyaddr = -1;
Michal Simekd722e862015-12-10 13:33:20 +0100601
Michal Simekd538ee12015-12-10 17:15:52 +0100602 offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset,
603 "phy-handle");
604 if (offset > 0)
605 emaclite->phyaddr = fdtdec_get_int(gd->fdt_blob, offset,
606 "reg", -1);
Michal Simek042272a2010-10-11 11:41:47 +1000607
Michal Simekd538ee12015-12-10 17:15:52 +0100608 emaclite->txpp = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
609 "xlnx,tx-ping-pong", 0);
610 emaclite->rxpp = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
611 "xlnx,rx-ping-pong", 0);
Michal Simekd722e862015-12-10 13:33:20 +0100612
Michal Simekd538ee12015-12-10 17:15:52 +0100613 printf("EMACLITE: %lx, phyaddr %d, %d/%d\n", (ulong)emaclite->regs,
614 emaclite->phyaddr, emaclite->txpp, emaclite->rxpp);
Michal Simekd722e862015-12-10 13:33:20 +0100615
Michal Simekd538ee12015-12-10 17:15:52 +0100616 return 0;
Michal Simek042272a2010-10-11 11:41:47 +1000617}
Michal Simekd538ee12015-12-10 17:15:52 +0100618
619static const struct udevice_id emaclite_ids[] = {
620 { .compatible = "xlnx,xps-ethernetlite-1.00.a" },
621 { }
622};
623
624U_BOOT_DRIVER(emaclite) = {
625 .name = "emaclite",
626 .id = UCLASS_ETH,
627 .of_match = emaclite_ids,
628 .ofdata_to_platdata = emaclite_ofdata_to_platdata,
629 .probe = emaclite_probe,
630 .remove = emaclite_remove,
631 .ops = &emaclite_ops,
632 .priv_auto_alloc_size = sizeof(struct xemaclite),
633 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
634};