blob: 9db9367e952c9b9cf43f7923b45077e0858bf923 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenk1df49e22002-09-17 21:37:55 +00002/*
3 * (C) Copyright 2002
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
wdenk1df49e22002-09-17 21:37:55 +00005 */
6
7#include <common.h>
Marek Vasut047a8002020-05-23 15:07:30 +02008#include <asm/io.h>
Marek Vasut5116aae2020-05-23 14:55:26 +02009#include <cpu_func.h>
wdenk1df49e22002-09-17 21:37:55 +000010#include <malloc.h>
Marek Vasut047a8002020-05-23 15:07:30 +020011#include <miiphy.h>
wdenk1df49e22002-09-17 21:37:55 +000012#include <net.h>
Ben Warren10efa022008-08-31 20:37:00 -070013#include <netdev.h>
wdenk1df49e22002-09-17 21:37:55 +000014#include <pci.h>
Simon Glassc05ed002020-05-10 11:40:11 -060015#include <linux/delay.h>
wdenk1df49e22002-09-17 21:37:55 +000016
Marek Vasutaba283d2020-05-23 12:49:16 +020017/* Ethernet chip registers. */
Marek Vasutf3878f52020-05-23 13:52:50 +020018#define SCB_STATUS 0 /* Rx/Command Unit Status *Word* */
19#define SCB_INT_ACK_BYTE 1 /* Rx/Command Unit STAT/ACK byte */
20#define SCB_CMD 2 /* Rx/Command Unit Command *Word* */
21#define SCB_INTR_CTL_BYTE 3 /* Rx/Command Unit Intr.Control Byte */
22#define SCB_POINTER 4 /* General purpose pointer. */
23#define SCB_PORT 8 /* Misc. commands and operands. */
24#define SCB_FLASH 12 /* Flash memory control. */
25#define SCB_EEPROM 14 /* EEPROM memory control. */
26#define SCB_CTRL_MDI 16 /* MDI interface control. */
27#define SCB_EARLY_RX 20 /* Early receive byte count. */
28#define SCB_GEN_CONTROL 28 /* 82559 General Control Register */
29#define SCB_GEN_STATUS 29 /* 82559 General Status register */
wdenk1df49e22002-09-17 21:37:55 +000030
Marek Vasutaba283d2020-05-23 12:49:16 +020031/* 82559 SCB status word defnitions */
Wolfgang Denkc570b2f2005-09-26 01:06:33 +020032#define SCB_STATUS_CX 0x8000 /* CU finished command (transmit) */
33#define SCB_STATUS_FR 0x4000 /* frame received */
34#define SCB_STATUS_CNA 0x2000 /* CU left active state */
35#define SCB_STATUS_RNR 0x1000 /* receiver left ready state */
36#define SCB_STATUS_MDI 0x0800 /* MDI read/write cycle done */
37#define SCB_STATUS_SWI 0x0400 /* software generated interrupt */
38#define SCB_STATUS_FCP 0x0100 /* flow control pause interrupt */
wdenk1df49e22002-09-17 21:37:55 +000039
Wolfgang Denkc570b2f2005-09-26 01:06:33 +020040#define SCB_INTACK_MASK 0xFD00 /* all the above */
wdenk1df49e22002-09-17 21:37:55 +000041
Wolfgang Denkc570b2f2005-09-26 01:06:33 +020042#define SCB_INTACK_TX (SCB_STATUS_CX | SCB_STATUS_CNA)
43#define SCB_INTACK_RX (SCB_STATUS_FR | SCB_STATUS_RNR)
wdenk1df49e22002-09-17 21:37:55 +000044
Marek Vasutaba283d2020-05-23 12:49:16 +020045/* System control block commands */
wdenk1df49e22002-09-17 21:37:55 +000046/* CU Commands */
Wolfgang Denkc570b2f2005-09-26 01:06:33 +020047#define CU_NOP 0x0000
48#define CU_START 0x0010
49#define CU_RESUME 0x0020
50#define CU_STATSADDR 0x0040 /* Load Dump Statistics ctrs addr */
51#define CU_SHOWSTATS 0x0050 /* Dump statistics counters. */
52#define CU_ADDR_LOAD 0x0060 /* Base address to add to CU commands */
53#define CU_DUMPSTATS 0x0070 /* Dump then reset stats counters. */
wdenk1df49e22002-09-17 21:37:55 +000054
55/* RUC Commands */
Wolfgang Denkc570b2f2005-09-26 01:06:33 +020056#define RUC_NOP 0x0000
57#define RUC_START 0x0001
58#define RUC_RESUME 0x0002
59#define RUC_ABORT 0x0004
60#define RUC_ADDR_LOAD 0x0006 /* (seems not to clear on acceptance) */
61#define RUC_RESUMENR 0x0007
wdenk1df49e22002-09-17 21:37:55 +000062
Wolfgang Denkc570b2f2005-09-26 01:06:33 +020063#define CU_CMD_MASK 0x00f0
64#define RU_CMD_MASK 0x0007
wdenk1df49e22002-09-17 21:37:55 +000065
Wolfgang Denkc570b2f2005-09-26 01:06:33 +020066#define SCB_M 0x0100 /* 0 = enable interrupt, 1 = disable */
67#define SCB_SWI 0x0200 /* 1 - cause device to interrupt */
wdenk1df49e22002-09-17 21:37:55 +000068
Wolfgang Denkc570b2f2005-09-26 01:06:33 +020069#define CU_STATUS_MASK 0x00C0
70#define RU_STATUS_MASK 0x003C
wdenk1df49e22002-09-17 21:37:55 +000071
Marek Vasutdb9f1812020-05-23 13:17:03 +020072#define RU_STATUS_IDLE (0 << 2)
73#define RU_STATUS_SUS (1 << 2)
74#define RU_STATUS_NORES (2 << 2)
75#define RU_STATUS_READY (4 << 2)
76#define RU_STATUS_NO_RBDS_SUS ((1 << 2) | (8 << 2))
77#define RU_STATUS_NO_RBDS_NORES ((2 << 2) | (8 << 2))
78#define RU_STATUS_NO_RBDS_READY ((4 << 2) | (8 << 2))
wdenk1df49e22002-09-17 21:37:55 +000079
Marek Vasutaba283d2020-05-23 12:49:16 +020080/* 82559 Port interface commands. */
wdenk1df49e22002-09-17 21:37:55 +000081#define I82559_RESET 0x00000000 /* Software reset */
82#define I82559_SELFTEST 0x00000001 /* 82559 Selftest command */
83#define I82559_SELECTIVE_RESET 0x00000002
84#define I82559_DUMP 0x00000003
85#define I82559_DUMP_WAKEUP 0x00000007
86
Marek Vasutaba283d2020-05-23 12:49:16 +020087/* 82559 Eeprom interface. */
wdenk1df49e22002-09-17 21:37:55 +000088#define EE_SHIFT_CLK 0x01 /* EEPROM shift clock. */
89#define EE_CS 0x02 /* EEPROM chip select. */
90#define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */
91#define EE_WRITE_0 0x01
92#define EE_WRITE_1 0x05
93#define EE_DATA_READ 0x08 /* EEPROM chip data out. */
94#define EE_ENB (0x4800 | EE_CS)
95#define EE_CMD_BITS 3
96#define EE_DATA_BITS 16
97
Marek Vasutaba283d2020-05-23 12:49:16 +020098/* The EEPROM commands include the alway-set leading bit. */
wdenk1df49e22002-09-17 21:37:55 +000099#define EE_EWENB_CMD (4 << addr_len)
100#define EE_WRITE_CMD (5 << addr_len)
101#define EE_READ_CMD (6 << addr_len)
102#define EE_ERASE_CMD (7 << addr_len)
103
Marek Vasutaba283d2020-05-23 12:49:16 +0200104/* Receive frame descriptors. */
Marek Vasutf3878f52020-05-23 13:52:50 +0200105struct eepro100_rxfd {
Marek Vasutd47cf872020-05-23 15:02:47 +0200106 u16 status;
107 u16 control;
108 u32 link; /* struct eepro100_rxfd * */
109 u32 rx_buf_addr; /* void * */
110 u32 count;
wdenk1df49e22002-09-17 21:37:55 +0000111
Marek Vasutd47cf872020-05-23 15:02:47 +0200112 u8 data[PKTSIZE_ALIGN];
wdenk1df49e22002-09-17 21:37:55 +0000113};
114
115#define RFD_STATUS_C 0x8000 /* completion of received frame */
Wolfgang Denkc570b2f2005-09-26 01:06:33 +0200116#define RFD_STATUS_OK 0x2000 /* frame received with no errors */
wdenk1df49e22002-09-17 21:37:55 +0000117
Wolfgang Denkc570b2f2005-09-26 01:06:33 +0200118#define RFD_CONTROL_EL 0x8000 /* 1=last RFD in RFA */
119#define RFD_CONTROL_S 0x4000 /* 1=suspend RU after receiving frame */
120#define RFD_CONTROL_H 0x0010 /* 1=RFD is a header RFD */
121#define RFD_CONTROL_SF 0x0008 /* 0=simplified, 1=flexible mode */
wdenk1df49e22002-09-17 21:37:55 +0000122
Wolfgang Denkc570b2f2005-09-26 01:06:33 +0200123#define RFD_COUNT_MASK 0x3fff
124#define RFD_COUNT_F 0x4000
125#define RFD_COUNT_EOF 0x8000
wdenk1df49e22002-09-17 21:37:55 +0000126
Wolfgang Denkc570b2f2005-09-26 01:06:33 +0200127#define RFD_RX_CRC 0x0800 /* crc error */
128#define RFD_RX_ALIGNMENT 0x0400 /* alignment error */
129#define RFD_RX_RESOURCE 0x0200 /* out of space, no resources */
130#define RFD_RX_DMA_OVER 0x0100 /* DMA overrun */
131#define RFD_RX_SHORT 0x0080 /* short frame error */
132#define RFD_RX_LENGTH 0x0020
133#define RFD_RX_ERROR 0x0010 /* receive error */
134#define RFD_RX_NO_ADR_MATCH 0x0004 /* no address match */
135#define RFD_RX_IA_MATCH 0x0002 /* individual address does not match */
136#define RFD_RX_TCO 0x0001 /* TCO indication */
wdenk1df49e22002-09-17 21:37:55 +0000137
Marek Vasutaba283d2020-05-23 12:49:16 +0200138/* Transmit frame descriptors */
Marek Vasutd47cf872020-05-23 15:02:47 +0200139struct eepro100_txfd { /* Transmit frame descriptor set. */
140 u16 status;
141 u16 command;
142 u32 link; /* void * */
143 u32 tx_desc_addr; /* Always points to the tx_buf_addr element. */
144 s32 count;
wdenk1df49e22002-09-17 21:37:55 +0000145
Marek Vasutd47cf872020-05-23 15:02:47 +0200146 u32 tx_buf_addr0; /* void *, frame to be transmitted. */
147 s32 tx_buf_size0; /* Length of Tx frame. */
148 u32 tx_buf_addr1; /* void *, frame to be transmitted. */
149 s32 tx_buf_size1; /* Length of Tx frame. */
wdenk1df49e22002-09-17 21:37:55 +0000150};
151
Marek Vasutf3878f52020-05-23 13:52:50 +0200152#define TXCB_CMD_TRANSMIT 0x0004 /* transmit command */
153#define TXCB_CMD_SF 0x0008 /* 0=simplified, 1=flexible mode */
154#define TXCB_CMD_NC 0x0010 /* 0=CRC insert by controller */
155#define TXCB_CMD_I 0x2000 /* generate interrupt on completion */
156#define TXCB_CMD_S 0x4000 /* suspend on completion */
157#define TXCB_CMD_EL 0x8000 /* last command block in CBL */
wdenk1df49e22002-09-17 21:37:55 +0000158
Marek Vasutf3878f52020-05-23 13:52:50 +0200159#define TXCB_COUNT_MASK 0x3fff
160#define TXCB_COUNT_EOF 0x8000
wdenk1df49e22002-09-17 21:37:55 +0000161
Marek Vasutaba283d2020-05-23 12:49:16 +0200162/* The Speedo3 Rx and Tx frame/buffer descriptors. */
Marek Vasutd47cf872020-05-23 15:02:47 +0200163struct descriptor { /* A generic descriptor. */
164 u16 status;
165 u16 command;
166 u32 link; /* struct descriptor * */
wdenk1df49e22002-09-17 21:37:55 +0000167
168 unsigned char params[0];
169};
170
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171#define CONFIG_SYS_CMD_EL 0x8000
172#define CONFIG_SYS_CMD_SUSPEND 0x4000
173#define CONFIG_SYS_CMD_INT 0x2000
174#define CONFIG_SYS_CMD_IAS 0x0001 /* individual address setup */
175#define CONFIG_SYS_CMD_CONFIGURE 0x0002 /* configure */
wdenk1df49e22002-09-17 21:37:55 +0000176
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200177#define CONFIG_SYS_STATUS_C 0x8000
178#define CONFIG_SYS_STATUS_OK 0x2000
wdenk1df49e22002-09-17 21:37:55 +0000179
Marek Vasutaba283d2020-05-23 12:49:16 +0200180/* Misc. */
Wolfgang Denkc570b2f2005-09-26 01:06:33 +0200181#define NUM_RX_DESC PKTBUFSRX
Marek Vasutaba283d2020-05-23 12:49:16 +0200182#define NUM_TX_DESC 1 /* Number of TX descriptors */
wdenk1df49e22002-09-17 21:37:55 +0000183
184#define TOUT_LOOP 1000000
185
Marek Vasutf3878f52020-05-23 13:52:50 +0200186static struct eepro100_rxfd rx_ring[NUM_RX_DESC]; /* RX descriptor ring */
187static struct eepro100_txfd tx_ring[NUM_TX_DESC]; /* TX descriptor ring */
wdenk1df49e22002-09-17 21:37:55 +0000188static int rx_next; /* RX descriptor ring pointer */
189static int tx_next; /* TX descriptor ring pointer */
190static int tx_threshold;
191
192/*
193 * The parameters for a CmdConfigure operation.
194 * There are so many options that it would be difficult to document
195 * each bit. We mostly use the default or recommended settings.
196 */
wdenk1df49e22002-09-17 21:37:55 +0000197static const char i82558_config_cmd[] = {
198 22, 0x08, 0, 1, 0, 0, 0x22, 0x03, 1, /* 1=Use MII 0=Use AUI */
199 0, 0x2E, 0, 0x60, 0x08, 0x88,
200 0x68, 0, 0x40, 0xf2, 0x84, /* Disable FC */
201 0x31, 0x05,
202};
203
Wolfgang Denk03b00402014-10-21 15:23:32 +0200204#if defined(CONFIG_E500)
wdenk42d1f032003-10-15 23:53:47 +0000205#define bus_to_phys(a) (a)
206#define phys_to_bus(a) (a)
207#else
wdenk1df49e22002-09-17 21:37:55 +0000208#define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a)
209#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
wdenk42d1f032003-10-15 23:53:47 +0000210#endif
wdenk1df49e22002-09-17 21:37:55 +0000211
Marek Vasutdb9f1812020-05-23 13:17:03 +0200212static inline int INW(struct eth_device *dev, u_long addr)
wdenk1df49e22002-09-17 21:37:55 +0000213{
Marek Vasut81bdeea2020-05-23 14:14:45 +0200214 return le16_to_cpu(readw(addr + (void *)dev->iobase));
wdenk1df49e22002-09-17 21:37:55 +0000215}
216
Marek Vasutdb9f1812020-05-23 13:17:03 +0200217static inline void OUTW(struct eth_device *dev, int command, u_long addr)
wdenk1df49e22002-09-17 21:37:55 +0000218{
Marek Vasut81bdeea2020-05-23 14:14:45 +0200219 writew(cpu_to_le16(command), addr + (void *)dev->iobase);
wdenk1df49e22002-09-17 21:37:55 +0000220}
221
Marek Vasutdb9f1812020-05-23 13:17:03 +0200222static inline void OUTL(struct eth_device *dev, int command, u_long addr)
wdenk1df49e22002-09-17 21:37:55 +0000223{
Marek Vasut81bdeea2020-05-23 14:14:45 +0200224 writel(cpu_to_le32(command), addr + (void *)dev->iobase);
wdenk1df49e22002-09-17 21:37:55 +0000225}
226
Jon Loeliger07d38a12007-07-09 17:30:01 -0500227#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
Marek Vasutdb9f1812020-05-23 13:17:03 +0200228static inline int INL(struct eth_device *dev, u_long addr)
Wolfgang Denka9127332005-09-26 00:39:59 +0200229{
Marek Vasut81bdeea2020-05-23 14:14:45 +0200230 return le32_to_cpu(readl(addr + (void *)dev->iobase));
Wolfgang Denka9127332005-09-26 00:39:59 +0200231}
232
Marek Vasutdb9f1812020-05-23 13:17:03 +0200233static int get_phyreg(struct eth_device *dev, unsigned char addr,
Marek Vasut773af832020-05-23 13:21:43 +0200234 unsigned char reg, unsigned short *value)
Wolfgang Denka9127332005-09-26 00:39:59 +0200235{
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200236 int cmd;
237 int timeout = 50;
Wolfgang Denka9127332005-09-26 00:39:59 +0200238
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200239 /* read requested data */
240 cmd = (2 << 26) | ((addr & 0x1f) << 21) | ((reg & 0x1f) << 16);
Marek Vasutf3878f52020-05-23 13:52:50 +0200241 OUTL(dev, cmd, SCB_CTRL_MDI);
Wolfgang Denkc570b2f2005-09-26 01:06:33 +0200242
Wolfgang Denka9127332005-09-26 00:39:59 +0200243 do {
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200244 udelay(1000);
Marek Vasutf3878f52020-05-23 13:52:50 +0200245 cmd = INL(dev, SCB_CTRL_MDI);
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200246 } while (!(cmd & (1 << 28)) && (--timeout));
247
248 if (timeout == 0)
249 return -1;
Wolfgang Denka9127332005-09-26 00:39:59 +0200250
Marek Vasutdb9f1812020-05-23 13:17:03 +0200251 *value = (unsigned short)(cmd & 0xffff);
Wolfgang Denkc570b2f2005-09-26 01:06:33 +0200252
Wolfgang Denka9127332005-09-26 00:39:59 +0200253 return 0;
254}
255
Marek Vasutdb9f1812020-05-23 13:17:03 +0200256static int set_phyreg(struct eth_device *dev, unsigned char addr,
Marek Vasut773af832020-05-23 13:21:43 +0200257 unsigned char reg, unsigned short value)
Wolfgang Denka9127332005-09-26 00:39:59 +0200258{
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200259 int cmd;
260 int timeout = 50;
Wolfgang Denka9127332005-09-26 00:39:59 +0200261
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200262 /* write requested data */
263 cmd = (1 << 26) | ((addr & 0x1f) << 21) | ((reg & 0x1f) << 16);
Marek Vasutf3878f52020-05-23 13:52:50 +0200264 OUTL(dev, cmd | value, SCB_CTRL_MDI);
Wolfgang Denka9127332005-09-26 00:39:59 +0200265
Marek Vasutf3878f52020-05-23 13:52:50 +0200266 while (!(INL(dev, SCB_CTRL_MDI) & (1 << 28)) && (--timeout))
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200267 udelay(1000);
268
269 if (timeout == 0)
270 return -1;
Wolfgang Denka9127332005-09-26 00:39:59 +0200271
272 return 0;
273}
Wolfgang Denka9127332005-09-26 00:39:59 +0200274
Marek Vasutaba283d2020-05-23 12:49:16 +0200275/*
276 * Check if given phyaddr is valid, i.e. there is a PHY connected.
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200277 * Do this by checking model value field from ID2 register.
278 */
Marek Vasut7a308732020-05-23 13:23:13 +0200279static struct eth_device *verify_phyaddr(const char *devname,
Marek Vasut773af832020-05-23 13:21:43 +0200280 unsigned char addr)
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200281{
282 struct eth_device *dev;
283 unsigned short value;
284 unsigned char model;
285
286 dev = eth_get_dev_by_name(devname);
Marek Vasutb0131732020-05-23 13:45:41 +0200287 if (!dev) {
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200288 printf("%s: no such device\n", devname);
289 return NULL;
290 }
291
292 /* read id2 register */
Mike Frysinger8ef583a2010-12-23 15:40:12 -0500293 if (get_phyreg(dev, addr, MII_PHYSID2, &value) != 0) {
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200294 printf("%s: mii read timeout!\n", devname);
295 return NULL;
296 }
297
298 /* get model */
299 model = (unsigned char)((value >> 4) & 0x003f);
300
301 if (model == 0) {
302 printf("%s: no PHY at address %d\n", devname, addr);
303 return NULL;
304 }
305
306 return dev;
307}
308
Joe Hershberger5a49f172016-08-08 11:28:38 -0500309static int eepro100_miiphy_read(struct mii_dev *bus, int addr, int devad,
310 int reg)
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200311{
Joe Hershberger5a49f172016-08-08 11:28:38 -0500312 unsigned short value = 0;
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200313 struct eth_device *dev;
314
Joe Hershberger5a49f172016-08-08 11:28:38 -0500315 dev = verify_phyaddr(bus->name, addr);
Marek Vasutb0131732020-05-23 13:45:41 +0200316 if (!dev)
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200317 return -1;
318
Joe Hershberger5a49f172016-08-08 11:28:38 -0500319 if (get_phyreg(dev, addr, reg, &value) != 0) {
320 printf("%s: mii read timeout!\n", bus->name);
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200321 return -1;
322 }
323
Joe Hershberger5a49f172016-08-08 11:28:38 -0500324 return value;
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200325}
326
Joe Hershberger5a49f172016-08-08 11:28:38 -0500327static int eepro100_miiphy_write(struct mii_dev *bus, int addr, int devad,
328 int reg, u16 value)
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200329{
330 struct eth_device *dev;
331
Joe Hershberger5a49f172016-08-08 11:28:38 -0500332 dev = verify_phyaddr(bus->name, addr);
Marek Vasutb0131732020-05-23 13:45:41 +0200333 if (!dev)
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200334 return -1;
335
336 if (set_phyreg(dev, addr, reg, value) != 0) {
Joe Hershberger5a49f172016-08-08 11:28:38 -0500337 printf("%s: mii write timeout!\n", bus->name);
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200338 return -1;
339 }
340
341 return 0;
342}
343
Jon Loeliger07d38a12007-07-09 17:30:01 -0500344#endif
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200345
Marek Vasut047a8002020-05-23 15:07:30 +0200346static void init_rx_ring(struct eth_device *dev)
347{
348 int i;
349
350 for (i = 0; i < NUM_RX_DESC; i++) {
351 rx_ring[i].status = 0;
352 rx_ring[i].control = (i == NUM_RX_DESC - 1) ?
353 cpu_to_le16 (RFD_CONTROL_S) : 0;
354 rx_ring[i].link =
355 cpu_to_le32(phys_to_bus((u32)&rx_ring[(i + 1) %
356 NUM_RX_DESC]));
357 rx_ring[i].rx_buf_addr = 0xffffffff;
358 rx_ring[i].count = cpu_to_le32(PKTSIZE_ALIGN << 16);
359 }
360
361 flush_dcache_range((unsigned long)rx_ring,
362 (unsigned long)rx_ring +
363 (sizeof(*rx_ring) * NUM_RX_DESC));
364
365 rx_next = 0;
366}
367
368static void purge_tx_ring(struct eth_device *dev)
369{
370 tx_next = 0;
371 tx_threshold = 0x01208000;
372 memset(tx_ring, 0, sizeof(*tx_ring) * NUM_TX_DESC);
373
374 flush_dcache_range((unsigned long)tx_ring,
375 (unsigned long)tx_ring +
376 (sizeof(*tx_ring) * NUM_TX_DESC));
377}
378
Marek Vasutaba283d2020-05-23 12:49:16 +0200379/* Wait for the chip get the command. */
Marek Vasutdb9f1812020-05-23 13:17:03 +0200380static int wait_for_eepro100(struct eth_device *dev)
wdenk1df49e22002-09-17 21:37:55 +0000381{
382 int i;
383
Marek Vasutf3878f52020-05-23 13:52:50 +0200384 for (i = 0; INW(dev, SCB_CMD) & (CU_CMD_MASK | RU_CMD_MASK); i++) {
Marek Vasut9b12ff92020-05-23 13:20:14 +0200385 if (i >= TOUT_LOOP)
wdenk1df49e22002-09-17 21:37:55 +0000386 return 0;
wdenk1df49e22002-09-17 21:37:55 +0000387 }
388
389 return 1;
390}
391
Marek Vasut95655b92020-05-23 14:30:31 +0200392static int eepro100_txcmd_send(struct eth_device *dev,
393 struct eepro100_txfd *desc)
394{
395 u16 rstat;
396 int i = 0;
397
Marek Vasut5116aae2020-05-23 14:55:26 +0200398 flush_dcache_range((unsigned long)desc,
399 (unsigned long)desc + sizeof(*desc));
400
Marek Vasut95655b92020-05-23 14:30:31 +0200401 if (!wait_for_eepro100(dev))
402 return -ETIMEDOUT;
403
404 OUTL(dev, phys_to_bus((u32)desc), SCB_POINTER);
405 OUTW(dev, SCB_M | CU_START, SCB_CMD);
406
407 while (true) {
Marek Vasut5116aae2020-05-23 14:55:26 +0200408 invalidate_dcache_range((unsigned long)desc,
409 (unsigned long)desc + sizeof(*desc));
Marek Vasut95655b92020-05-23 14:30:31 +0200410 rstat = le16_to_cpu(desc->status);
411 if (rstat & CONFIG_SYS_STATUS_C)
412 break;
413
414 if (i++ >= TOUT_LOOP) {
415 printf("%s: Tx error buffer not ready\n", dev->name);
416 return -EINVAL;
417 }
418 }
419
Marek Vasut5116aae2020-05-23 14:55:26 +0200420 invalidate_dcache_range((unsigned long)desc,
421 (unsigned long)desc + sizeof(*desc));
Marek Vasut95655b92020-05-23 14:30:31 +0200422 rstat = le16_to_cpu(desc->status);
423
424 if (!(rstat & CONFIG_SYS_STATUS_OK)) {
425 printf("TX error status = 0x%08X\n", rstat);
426 return -EIO;
427 }
428
429 return 0;
430}
431
Marek Vasut047a8002020-05-23 15:07:30 +0200432/* SROM Read. */
433static int read_eeprom(struct eth_device *dev, int location, int addr_len)
434{
435 unsigned short retval = 0;
436 int read_cmd = location | EE_READ_CMD;
437 int i;
438
439 OUTW(dev, EE_ENB & ~EE_CS, SCB_EEPROM);
440 OUTW(dev, EE_ENB, SCB_EEPROM);
441
442 /* Shift the read command bits out. */
443 for (i = 12; i >= 0; i--) {
444 short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
445
446 OUTW(dev, EE_ENB | dataval, SCB_EEPROM);
447 udelay(1);
448 OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCB_EEPROM);
449 udelay(1);
450 }
451 OUTW(dev, EE_ENB, SCB_EEPROM);
452
453 for (i = 15; i >= 0; i--) {
454 OUTW(dev, EE_ENB | EE_SHIFT_CLK, SCB_EEPROM);
455 udelay(1);
456 retval = (retval << 1) |
457 ((INW(dev, SCB_EEPROM) & EE_DATA_READ) ? 1 : 0);
458 OUTW(dev, EE_ENB, SCB_EEPROM);
459 udelay(1);
460 }
461
462 /* Terminate the EEPROM access. */
463 OUTW(dev, EE_ENB & ~EE_CS, SCB_EEPROM);
464 return retval;
465}
466
467static struct pci_device_id supported[] = {
468 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82557},
469 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559},
470 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559ER},
471 {}
472};
473
474static void read_hw_addr(struct eth_device *dev, bd_t *bis)
475{
476 u16 sum = 0;
477 int i, j;
478 int addr_len = read_eeprom(dev, 0, 6) == 0xffff ? 8 : 6;
479
480 for (j = 0, i = 0; i < 0x40; i++) {
481 u16 value = read_eeprom(dev, i, addr_len);
482
483 sum += value;
484 if (i < 3) {
485 dev->enetaddr[j++] = value;
486 dev->enetaddr[j++] = value >> 8;
487 }
488 }
489
490 if (sum != 0xBABA) {
491 memset(dev->enetaddr, 0, ETH_ALEN);
492 debug("%s: Invalid EEPROM checksum %#4.4x, check settings before activating this device!\n",
493 dev->name, sum);
494 }
495}
496
Marek Vasut7a308732020-05-23 13:23:13 +0200497static int eepro100_init(struct eth_device *dev, bd_t *bis)
wdenk1df49e22002-09-17 21:37:55 +0000498{
Marek Vasut95655b92020-05-23 14:30:31 +0200499 struct eepro100_txfd *ias_cmd, *cfg_cmd;
500 int ret, status = -1;
wdenk1df49e22002-09-17 21:37:55 +0000501 int tx_cur;
wdenk1df49e22002-09-17 21:37:55 +0000502
Marek Vasutaba283d2020-05-23 12:49:16 +0200503 /* Reset the ethernet controller */
Marek Vasutf3878f52020-05-23 13:52:50 +0200504 OUTL(dev, I82559_SELECTIVE_RESET, SCB_PORT);
Simon Glass07e11142020-05-10 11:40:10 -0600505 udelay(20);
wdenk1df49e22002-09-17 21:37:55 +0000506
Marek Vasutf3878f52020-05-23 13:52:50 +0200507 OUTL(dev, I82559_RESET, SCB_PORT);
Simon Glass07e11142020-05-10 11:40:10 -0600508 udelay(20);
wdenk1df49e22002-09-17 21:37:55 +0000509
Marek Vasutdb9f1812020-05-23 13:17:03 +0200510 if (!wait_for_eepro100(dev)) {
511 printf("Error: Can not reset ethernet controller.\n");
Marek Vasutf3878f52020-05-23 13:52:50 +0200512 goto done;
wdenk1df49e22002-09-17 21:37:55 +0000513 }
Marek Vasutf3878f52020-05-23 13:52:50 +0200514 OUTL(dev, 0, SCB_POINTER);
515 OUTW(dev, SCB_M | RUC_ADDR_LOAD, SCB_CMD);
wdenk1df49e22002-09-17 21:37:55 +0000516
Marek Vasutdb9f1812020-05-23 13:17:03 +0200517 if (!wait_for_eepro100(dev)) {
518 printf("Error: Can not reset ethernet controller.\n");
Marek Vasutf3878f52020-05-23 13:52:50 +0200519 goto done;
wdenk1df49e22002-09-17 21:37:55 +0000520 }
Marek Vasutf3878f52020-05-23 13:52:50 +0200521 OUTL(dev, 0, SCB_POINTER);
522 OUTW(dev, SCB_M | CU_ADDR_LOAD, SCB_CMD);
wdenk1df49e22002-09-17 21:37:55 +0000523
Marek Vasutaba283d2020-05-23 12:49:16 +0200524 /* Initialize Rx and Tx rings. */
Marek Vasutdb9f1812020-05-23 13:17:03 +0200525 init_rx_ring(dev);
526 purge_tx_ring(dev);
wdenk1df49e22002-09-17 21:37:55 +0000527
Marek Vasutaba283d2020-05-23 12:49:16 +0200528 /* Tell the adapter where the RX ring is located. */
Marek Vasutdb9f1812020-05-23 13:17:03 +0200529 if (!wait_for_eepro100(dev)) {
530 printf("Error: Can not reset ethernet controller.\n");
Marek Vasutf3878f52020-05-23 13:52:50 +0200531 goto done;
wdenk1df49e22002-09-17 21:37:55 +0000532 }
533
Marek Vasut5116aae2020-05-23 14:55:26 +0200534 /* RX ring cache was already flushed in init_rx_ring() */
Marek Vasutf3878f52020-05-23 13:52:50 +0200535 OUTL(dev, phys_to_bus((u32)&rx_ring[rx_next]), SCB_POINTER);
536 OUTW(dev, SCB_M | RUC_START, SCB_CMD);
wdenk1df49e22002-09-17 21:37:55 +0000537
538 /* Send the Configure frame */
539 tx_cur = tx_next;
540 tx_next = ((tx_next + 1) % NUM_TX_DESC);
541
Marek Vasut95655b92020-05-23 14:30:31 +0200542 cfg_cmd = &tx_ring[tx_cur];
Marek Vasutb0131732020-05-23 13:45:41 +0200543 cfg_cmd->command = cpu_to_le16(CONFIG_SYS_CMD_SUSPEND |
544 CONFIG_SYS_CMD_CONFIGURE);
wdenk1df49e22002-09-17 21:37:55 +0000545 cfg_cmd->status = 0;
Marek Vasutb0131732020-05-23 13:45:41 +0200546 cfg_cmd->link = cpu_to_le32(phys_to_bus((u32)&tx_ring[tx_next]));
wdenk1df49e22002-09-17 21:37:55 +0000547
Marek Vasut95655b92020-05-23 14:30:31 +0200548 memcpy(((struct descriptor *)cfg_cmd)->params, i82558_config_cmd,
Marek Vasut773af832020-05-23 13:21:43 +0200549 sizeof(i82558_config_cmd));
wdenk1df49e22002-09-17 21:37:55 +0000550
Marek Vasut95655b92020-05-23 14:30:31 +0200551 ret = eepro100_txcmd_send(dev, cfg_cmd);
552 if (ret) {
553 if (ret == -ETIMEDOUT)
554 printf("Error---CONFIG_SYS_CMD_CONFIGURE: Can not reset ethernet controller.\n");
Marek Vasutf3878f52020-05-23 13:52:50 +0200555 goto done;
wdenk1df49e22002-09-17 21:37:55 +0000556 }
557
Marek Vasutaba283d2020-05-23 12:49:16 +0200558 /* Send the Individual Address Setup frame */
wdenk1df49e22002-09-17 21:37:55 +0000559 tx_cur = tx_next;
560 tx_next = ((tx_next + 1) % NUM_TX_DESC);
561
Marek Vasut95655b92020-05-23 14:30:31 +0200562 ias_cmd = &tx_ring[tx_cur];
Marek Vasutb0131732020-05-23 13:45:41 +0200563 ias_cmd->command = cpu_to_le16(CONFIG_SYS_CMD_SUSPEND |
564 CONFIG_SYS_CMD_IAS);
wdenk1df49e22002-09-17 21:37:55 +0000565 ias_cmd->status = 0;
Marek Vasutb0131732020-05-23 13:45:41 +0200566 ias_cmd->link = cpu_to_le32(phys_to_bus((u32)&tx_ring[tx_next]));
wdenk1df49e22002-09-17 21:37:55 +0000567
Marek Vasut95655b92020-05-23 14:30:31 +0200568 memcpy(((struct descriptor *)ias_cmd)->params, dev->enetaddr, 6);
wdenk1df49e22002-09-17 21:37:55 +0000569
Marek Vasut95655b92020-05-23 14:30:31 +0200570 ret = eepro100_txcmd_send(dev, ias_cmd);
571 if (ret) {
572 if (ret == -ETIMEDOUT)
573 printf("Error: Can not reset ethernet controller.\n");
Marek Vasutf3878f52020-05-23 13:52:50 +0200574 goto done;
wdenk1df49e22002-09-17 21:37:55 +0000575 }
576
Ben Warren422b1a02008-01-09 18:15:53 -0500577 status = 0;
wdenk1df49e22002-09-17 21:37:55 +0000578
Marek Vasutf3878f52020-05-23 13:52:50 +0200579done:
wdenk1df49e22002-09-17 21:37:55 +0000580 return status;
581}
582
Joe Hershbergerbccbe612012-05-21 14:45:25 +0000583static int eepro100_send(struct eth_device *dev, void *packet, int length)
wdenk1df49e22002-09-17 21:37:55 +0000584{
Marek Vasut5116aae2020-05-23 14:55:26 +0200585 struct eepro100_txfd *desc;
Marek Vasut95655b92020-05-23 14:30:31 +0200586 int ret, status = -1;
wdenk1df49e22002-09-17 21:37:55 +0000587 int tx_cur;
588
589 if (length <= 0) {
Marek Vasutdb9f1812020-05-23 13:17:03 +0200590 printf("%s: bad packet size: %d\n", dev->name, length);
Marek Vasutf3878f52020-05-23 13:52:50 +0200591 goto done;
wdenk1df49e22002-09-17 21:37:55 +0000592 }
593
594 tx_cur = tx_next;
595 tx_next = (tx_next + 1) % NUM_TX_DESC;
596
Marek Vasut5116aae2020-05-23 14:55:26 +0200597 desc = &tx_ring[tx_cur];
598 desc->command = cpu_to_le16(TXCB_CMD_TRANSMIT | TXCB_CMD_SF |
599 TXCB_CMD_S | TXCB_CMD_EL);
600 desc->status = 0;
601 desc->count = cpu_to_le32(tx_threshold);
602 desc->link = cpu_to_le32(phys_to_bus((u32)&tx_ring[tx_next]));
603 desc->tx_desc_addr = cpu_to_le32(phys_to_bus((u32)&desc->tx_buf_addr0));
604 desc->tx_buf_addr0 = cpu_to_le32(phys_to_bus((u_long)packet));
605 desc->tx_buf_size0 = cpu_to_le32(length);
wdenk1df49e22002-09-17 21:37:55 +0000606
Marek Vasut95655b92020-05-23 14:30:31 +0200607 ret = eepro100_txcmd_send(dev, &tx_ring[tx_cur]);
608 if (ret) {
609 if (ret == -ETIMEDOUT)
610 printf("%s: Tx error ethernet controller not ready.\n",
611 dev->name);
Marek Vasutf3878f52020-05-23 13:52:50 +0200612 goto done;
wdenk1df49e22002-09-17 21:37:55 +0000613 }
614
615 status = length;
616
Marek Vasutf3878f52020-05-23 13:52:50 +0200617done:
wdenk1df49e22002-09-17 21:37:55 +0000618 return status;
619}
620
Marek Vasutdb9f1812020-05-23 13:17:03 +0200621static int eepro100_recv(struct eth_device *dev)
wdenk1df49e22002-09-17 21:37:55 +0000622{
Marek Vasut5116aae2020-05-23 14:55:26 +0200623 struct eepro100_rxfd *desc;
wdenk1df49e22002-09-17 21:37:55 +0000624 int rx_prev, length = 0;
Marek Vasut5116aae2020-05-23 14:55:26 +0200625 u16 status, stat;
wdenk1df49e22002-09-17 21:37:55 +0000626
Marek Vasutf3878f52020-05-23 13:52:50 +0200627 stat = INW(dev, SCB_STATUS);
628 OUTW(dev, stat & SCB_STATUS_RNR, SCB_STATUS);
wdenk1df49e22002-09-17 21:37:55 +0000629
630 for (;;) {
Marek Vasut5116aae2020-05-23 14:55:26 +0200631 desc = &rx_ring[rx_next];
632 invalidate_dcache_range((unsigned long)desc,
633 (unsigned long)desc + sizeof(*desc));
634 status = le16_to_cpu(desc->status);
wdenk1df49e22002-09-17 21:37:55 +0000635
Marek Vasut9b12ff92020-05-23 13:20:14 +0200636 if (!(status & RFD_STATUS_C))
wdenk1df49e22002-09-17 21:37:55 +0000637 break;
wdenk1df49e22002-09-17 21:37:55 +0000638
Marek Vasutaba283d2020-05-23 12:49:16 +0200639 /* Valid frame status. */
wdenk1df49e22002-09-17 21:37:55 +0000640 if ((status & RFD_STATUS_OK)) {
Marek Vasutaba283d2020-05-23 12:49:16 +0200641 /* A valid frame received. */
Marek Vasut5116aae2020-05-23 14:55:26 +0200642 length = le32_to_cpu(desc->count) & 0x3fff;
wdenk1df49e22002-09-17 21:37:55 +0000643
Marek Vasutaba283d2020-05-23 12:49:16 +0200644 /* Pass the packet up to the protocol layers. */
Marek Vasut5116aae2020-05-23 14:55:26 +0200645 net_process_received_packet((u8 *)desc->data, length);
wdenk1df49e22002-09-17 21:37:55 +0000646 } else {
Marek Vasutaba283d2020-05-23 12:49:16 +0200647 /* There was an error. */
Marek Vasutdb9f1812020-05-23 13:17:03 +0200648 printf("RX error status = 0x%08X\n", status);
wdenk1df49e22002-09-17 21:37:55 +0000649 }
650
Marek Vasut5116aae2020-05-23 14:55:26 +0200651 desc->control = cpu_to_le16(RFD_CONTROL_S);
652 desc->status = 0;
653 desc->count = cpu_to_le32(PKTSIZE_ALIGN << 16);
654 flush_dcache_range((unsigned long)desc,
655 (unsigned long)desc + sizeof(*desc));
wdenk1df49e22002-09-17 21:37:55 +0000656
657 rx_prev = (rx_next + NUM_RX_DESC - 1) % NUM_RX_DESC;
Marek Vasut5116aae2020-05-23 14:55:26 +0200658 desc = &rx_ring[rx_prev];
659 desc->control = 0;
660 flush_dcache_range((unsigned long)desc,
661 (unsigned long)desc + sizeof(*desc));
wdenk1df49e22002-09-17 21:37:55 +0000662
Marek Vasutaba283d2020-05-23 12:49:16 +0200663 /* Update entry information. */
wdenk1df49e22002-09-17 21:37:55 +0000664 rx_next = (rx_next + 1) % NUM_RX_DESC;
665 }
666
667 if (stat & SCB_STATUS_RNR) {
Marek Vasutdb9f1812020-05-23 13:17:03 +0200668 printf("%s: Receiver is not ready, restart it !\n", dev->name);
wdenk1df49e22002-09-17 21:37:55 +0000669
Marek Vasutaba283d2020-05-23 12:49:16 +0200670 /* Reinitialize Rx ring. */
Marek Vasutdb9f1812020-05-23 13:17:03 +0200671 init_rx_ring(dev);
wdenk1df49e22002-09-17 21:37:55 +0000672
Marek Vasutdb9f1812020-05-23 13:17:03 +0200673 if (!wait_for_eepro100(dev)) {
674 printf("Error: Can not restart ethernet controller.\n");
Marek Vasutf3878f52020-05-23 13:52:50 +0200675 goto done;
wdenk1df49e22002-09-17 21:37:55 +0000676 }
677
Marek Vasut5116aae2020-05-23 14:55:26 +0200678 /* RX ring cache was already flushed in init_rx_ring() */
Marek Vasutf3878f52020-05-23 13:52:50 +0200679 OUTL(dev, phys_to_bus((u32)&rx_ring[rx_next]), SCB_POINTER);
680 OUTW(dev, SCB_M | RUC_START, SCB_CMD);
wdenk1df49e22002-09-17 21:37:55 +0000681 }
682
Marek Vasutf3878f52020-05-23 13:52:50 +0200683done:
wdenk1df49e22002-09-17 21:37:55 +0000684 return length;
685}
686
Marek Vasutdb9f1812020-05-23 13:17:03 +0200687static void eepro100_halt(struct eth_device *dev)
wdenk1df49e22002-09-17 21:37:55 +0000688{
Marek Vasutaba283d2020-05-23 12:49:16 +0200689 /* Reset the ethernet controller */
Marek Vasutf3878f52020-05-23 13:52:50 +0200690 OUTL(dev, I82559_SELECTIVE_RESET, SCB_PORT);
Simon Glass07e11142020-05-10 11:40:10 -0600691 udelay(20);
wdenk1df49e22002-09-17 21:37:55 +0000692
Marek Vasutf3878f52020-05-23 13:52:50 +0200693 OUTL(dev, I82559_RESET, SCB_PORT);
Simon Glass07e11142020-05-10 11:40:10 -0600694 udelay(20);
wdenk1df49e22002-09-17 21:37:55 +0000695
Marek Vasutdb9f1812020-05-23 13:17:03 +0200696 if (!wait_for_eepro100(dev)) {
697 printf("Error: Can not reset ethernet controller.\n");
Marek Vasutf3878f52020-05-23 13:52:50 +0200698 goto done;
wdenk1df49e22002-09-17 21:37:55 +0000699 }
Marek Vasutf3878f52020-05-23 13:52:50 +0200700 OUTL(dev, 0, SCB_POINTER);
701 OUTW(dev, SCB_M | RUC_ADDR_LOAD, SCB_CMD);
wdenk1df49e22002-09-17 21:37:55 +0000702
Marek Vasutdb9f1812020-05-23 13:17:03 +0200703 if (!wait_for_eepro100(dev)) {
704 printf("Error: Can not reset ethernet controller.\n");
Marek Vasutf3878f52020-05-23 13:52:50 +0200705 goto done;
wdenk1df49e22002-09-17 21:37:55 +0000706 }
Marek Vasutf3878f52020-05-23 13:52:50 +0200707 OUTL(dev, 0, SCB_POINTER);
708 OUTW(dev, SCB_M | CU_ADDR_LOAD, SCB_CMD);
wdenk1df49e22002-09-17 21:37:55 +0000709
Marek Vasutf3878f52020-05-23 13:52:50 +0200710done:
wdenk1df49e22002-09-17 21:37:55 +0000711 return;
712}
713
Marek Vasut047a8002020-05-23 15:07:30 +0200714int eepro100_initialize(bd_t *bis)
wdenk1df49e22002-09-17 21:37:55 +0000715{
Marek Vasut047a8002020-05-23 15:07:30 +0200716 pci_dev_t devno;
717 int card_number = 0;
718 struct eth_device *dev;
719 u32 iobase, status;
720 int idx = 0;
wdenk1df49e22002-09-17 21:37:55 +0000721
Marek Vasut047a8002020-05-23 15:07:30 +0200722 while (1) {
723 /* Find PCI device */
724 devno = pci_find_devices(supported, idx++);
725 if (devno < 0)
726 break;
wdenk1df49e22002-09-17 21:37:55 +0000727
Marek Vasut047a8002020-05-23 15:07:30 +0200728 pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &iobase);
729 iobase &= ~0xf;
wdenk1df49e22002-09-17 21:37:55 +0000730
Marek Vasut047a8002020-05-23 15:07:30 +0200731 debug("eepro100: Intel i82559 PCI EtherExpressPro @0x%x\n",
732 iobase);
wdenk1df49e22002-09-17 21:37:55 +0000733
Marek Vasut047a8002020-05-23 15:07:30 +0200734 pci_write_config_dword(devno, PCI_COMMAND,
735 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
wdenk1df49e22002-09-17 21:37:55 +0000736
Marek Vasut047a8002020-05-23 15:07:30 +0200737 /* Check if I/O accesses and Bus Mastering are enabled. */
738 pci_read_config_dword(devno, PCI_COMMAND, &status);
739 if (!(status & PCI_COMMAND_MEMORY)) {
740 printf("Error: Can not enable MEM access.\n");
741 continue;
wdenk1df49e22002-09-17 21:37:55 +0000742 }
Marek Vasut047a8002020-05-23 15:07:30 +0200743
744 if (!(status & PCI_COMMAND_MASTER)) {
745 printf("Error: Can not enable Bus Mastering.\n");
746 continue;
747 }
748
749 dev = (struct eth_device *)malloc(sizeof(*dev));
750 if (!dev) {
751 printf("eepro100: Can not allocate memory\n");
752 break;
753 }
754 memset(dev, 0, sizeof(*dev));
755
756 sprintf(dev->name, "i82559#%d", card_number);
757 dev->priv = (void *)devno; /* this have to come before bus_to_phys() */
758 dev->iobase = bus_to_phys(iobase);
759 dev->init = eepro100_init;
760 dev->halt = eepro100_halt;
761 dev->send = eepro100_send;
762 dev->recv = eepro100_recv;
763
764 eth_register(dev);
765
766#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
767 /* register mii command access routines */
768 int retval;
769 struct mii_dev *mdiodev = mdio_alloc();
770
771 if (!mdiodev)
772 return -ENOMEM;
773 strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
774 mdiodev->read = eepro100_miiphy_read;
775 mdiodev->write = eepro100_miiphy_write;
776
777 retval = mdio_register(mdiodev);
778 if (retval < 0)
779 return retval;
780#endif
781
782 card_number++;
783
784 /* Set the latency timer for value. */
785 pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x20);
786
787 udelay(10 * 1000);
788
789 read_hw_addr(dev, bis);
wdenk1df49e22002-09-17 21:37:55 +0000790 }
791
Marek Vasut047a8002020-05-23 15:07:30 +0200792 return card_number;
wdenk1df49e22002-09-17 21:37:55 +0000793}