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wdenk1df49e22002-09-17 21:37:55 +00001/*
2 * (C) Copyright 2001
3 * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * cpu.c
26 *
27 * CPU specific code
28 *
29 * written or collected and sometimes rewritten by
30 * Magnus Damm <damm@bitsmart.com>
31 *
32 * minor modifications by
33 * Wolfgang Denk <wd@denx.de>
34 *
35 * more modifications by
36 * Josh Huber <huber@mclx.com>
37 * added support for the 74xx series of cpus
38 * added support for the 7xx series of cpus
39 * made the code a little less hard-coded, and more auto-detectish
40 */
41
42#include <common.h>
43#include <command.h>
44#include <74xx_7xx.h>
45#include <asm/cache.h>
46
wdenkc7de8292002-11-19 11:04:11 +000047#ifdef CONFIG_AMIGAONEG3SE
48#include "../board/MAI/AmigaOneG3SE/via686.h"
49#include "../board/MAI/AmigaOneG3SE/memio.h"
50#endif
51
wdenk1df49e22002-09-17 21:37:55 +000052cpu_t
53get_cpu_type(void)
54{
55 uint pvr = get_pvr();
56 cpu_t type;
57
58 type = CPU_UNKNOWN;
59
60 switch (PVR_VER(pvr)) {
61 case 0x000c:
62 type = CPU_7400;
63 break;
64 case 0x0008:
65 type = CPU_750;
66
wdenk72755c72003-06-20 23:10:58 +000067 if (((pvr >> 8) & 0xff) == 0x01) {
wdenk1df49e22002-09-17 21:37:55 +000068 type = CPU_750CX; /* old CX (80100 and 8010x?)*/
69 } else if (((pvr >> 8) & 0xff) == 0x22) {
70 type = CPU_750CX; /* CX (82201,82202) and CXe (82214) */
71 } else if (((pvr >> 8) & 0xff) == 0x33) {
72 type = CPU_750CX; /* CXe (83311) */
73 } else if (((pvr >> 12) & 0xF) == 0x3) {
74 type = CPU_755;
wdenk72755c72003-06-20 23:10:58 +000075 }
76 break;
77
78 case 0x7000:
79 type = CPU_750FX;
wdenk1df49e22002-09-17 21:37:55 +000080 break;
81
82 case 0x800C:
83 type = CPU_7410;
84 break;
85
wdenk72755c72003-06-20 23:10:58 +000086 case 0x8000:
wdenk1df49e22002-09-17 21:37:55 +000087 type = CPU_7450;
88 break;
89
90 default:
91 break;
92 }
93
94 return type;
95}
96
97/* ------------------------------------------------------------------------- */
98
99#if !defined(CONFIG_BAB7xx)
100int checkcpu (void)
101{
102 DECLARE_GLOBAL_DATA_PTR;
103
104 uint type = get_cpu_type();
105 uint pvr = get_pvr();
106 ulong clock = gd->cpu_clk;
107 char buf[32];
108 char *str;
109
110 puts ("CPU: ");
111
112 switch (type) {
113 case CPU_750CX:
114 printf ("750CX%s v%d.%d", (pvr&0xf0)?"e":"",
115 (pvr>>8) & 0xf,
116 pvr & 0xf);
117 goto PR_CLK;
118
119 case CPU_750:
120 str = "750";
121 break;
122
wdenk72755c72003-06-20 23:10:58 +0000123 case CPU_750FX:
124 str = "750FX";
125 break;
126
wdenk1df49e22002-09-17 21:37:55 +0000127 case CPU_755:
128 str = "755";
129 break;
130
131 case CPU_7400:
132 str = "MPC7400";
133 break;
134
wdenk72755c72003-06-20 23:10:58 +0000135 case CPU_7410:
136 str = "MPC7410";
wdenk1df49e22002-09-17 21:37:55 +0000137 break;
138
wdenk72755c72003-06-20 23:10:58 +0000139 case CPU_7450:
140 str = "MPC7450";
wdenk1df49e22002-09-17 21:37:55 +0000141 break;
142
143 default:
wdenk72755c72003-06-20 23:10:58 +0000144 printf("Unknown CPU -- PVR: 0x%08x\n", pvr);
wdenk1df49e22002-09-17 21:37:55 +0000145 return -1;
146 }
147
148 printf ("%s v%d.%d", str, (pvr >> 8) & 0xFF, pvr & 0xFF);
149PR_CLK:
150 printf (" @ %s MHz\n", strmhz(buf, clock));
151
152 return (0);
153}
154#endif
155/* these two functions are unimplemented currently [josh] */
156
wdenk72755c72003-06-20 23:10:58 +0000157/* -------------------------------------------------------------------- */
158/* L1 i-cache */
wdenk1df49e22002-09-17 21:37:55 +0000159
160int
161checkicache(void)
162{
163 return 0; /* XXX */
164}
165
wdenk72755c72003-06-20 23:10:58 +0000166/* -------------------------------------------------------------------- */
167/* L1 d-cache */
wdenk1df49e22002-09-17 21:37:55 +0000168
169int
170checkdcache(void)
171{
172 return 0; /* XXX */
173}
174
wdenk72755c72003-06-20 23:10:58 +0000175/* -------------------------------------------------------------------- */
wdenk1df49e22002-09-17 21:37:55 +0000176
177static inline void
178soft_restart(unsigned long addr)
179{
180 /* SRR0 has system reset vector, SRR1 has default MSR value */
181 /* rfi restores MSR from SRR1 and sets the PC to the SRR0 value */
182
183 __asm__ __volatile__ ("mtspr 26, %0" :: "r" (addr));
184 __asm__ __volatile__ ("li 4, (1 << 6)" ::: "r4");
185 __asm__ __volatile__ ("mtspr 27, 4");
186 __asm__ __volatile__ ("rfi");
187
188 while(1); /* not reached */
189}
190
191
192#if !defined(CONFIG_PCIPPC2) && \
193 !defined(CONFIG_BAB7xx) && \
194 !defined(CONFIG_ELPPC)
195/* no generic way to do board reset. simply call soft_reset. */
196void
wdenk8bde7f72003-06-27 21:31:46 +0000197do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
wdenk1df49e22002-09-17 21:37:55 +0000198{
199 ulong addr;
200 /* flush and disable I/D cache */
201 __asm__ __volatile__ ("mfspr 3, 1008" ::: "r3");
202 __asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5");
203 __asm__ __volatile__ ("ori 4, 3, 0xc00" ::: "r4");
204 __asm__ __volatile__ ("andc 5, 3, 5" ::: "r5");
205 __asm__ __volatile__ ("sync");
206 __asm__ __volatile__ ("mtspr 1008, 4");
207 __asm__ __volatile__ ("isync");
208 __asm__ __volatile__ ("sync");
209 __asm__ __volatile__ ("mtspr 1008, 5");
210 __asm__ __volatile__ ("isync");
211 __asm__ __volatile__ ("sync");
212
213#ifdef CFG_RESET_ADDRESS
214 addr = CFG_RESET_ADDRESS;
215#else
216 /*
217 * note: when CFG_MONITOR_BASE points to a RAM address,
218 * CFG_MONITOR_BASE - sizeof (ulong) is usually a valid
219 * address. Better pick an address known to be invalid on your
220 * system and assign it to CFG_RESET_ADDRESS.
221 */
222 addr = CFG_MONITOR_BASE - sizeof (ulong);
223#endif
224 soft_restart(addr);
225 while(1); /* not reached */
226}
227#endif
228
229/* ------------------------------------------------------------------------- */
230
231/*
232 * For the 7400 the TB clock runs at 1/4 the cpu bus speed.
233 */
wdenkc7de8292002-11-19 11:04:11 +0000234#ifdef CONFIG_AMIGAONEG3SE
235unsigned long get_tbclk(void)
236{
237 DECLARE_GLOBAL_DATA_PTR;
238
239 return (gd->bus_clk / 4);
240}
241#else /* ! CONFIG_AMIGAONEG3SE */
242
243unsigned long get_tbclk (void)
wdenk1df49e22002-09-17 21:37:55 +0000244{
245 return CFG_BUS_HZ / 4;
246}
wdenkc7de8292002-11-19 11:04:11 +0000247#endif /* CONFIG_AMIGAONEG3SE */
wdenk1df49e22002-09-17 21:37:55 +0000248/* ------------------------------------------------------------------------- */
249
250#if defined(CONFIG_WATCHDOG)
251#if !defined(CONFIG_PCIPPC2) && !defined(CONFIG_BAB7xx)
252void
253watchdog_reset(void)
254{
255
256}
257#endif /* !CONFIG_PCIPPC2 && !CONFIG_BAB7xx */
258#endif /* CONFIG_WATCHDOG */
259
260/* ------------------------------------------------------------------------- */