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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 3a99481159bf21028acc6b0d66f7809c3c6f053d / . / arch / arm / dts / r8a779a0.dtsi
blob: dfd6ae8b564fb1ba19d591ee7fcec5f0f72dea75 [file] [log] [blame]
Marek Vasutb6ec11b2021-04-25 22:28:00 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the R-Car V3U (R8A779A0) SoC
4 *
5 * Copyright (C) 2020 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r8a779a0-cpg-mssr.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/power/r8a779a0-sysc.h>
11
12/ {
13 compatible = "renesas,r8a779a0";
14 #address-cells = <2>;
15 #size-cells = <2>;
16
17 aliases {
18 i2c0 = &i2c0;
19 i2c1 = &i2c1;
20 i2c2 = &i2c2;
21 i2c3 = &i2c3;
22 i2c4 = &i2c4;
23 i2c5 = &i2c5;
24 i2c6 = &i2c6;
25 };
26
27 cpus {
28 #address-cells = <1>;
29 #size-cells = <0>;
30
31 a76_0: cpu@0 {
32 compatible = "arm,cortex-a76";
33 reg = <0>;
34 device_type = "cpu";
35 power-domains = <&sysc R8A779A0_PD_A1E0D0C0>;
36 next-level-cache = <&L3_CA76_0>;
37 };
38
39 L3_CA76_0: cache-controller-0 {
40 compatible = "cache";
41 power-domains = <&sysc R8A779A0_PD_A2E0D0>;
42 cache-unified;
43 cache-level = <3>;
44 };
45 };
46
47 extal_clk: extal {
48 compatible = "fixed-clock";
49 #clock-cells = <0>;
50 /* This value must be overridden by the board */
51 clock-frequency = <0>;
52 };
53
54 extalr_clk: extalr {
55 compatible = "fixed-clock";
56 #clock-cells = <0>;
57 /* This value must be overridden by the board */
58 clock-frequency = <0>;
59 };
60
61 pmu_a76 {
62 compatible = "arm,cortex-a76-pmu";
63 interrupts-extended = <&gic GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
64 <&gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
65 <&gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
66 <&gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
67 };
68
69 /* External SCIF clock - to be overridden by boards that provide it */
70 scif_clk: scif {
71 compatible = "fixed-clock";
72 #clock-cells = <0>;
73 clock-frequency = <0>;
74 };
75
76 soc: soc {
77 compatible = "simple-bus";
78 interrupt-parent = <&gic>;
79 #address-cells = <2>;
80 #size-cells = <2>;
81 ranges;
82
83 rwdt: watchdog@e6020000 {
84 compatible = "renesas,r8a779a0-wdt",
85 "renesas,rcar-gen3-wdt";
86 reg = <0 0xe6020000 0 0x0c>;
87 clocks = <&cpg CPG_MOD 907>;
88 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
89 resets = <&cpg 907>;
90 status = "disabled";
91 };
92
93 pfc: pin-controller@e6050000 {
94 compatible = "renesas,pfc-r8a779a0";
95 reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>,
96 <0 0xe6058000 0 0x16c>, <0 0xe6058800 0 0x16c>,
97 <0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>,
98 <0 0xe6068000 0 0x16c>, <0 0xe6068800 0 0x16c>,
99 <0 0xe6069000 0 0x16c>, <0 0xe6069800 0 0x16c>;
100 };
101
102 gpio0: gpio@e6058180 {
103 compatible = "renesas,gpio-r8a779a0";
104 reg = <0 0xe6058180 0 0x54>;
105 interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>;
106 clocks = <&cpg CPG_MOD 916>;
107 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
108 resets = <&cpg 916>;
109 gpio-controller;
110 #gpio-cells = <2>;
111 gpio-ranges = <&pfc 0 0 28>;
112 interrupt-controller;
113 #interrupt-cells = <2>;
114 };
115
116 gpio1: gpio@e6050180 {
117 compatible = "renesas,gpio-r8a779a0";
118 reg = <0 0xe6050180 0 0x54>;
119 interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
120 clocks = <&cpg CPG_MOD 915>;
121 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
122 resets = <&cpg 915>;
123 gpio-controller;
124 #gpio-cells = <2>;
125 gpio-ranges = <&pfc 0 32 31>;
126 interrupt-controller;
127 #interrupt-cells = <2>;
128 };
129
130 gpio2: gpio@e6050980 {
131 compatible = "renesas,gpio-r8a779a0";
132 reg = <0 0xe6050980 0 0x54>;
133 interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
134 clocks = <&cpg CPG_MOD 915>;
135 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
136 resets = <&cpg 915>;
137 gpio-controller;
138 #gpio-cells = <2>;
139 gpio-ranges = <&pfc 0 64 25>;
140 interrupt-controller;
141 #interrupt-cells = <2>;
142 };
143
144 gpio3: gpio@e6058980 {
145 compatible = "renesas,gpio-r8a779a0";
146 reg = <0 0xe6058980 0 0x54>;
147 interrupts = <GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>;
148 clocks = <&cpg CPG_MOD 916>;
149 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
150 resets = <&cpg 916>;
151 gpio-controller;
152 #gpio-cells = <2>;
153 gpio-ranges = <&pfc 0 96 17>;
154 interrupt-controller;
155 #interrupt-cells = <2>;
156 };
157
158 gpio4: gpio@e6060180 {
159 compatible = "renesas,gpio-r8a779a0";
160 reg = <0 0xe6060180 0 0x54>;
161 interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>;
162 clocks = <&cpg CPG_MOD 917>;
163 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
164 resets = <&cpg 917>;
165 gpio-controller;
166 #gpio-cells = <2>;
167 gpio-ranges = <&pfc 0 128 27>;
168 interrupt-controller;
169 #interrupt-cells = <2>;
170 };
171
172 gpio5: gpio@e6060980 {
173 compatible = "renesas,gpio-r8a779a0";
174 reg = <0 0xe6060980 0 0x54>;
175 interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
176 clocks = <&cpg CPG_MOD 917>;
177 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
178 resets = <&cpg 917>;
179 gpio-controller;
180 #gpio-cells = <2>;
181 gpio-ranges = <&pfc 0 160 21>;
182 interrupt-controller;
183 #interrupt-cells = <2>;
184 };
185
186 gpio6: gpio@e6068180 {
187 compatible = "renesas,gpio-r8a779a0";
188 reg = <0 0xe6068180 0 0x54>;
189 interrupts = <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>;
190 clocks = <&cpg CPG_MOD 918>;
191 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
192 resets = <&cpg 918>;
193 gpio-controller;
194 #gpio-cells = <2>;
195 gpio-ranges = <&pfc 0 192 21>;
196 interrupt-controller;
197 #interrupt-cells = <2>;
198 };
199
200 gpio7: gpio@e6068980 {
201 compatible = "renesas,gpio-r8a779a0";
202 reg = <0 0xe6068980 0 0x54>;
203 interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>;
204 clocks = <&cpg CPG_MOD 918>;
205 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
206 resets = <&cpg 918>;
207 gpio-controller;
208 #gpio-cells = <2>;
209 gpio-ranges = <&pfc 0 224 21>;
210 interrupt-controller;
211 #interrupt-cells = <2>;
212 };
213
214 gpio8: gpio@e6069180 {
215 compatible = "renesas,gpio-r8a779a0";
216 reg = <0 0xe6069180 0 0x54>;
217 interrupts = <GIC_SPI 864 IRQ_TYPE_LEVEL_HIGH>;
218 clocks = <&cpg CPG_MOD 918>;
219 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
220 resets = <&cpg 918>;
221 gpio-controller;
222 #gpio-cells = <2>;
223 gpio-ranges = <&pfc 0 256 21>;
224 interrupt-controller;
225 #interrupt-cells = <2>;
226 };
227
228 gpio9: gpio@e6069980 {
229 compatible = "renesas,gpio-r8a779a0";
230 reg = <0 0xe6069980 0 0x54>;
231 interrupts = <GIC_SPI 868 IRQ_TYPE_LEVEL_HIGH>;
232 clocks = <&cpg CPG_MOD 918>;
233 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
234 resets = <&cpg 918>;
235 gpio-controller;
236 #gpio-cells = <2>;
237 gpio-ranges = <&pfc 0 288 21>;
238 interrupt-controller;
239 #interrupt-cells = <2>;
240 };
241
242 cpg: clock-controller@e6150000 {
243 compatible = "renesas,r8a779a0-cpg-mssr";
244 reg = <0 0xe6150000 0 0x4000>;
245 clocks = <&extal_clk>, <&extalr_clk>;
246 clock-names = "extal", "extalr";
247 #clock-cells = <2>;
248 #power-domain-cells = <0>;
249 #reset-cells = <1>;
250 };
251
252 rst: reset-controller@e6160000 {
253 compatible = "renesas,r8a779a0-rst";
254 reg = <0 0xe6160000 0 0x4000>;
255 };
256
257 sysc: system-controller@e6180000 {
258 compatible = "renesas,r8a779a0-sysc";
259 reg = <0 0xe6180000 0 0x4000>;
260 #power-domain-cells = <1>;
261 };
262
263 i2c0: i2c@e6500000 {
264 compatible = "renesas,i2c-r8a779a0",
265 "renesas,rcar-gen3-i2c";
266 reg = <0 0xe6500000 0 0x40>;
267 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
268 clocks = <&cpg CPG_MOD 518>;
269 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
270 resets = <&cpg 518>;
271 dmas = <&dmac1 0x91>, <&dmac1 0x90>;
272 dma-names = "tx", "rx";
273 i2c-scl-internal-delay-ns = <110>;
274 #address-cells = <1>;
275 #size-cells = <0>;
276 status = "disabled";
277 };
278
279 i2c1: i2c@e6508000 {
280 compatible = "renesas,i2c-r8a779a0",
281 "renesas,rcar-gen3-i2c";
282 reg = <0 0xe6508000 0 0x40>;
283 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
284 clocks = <&cpg CPG_MOD 519>;
285 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
286 resets = <&cpg 519>;
287 dmas = <&dmac1 0x93>, <&dmac1 0x92>;
288 dma-names = "tx", "rx";
289 i2c-scl-internal-delay-ns = <110>;
290 #address-cells = <1>;
291 #size-cells = <0>;
292 status = "disabled";
293 };
294
295 i2c2: i2c@e6510000 {
296 compatible = "renesas,i2c-r8a779a0",
297 "renesas,rcar-gen3-i2c";
298 reg = <0 0xe6510000 0 0x40>;
299 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
300 clocks = <&cpg CPG_MOD 520>;
301 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
302 resets = <&cpg 520>;
303 dmas = <&dmac1 0x95>, <&dmac1 0x94>;
304 dma-names = "tx", "rx";
305 i2c-scl-internal-delay-ns = <110>;
306 #address-cells = <1>;
307 #size-cells = <0>;
308 status = "disabled";
309 };
310
311 i2c3: i2c@e66d0000 {
312 compatible = "renesas,i2c-r8a779a0",
313 "renesas,rcar-gen3-i2c";
314 reg = <0 0xe66d0000 0 0x40>;
315 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
316 clocks = <&cpg CPG_MOD 521>;
317 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
318 resets = <&cpg 521>;
319 dmas = <&dmac1 0x97>, <&dmac1 0x96>;
320 dma-names = "tx", "rx";
321 i2c-scl-internal-delay-ns = <110>;
322 #address-cells = <1>;
323 #size-cells = <0>;
324 status = "disabled";
325 };
326
327 i2c4: i2c@e66d8000 {
328 compatible = "renesas,i2c-r8a779a0",
329 "renesas,rcar-gen3-i2c";
330 reg = <0 0xe66d8000 0 0x40>;
331 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
332 clocks = <&cpg CPG_MOD 522>;
333 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
334 resets = <&cpg 522>;
335 dmas = <&dmac1 0x99>, <&dmac1 0x98>;
336 dma-names = "tx", "rx";
337 i2c-scl-internal-delay-ns = <110>;
338 #address-cells = <1>;
339 #size-cells = <0>;
340 status = "disabled";
341 };
342
343 i2c5: i2c@e66e0000 {
344 compatible = "renesas,i2c-r8a779a0",
345 "renesas,rcar-gen3-i2c";
346 reg = <0 0xe66e0000 0 0x40>;
347 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
348 clocks = <&cpg CPG_MOD 523>;
349 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
350 resets = <&cpg 523>;
351 dmas = <&dmac1 0x9b>, <&dmac1 0x9a>;
352 dma-names = "tx", "rx";
353 i2c-scl-internal-delay-ns = <110>;
354 #address-cells = <1>;
355 #size-cells = <0>;
356 status = "disabled";
357 };
358
359 i2c6: i2c@e66e8000 {
360 compatible = "renesas,i2c-r8a779a0",
361 "renesas,rcar-gen3-i2c";
362 reg = <0 0xe66e8000 0 0x40>;
363 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
364 clocks = <&cpg CPG_MOD 524>;
365 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
366 resets = <&cpg 524>;
367 dmas = <&dmac1 0x9d>, <&dmac1 0x9c>;
368 dma-names = "tx", "rx";
369 i2c-scl-internal-delay-ns = <110>;
370 #address-cells = <1>;
371 #size-cells = <0>;
372 status = "disabled";
373 };
374
375 hscif0: serial@e6540000 {
376 compatible = "renesas,hscif-r8a779a0",
377 "renesas,rcar-gen3-hscif", "renesas,hscif";
378 reg = <0 0xe6540000 0 0x60>;
379 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
380 clocks = <&cpg CPG_MOD 514>,
381 <&cpg CPG_CORE R8A779A0_CLK_S1D2>,
382 <&scif_clk>;
383 clock-names = "fck", "brg_int", "scif_clk";
384 dmas = <&dmac1 0x31>, <&dmac1 0x30>;
385 dma-names = "tx", "rx";
386 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
387 resets = <&cpg 514>;
388 status = "disabled";
389 };
390
391 hscif1: serial@e6550000 {
392 compatible = "renesas,hscif-r8a779a0",
393 "renesas,rcar-gen3-hscif", "renesas,hscif";
394 reg = <0 0xe6550000 0 0x60>;
395 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
396 clocks = <&cpg CPG_MOD 515>,
397 <&cpg CPG_CORE R8A779A0_CLK_S1D2>,
398 <&scif_clk>;
399 clock-names = "fck", "brg_int", "scif_clk";
400 dmas = <&dmac1 0x33>, <&dmac1 0x32>;
401 dma-names = "tx", "rx";
402 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
403 resets = <&cpg 515>;
404 status = "disabled";
405 };
406
407 hscif2: serial@e6560000 {
408 compatible = "renesas,hscif-r8a779a0",
409 "renesas,rcar-gen3-hscif", "renesas,hscif";
410 reg = <0 0xe6560000 0 0x60>;
411 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
412 clocks = <&cpg CPG_MOD 516>,
413 <&cpg CPG_CORE R8A779A0_CLK_S1D2>,
414 <&scif_clk>;
415 clock-names = "fck", "brg_int", "scif_clk";
416 dmas = <&dmac1 0x35>, <&dmac1 0x34>;
417 dma-names = "tx", "rx";
418 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
419 resets = <&cpg 516>;
420 status = "disabled";
421 };
422
423 hscif3: serial@e66a0000 {
424 compatible = "renesas,hscif-r8a779a0",
425 "renesas,rcar-gen3-hscif", "renesas,hscif";
426 reg = <0 0xe66a0000 0 0x60>;
427 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
428 clocks = <&cpg CPG_MOD 517>,
429 <&cpg CPG_CORE R8A779A0_CLK_S1D2>,
430 <&scif_clk>;
431 clock-names = "fck", "brg_int", "scif_clk";
432 dmas = <&dmac1 0x37>, <&dmac1 0x36>;
433 dma-names = "tx", "rx";
434 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
435 resets = <&cpg 517>;
436 status = "disabled";
437 };
438
439 avb0: ethernet@e6800000 {
440 compatible = "renesas,etheravb-r8a779a0",
441 "renesas,etheravb-rcar-gen3";
442 reg = <0 0xe6800000 0 0x800>;
443 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
444 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
445 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
446 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
447 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
448 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
449 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
450 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
451 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
452 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
453 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
454 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
455 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
456 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
457 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
458 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
459 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
460 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
461 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
462 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
463 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
464 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
465 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
466 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
467 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
468 interrupt-names = "ch0", "ch1", "ch2", "ch3",
469 "ch4", "ch5", "ch6", "ch7",
470 "ch8", "ch9", "ch10", "ch11",
471 "ch12", "ch13", "ch14", "ch15",
472 "ch16", "ch17", "ch18", "ch19",
473 "ch20", "ch21", "ch22", "ch23",
474 "ch24";
475 clocks = <&cpg CPG_MOD 211>;
476 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
477 resets = <&cpg 211>;
478 phy-mode = "rgmii";
479 rx-internal-delay-ps = <0>;
480 tx-internal-delay-ps = <0>;
481 #address-cells = <1>;
482 #size-cells = <0>;
483 status = "disabled";
484 };
485
486 avb1: ethernet@e6810000 {
487 compatible = "renesas,etheravb-r8a779a0",
488 "renesas,etheravb-rcar-gen3";
489 reg = <0 0xe6810000 0 0x800>;
490 interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
491 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
492 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
493 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
494 <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>,
495 <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
496 <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>,
497 <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
498 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
499 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
500 <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>,
501 <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
502 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
503 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
504 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
505 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
506 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
507 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
508 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
509 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
510 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
511 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
512 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
513 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
514 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
515 interrupt-names = "ch0", "ch1", "ch2", "ch3",
516 "ch4", "ch5", "ch6", "ch7",
517 "ch8", "ch9", "ch10", "ch11",
518 "ch12", "ch13", "ch14", "ch15",
519 "ch16", "ch17", "ch18", "ch19",
520 "ch20", "ch21", "ch22", "ch23",
521 "ch24";
522 clocks = <&cpg CPG_MOD 212>;
523 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
524 resets = <&cpg 212>;
525 phy-mode = "rgmii";
526 rx-internal-delay-ps = <0>;
527 tx-internal-delay-ps = <0>;
528 #address-cells = <1>;
529 #size-cells = <0>;
530 status = "disabled";
531 };
532
533 avb2: ethernet@e6820000 {
534 compatible = "renesas,etheravb-r8a779a0",
535 "renesas,etheravb-rcar-gen3";
536 reg = <0 0xe6820000 0 0x1000>;
537 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
538 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
539 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
540 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
541 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
542 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
543 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
544 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
545 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
546 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
547 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
548 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
549 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
550 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
551 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
552 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
553 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
554 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
555 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
556 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
557 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
558 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
559 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
560 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
561 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
562 interrupt-names = "ch0", "ch1", "ch2", "ch3",
563 "ch4", "ch5", "ch6", "ch7",
564 "ch8", "ch9", "ch10", "ch11",
565 "ch12", "ch13", "ch14", "ch15",
566 "ch16", "ch17", "ch18", "ch19",
567 "ch20", "ch21", "ch22", "ch23",
568 "ch24";
569 clocks = <&cpg CPG_MOD 213>;
570 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
571 resets = <&cpg 213>;
572 phy-mode = "rgmii";
573 rx-internal-delay-ps = <0>;
574 tx-internal-delay-ps = <0>;
575 #address-cells = <1>;
576 #size-cells = <0>;
577 status = "disabled";
578 };
579
580 avb3: ethernet@e6830000 {
581 compatible = "renesas,etheravb-r8a779a0",
582 "renesas,etheravb-rcar-gen3";
583 reg = <0 0xe6830000 0 0x1000>;
584 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
585 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
586 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
587 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
588 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
589 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
590 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
591 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
592 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
593 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
594 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
595 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
596 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
597 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
598 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
599 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
600 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
601 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
602 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
603 <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
604 <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
605 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
606 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
607 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
608 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
609 interrupt-names = "ch0", "ch1", "ch2", "ch3",
610 "ch4", "ch5", "ch6", "ch7",
611 "ch8", "ch9", "ch10", "ch11",
612 "ch12", "ch13", "ch14", "ch15",
613 "ch16", "ch17", "ch18", "ch19",
614 "ch20", "ch21", "ch22", "ch23",
615 "ch24";
616 clocks = <&cpg CPG_MOD 214>;
617 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
618 resets = <&cpg 214>;
619 phy-mode = "rgmii";
620 rx-internal-delay-ps = <0>;
621 tx-internal-delay-ps = <0>;
622 #address-cells = <1>;
623 #size-cells = <0>;
624 status = "disabled";
625 };
626
627 avb4: ethernet@e6840000 {
628 compatible = "renesas,etheravb-r8a779a0",
629 "renesas,etheravb-rcar-gen3";
630 reg = <0 0xe6840000 0 0x1000>;
631 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
632 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>,
633 <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
634 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
635 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
636 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
637 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
638 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>,
639 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
640 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
641 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
642 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
643 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
644 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
645 <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
646 <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>,
647 <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>,
648 <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>,
649 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
650 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
651 <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
652 <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
653 <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
654 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
655 <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>;
656 interrupt-names = "ch0", "ch1", "ch2", "ch3",
657 "ch4", "ch5", "ch6", "ch7",
658 "ch8", "ch9", "ch10", "ch11",
659 "ch12", "ch13", "ch14", "ch15",
660 "ch16", "ch17", "ch18", "ch19",
661 "ch20", "ch21", "ch22", "ch23",
662 "ch24";
663 clocks = <&cpg CPG_MOD 215>;
664 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
665 resets = <&cpg 215>;
666 phy-mode = "rgmii";
667 rx-internal-delay-ps = <0>;
668 tx-internal-delay-ps = <0>;
669 #address-cells = <1>;
670 #size-cells = <0>;
671 status = "disabled";
672 };
673
674 avb5: ethernet@e6850000 {
675 compatible = "renesas,etheravb-r8a779a0",
676 "renesas,etheravb-rcar-gen3";
677 reg = <0 0xe6850000 0 0x1000>;
678 interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
679 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
680 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
681 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
682 <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
683 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
684 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
685 <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
686 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
687 <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
688 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
689 <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>,
690 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
691 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
692 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
693 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
694 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
695 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
696 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
697 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
698 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
699 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
700 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
701 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
702 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
703 interrupt-names = "ch0", "ch1", "ch2", "ch3",
704 "ch4", "ch5", "ch6", "ch7",
705 "ch8", "ch9", "ch10", "ch11",
706 "ch12", "ch13", "ch14", "ch15",
707 "ch16", "ch17", "ch18", "ch19",
708 "ch20", "ch21", "ch22", "ch23",
709 "ch24";
710 clocks = <&cpg CPG_MOD 216>;
711 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
712 resets = <&cpg 216>;
713 phy-mode = "rgmii";
714 rx-internal-delay-ps = <0>;
715 tx-internal-delay-ps = <0>;
716 #address-cells = <1>;
717 #size-cells = <0>;
718 status = "disabled";
719 };
720
721 scif0: serial@e6e60000 {
722 compatible = "renesas,scif-r8a779a0",
723 "renesas,rcar-gen3-scif", "renesas,scif";
724 reg = <0 0xe6e60000 0 64>;
725 interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>;
726 clocks = <&cpg CPG_MOD 702>,
727 <&cpg CPG_CORE R8A779A0_CLK_S1D2>,
728 <&scif_clk>;
729 clock-names = "fck", "brg_int", "scif_clk";
730 dmas = <&dmac1 0x51>, <&dmac1 0x50>;
731 dma-names = "tx", "rx";
732 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
733 resets = <&cpg 702>;
734 status = "disabled";
735 };
736
737 scif1: serial@e6e68000 {
738 compatible = "renesas,scif-r8a779a0",
739 "renesas,rcar-gen3-scif", "renesas,scif";
740 reg = <0 0xe6e68000 0 64>;
741 interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
742 clocks = <&cpg CPG_MOD 703>,
743 <&cpg CPG_CORE R8A779A0_CLK_S1D2>,
744 <&scif_clk>;
745 clock-names = "fck", "brg_int", "scif_clk";
746 dmas = <&dmac1 0x53>, <&dmac1 0x52>;
747 dma-names = "tx", "rx";
748 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
749 resets = <&cpg 703>;
750 status = "disabled";
751 };
752
753 scif3: serial@e6c50000 {
754 compatible = "renesas,scif-r8a779a0",
755 "renesas,rcar-gen3-scif", "renesas,scif";
756 reg = <0 0xe6c50000 0 64>;
757 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>;
758 clocks = <&cpg CPG_MOD 704>,
759 <&cpg CPG_CORE R8A779A0_CLK_S1D2>,
760 <&scif_clk>;
761 clock-names = "fck", "brg_int", "scif_clk";
762 dmas = <&dmac1 0x57>, <&dmac1 0x56>;
763 dma-names = "tx", "rx";
764 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
765 resets = <&cpg 704>;
766 status = "disabled";
767 };
768
769 scif4: serial@e6c40000 {
770 compatible = "renesas,scif-r8a779a0",
771 "renesas,rcar-gen3-scif", "renesas,scif";
772 reg = <0 0xe6c40000 0 64>;
773 interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>;
774 clocks = <&cpg CPG_MOD 705>,
775 <&cpg CPG_CORE R8A779A0_CLK_S1D2>,
776 <&scif_clk>;
777 clock-names = "fck", "brg_int", "scif_clk";
778 dmas = <&dmac1 0x59>, <&dmac1 0x58>;
779 dma-names = "tx", "rx";
780 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
781 resets = <&cpg 705>;
782 status = "disabled";
783 };
784
785 msiof0: spi@e6e90000 {
786 compatible = "renesas,msiof-r8a779a0",
787 "renesas,rcar-gen3-msiof";
788 reg = <0 0xe6e90000 0 0x0064>;
789 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
790 clocks = <&cpg CPG_MOD 618>;
791 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
792 resets = <&cpg 618>;
793 dmas = <&dmac1 0x41>, <&dmac1 0x40>;
794 dma-names = "tx", "rx";
795 #address-cells = <1>;
796 #size-cells = <0>;
797 status = "disabled";
798 };
799
800 msiof1: spi@e6ea0000 {
801 compatible = "renesas,msiof-r8a779a0",
802 "renesas,rcar-gen3-msiof";
803 reg = <0 0xe6ea0000 0 0x0064>;
804 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
805 clocks = <&cpg CPG_MOD 619>;
806 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
807 resets = <&cpg 619>;
808 dmas = <&dmac1 0x43>, <&dmac1 0x42>;
809 dma-names = "tx", "rx";
810 #address-cells = <1>;
811 #size-cells = <0>;
812 status = "disabled";
813 };
814
815 msiof2: spi@e6c00000 {
816 compatible = "renesas,msiof-r8a779a0",
817 "renesas,rcar-gen3-msiof";
818 reg = <0 0xe6c00000 0 0x0064>;
819 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
820 clocks = <&cpg CPG_MOD 620>;
821 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
822 resets = <&cpg 620>;
823 dmas = <&dmac1 0x45>, <&dmac1 0x44>;
824 dma-names = "tx", "rx";
825 #address-cells = <1>;
826 #size-cells = <0>;
827 status = "disabled";
828 };
829
830 msiof3: spi@e6c10000 {
831 compatible = "renesas,msiof-r8a779a0",
832 "renesas,rcar-gen3-msiof";
833 reg = <0 0xe6c10000 0 0x0064>;
834 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
835 clocks = <&cpg CPG_MOD 621>;
836 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
837 resets = <&cpg 621>;
838 dmas = <&dmac1 0x47>, <&dmac1 0x46>;
839 dma-names = "tx", "rx";
840 #address-cells = <1>;
841 #size-cells = <0>;
842 status = "disabled";
843 };
844
845 msiof4: spi@e6c20000 {
846 compatible = "renesas,msiof-r8a779a0",
847 "renesas,rcar-gen3-msiof";
848 reg = <0 0xe6c20000 0 0x0064>;
849 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
850 clocks = <&cpg CPG_MOD 622>;
851 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
852 resets = <&cpg 622>;
853 dmas = <&dmac1 0x49>, <&dmac1 0x48>;
854 dma-names = "tx", "rx";
855 #address-cells = <1>;
856 #size-cells = <0>;
857 status = "disabled";
858 };
859
860 msiof5: spi@e6c28000 {
861 compatible = "renesas,msiof-r8a779a0",
862 "renesas,rcar-gen3-msiof";
863 reg = <0 0xe6c28000 0 0x0064>;
864 interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>;
865 clocks = <&cpg CPG_MOD 623>;
866 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
867 resets = <&cpg 623>;
868 dmas = <&dmac1 0x4b>, <&dmac1 0x4a>;
869 dma-names = "tx", "rx";
870 #address-cells = <1>;
871 #size-cells = <0>;
872 status = "disabled";
873 };
874
875 dmac1: dma-controller@e7350000 {
876 compatible = "renesas,dmac-r8a779a0";
877 reg = <0 0xe7350000 0 0x1000>,
878 <0 0xe7300000 0 0x10000>;
879 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
880 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
881 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
882 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
883 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
884 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
885 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
886 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
887 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
888 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
889 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
890 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
891 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
892 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
893 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
894 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
895 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
896 interrupt-names = "error",
897 "ch0", "ch1", "ch2", "ch3", "ch4",
898 "ch5", "ch6", "ch7", "ch8", "ch9",
899 "ch10", "ch11", "ch12", "ch13",
900 "ch14", "ch15";
901 clocks = <&cpg CPG_MOD 709>;
902 clock-names = "fck";
903 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
904 resets = <&cpg 709>;
905 #dma-cells = <1>;
906 dma-channels = <16>;
907 };
908
909 dmac2: dma-controller@e7351000 {
910 compatible = "renesas,dmac-r8a779a0";
911 reg = <0 0xe7351000 0 0x1000>,
912 <0 0xe7310000 0 0x10000>;
913 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
914 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
915 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
916 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
917 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
918 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
919 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
920 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
921 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
922 interrupt-names = "error",
923 "ch0", "ch1", "ch2", "ch3", "ch4",
924 "ch5", "ch6", "ch7";
925 clocks = <&cpg CPG_MOD 710>;
926 clock-names = "fck";
927 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
928 resets = <&cpg 710>;
929 #dma-cells = <1>;
930 dma-channels = <8>;
931 };
932
933 mmc0: mmc@ee140000 {
934 compatible = "renesas,sdhi-r8a779a0",
935 "renesas,rcar-gen3-sdhi";
936 reg = <0 0xee140000 0 0x2000>;
937 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
938 clocks = <&cpg CPG_MOD 706>;
939 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
940 resets = <&cpg 706>;
941 max-frequency = <200000000>;
942 status = "disabled";
943 };
944
945 gic: interrupt-controller@f1000000 {
946 compatible = "arm,gic-v3";
947 #interrupt-cells = <3>;
948 #address-cells = <0>;
949 interrupt-controller;
950 reg = <0x0 0xf1000000 0 0x20000>,
951 <0x0 0xf1060000 0 0x110000>;
952 interrupts = <GIC_PPI 9
953 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
954 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
955 };
956
957 prr: chipid@fff00044 {
958 compatible = "renesas,prr";
959 reg = <0 0xfff00044 0 4>;
960 };
961 };
962
963 timer {
964 compatible = "arm,armv8-timer";
965 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
966 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
967 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
968 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
969 };
970};