blob: b07261d3db5a451c164f8f250d0e4574e41b41ae [file] [log] [blame]
Masahiro Yamada0b11dbf2015-07-26 02:46:26 +09001#
2# Multifunction miscellaneous devices
3#
4
5menu "Multifunction device drivers"
6
Thomas Chou4395e062015-10-07 20:20:51 +08007config MISC
8 bool "Enable Driver Model for Misc drivers"
9 depends on DM
10 help
11 Enable driver model for miscellaneous devices. This class is
12 used only for those do not fit other more general classes. A
13 set of generic read, write and ioctl methods may be used to
14 access the device.
15
Simon Glassaaba7032018-11-18 08:14:27 -070016config SPL_MISC
17 bool "Enable Driver Model for Misc drivers in SPL"
18 depends on SPL_DM
Sean Anderson38127742022-04-22 16:11:37 -040019 default MISC
Simon Glassaaba7032018-11-18 08:14:27 -070020 help
21 Enable driver model for miscellaneous devices. This class is
22 used only for those do not fit other more general classes. A
23 set of generic read, write and ioctl methods may be used to
24 access the device.
25
26config TPL_MISC
27 bool "Enable Driver Model for Misc drivers in TPL"
28 depends on TPL_DM
Sean Anderson38127742022-04-22 16:11:37 -040029 default MISC
30 help
31 Enable driver model for miscellaneous devices. This class is
32 used only for those do not fit other more general classes. A
33 set of generic read, write and ioctl methods may be used to
34 access the device.
35
36config VPL_MISC
37 bool "Enable Driver Model for Misc drivers in VPL"
38 depends on VPL_DM
39 default MISC
Simon Glassaaba7032018-11-18 08:14:27 -070040 help
41 Enable driver model for miscellaneous devices. This class is
42 used only for those do not fit other more general classes. A
43 set of generic read, write and ioctl methods may be used to
44 access the device.
45
Sean Andersonc8ce7ba2022-05-05 13:11:39 -040046config NVMEM
47 bool "NVMEM support"
48 help
49 This adds support for a common interface to different types of
50 non-volatile memory. Consumers can use nvmem-cells properties to look
51 up hardware configuration data such as MAC addresses and calibration
52 settings.
53
54config SPL_NVMEM
55 bool "NVMEM support in SPL"
56 help
57 This adds support for a common interface to different types of
58 non-volatile memory. Consumers can use nvmem-cells properties to look
59 up hardware configuration data such as MAC addresses and calibration
60 settings.
61
Thomas Chouca844dd2015-10-14 08:43:31 +080062config ALTERA_SYSID
63 bool "Altera Sysid support"
64 depends on MISC
65 help
66 Select this to enable a sysid for Altera devices. Please find
67 details on the "Embedded Peripherals IP User Guide" of Altera.
68
Marek Behúnaa5eb9a2017-06-09 19:28:44 +020069config ATSHA204A
70 bool "Support for Atmel ATSHA204A module"
Pali Rohár467f0c42022-04-12 11:20:44 +020071 select BITREVERSE
Marek Behúnaa5eb9a2017-06-09 19:28:44 +020072 depends on MISC
73 help
74 Enable support for I2C connected Atmel's ATSHA204A
75 CryptoAuthentication module found for example on the Turris Omnia
76 board.
77
Tim Harvey8479b9e2022-03-07 16:24:04 -080078config GATEWORKS_SC
79 bool "Gateworks System Controller Support"
80 depends on MISC
81 help
82 Enable access for the Gateworks System Controller used on Gateworks
83 boards to provide a boot watchdog, power control, temperature monitor,
84 voltage ADCs, and EEPROM.
85
Philipp Tomsich49cd8e82017-05-05 19:21:38 +020086config ROCKCHIP_EFUSE
87 bool "Rockchip e-fuse support"
88 depends on MISC
89 help
90 Enable (read-only) access for the e-fuse block found in Rockchip
91 SoCs: accesses can either be made using byte addressing and a length
92 or through child-nodes that are generated based on the e-fuse map
93 retrieved from the DTS.
94
95 This driver currently supports the RK3399 only, but can easily be
96 extended (by porting the read function from the Linux kernel sources)
97 to support other recent Rockchip devices.
98
Finley Xiaoa907dc32019-09-25 17:57:49 +020099config ROCKCHIP_OTP
100 bool "Rockchip OTP Support"
101 depends on MISC
102 help
103 Enable (read-only) access for the one-time-programmable memory block
104 found in Rockchip SoCs: accesses can either be made using byte
105 addressing and a length or through child-nodes that are generated
106 based on the e-fuse map retrieved from the DTS.
107
Pragnesh Patel05307212020-05-29 11:33:21 +0530108config SIFIVE_OTP
109 bool "SiFive eMemory OTP driver"
110 depends on MISC
111 help
112 Enable support for reading and writing the eMemory OTP on the
113 SiFive SoCs.
114
Tom Rinid9136522022-11-19 18:45:33 -0500115config SMSC_LPC47M
116 bool "LPC47M SMSC driver"
117
118config SMSC_SIO1007
119 bool "SIO1007 SMSC driver"
120
Liviu Dudau0fabfeb2018-09-28 13:43:31 +0100121config VEXPRESS_CONFIG
122 bool "Enable support for Arm Versatile Express config bus"
123 depends on MISC
124 help
125 If you say Y here, you will get support for accessing the
126 configuration bus on the Arm Versatile Express boards via
127 a sysreg driver.
128
Simon Glass6fb9ac12015-02-13 12:20:47 -0700129config CMD_CROS_EC
130 bool "Enable crosec command"
131 depends on CROS_EC
132 help
133 Enable command-line access to the Chrome OS EC (Embedded
134 Controller). This provides the 'crosec' command which has
135 a number of sub-commands for performing EC tasks such as
136 updating its flash, accessing a small saved context area
137 and talking to the I2C bus behind the EC (if there is one).
138
139config CROS_EC
140 bool "Enable Chrome OS EC"
141 help
142 Enable access to the Chrome OS EC. This is a separate
143 microcontroller typically available on a SPI bus on Chromebooks. It
144 provides access to the keyboard, some internal storage and may
145 control access to the battery and main PMIC depending on the
146 device. You can use the 'crosec' command to access it.
147
Simon Glassaaba7032018-11-18 08:14:27 -0700148config SPL_CROS_EC
149 bool "Enable Chrome OS EC in SPL"
Tom Rini8a1ab5e2022-05-10 12:51:47 -0400150 depends on SPL_MISC
Simon Glassaaba7032018-11-18 08:14:27 -0700151 help
152 Enable access to the Chrome OS EC in SPL. This is a separate
153 microcontroller typically available on a SPI bus on Chromebooks. It
154 provides access to the keyboard, some internal storage and may
155 control access to the battery and main PMIC depending on the
156 device. You can use the 'crosec' command to access it.
157
158config TPL_CROS_EC
159 bool "Enable Chrome OS EC in TPL"
Tom Rini8a1ab5e2022-05-10 12:51:47 -0400160 depends on TPL_MISC
Simon Glassaaba7032018-11-18 08:14:27 -0700161 help
162 Enable access to the Chrome OS EC in TPL. This is a separate
163 microcontroller typically available on a SPI bus on Chromebooks. It
164 provides access to the keyboard, some internal storage and may
165 control access to the battery and main PMIC depending on the
166 device. You can use the 'crosec' command to access it.
167
Simon Glass747093d2022-04-30 00:56:53 -0600168config VPL_CROS_EC
169 bool "Enable Chrome OS EC in VPL"
Tom Rini8a1ab5e2022-05-10 12:51:47 -0400170 depends on VPL_MISC
Simon Glass747093d2022-04-30 00:56:53 -0600171 help
172 Enable access to the Chrome OS EC in VPL. This is a separate
173 microcontroller typically available on a SPI bus on Chromebooks. It
174 provides access to the keyboard, some internal storage and may
175 control access to the battery and main PMIC depending on the
176 device. You can use the 'crosec' command to access it.
177
Simon Glass6fb9ac12015-02-13 12:20:47 -0700178config CROS_EC_I2C
179 bool "Enable Chrome OS EC I2C driver"
180 depends on CROS_EC
181 help
182 Enable I2C access to the Chrome OS EC. This is used on older
183 ARM Chromebooks such as snow and spring before the standard bus
184 changed to SPI. The EC will accept commands across the I2C using
185 a special message protocol, and provide responses.
186
187config CROS_EC_LPC
188 bool "Enable Chrome OS EC LPC driver"
189 depends on CROS_EC
190 help
191 Enable I2C access to the Chrome OS EC. This is used on x86
192 Chromebooks such as link and falco. The keyboard is provided
193 through a legacy port interface, so on x86 machines the main
194 function of the EC is power and thermal management.
195
Simon Glassaaba7032018-11-18 08:14:27 -0700196config SPL_CROS_EC_LPC
197 bool "Enable Chrome OS EC LPC driver in SPL"
Tom Rini8a1ab5e2022-05-10 12:51:47 -0400198 depends on CROS_EC && SPL_MISC
Simon Glassaaba7032018-11-18 08:14:27 -0700199 help
200 Enable I2C access to the Chrome OS EC. This is used on x86
201 Chromebooks such as link and falco. The keyboard is provided
202 through a legacy port interface, so on x86 machines the main
203 function of the EC is power and thermal management.
204
205config TPL_CROS_EC_LPC
206 bool "Enable Chrome OS EC LPC driver in TPL"
Tom Rini8a1ab5e2022-05-10 12:51:47 -0400207 depends on CROS_EC && TPL_MISC
Simon Glassaaba7032018-11-18 08:14:27 -0700208 help
209 Enable I2C access to the Chrome OS EC. This is used on x86
210 Chromebooks such as link and falco. The keyboard is provided
211 through a legacy port interface, so on x86 machines the main
212 function of the EC is power and thermal management.
213
Simon Glass747093d2022-04-30 00:56:53 -0600214config VPL_CROS_EC_LPC
215 bool "Enable Chrome OS EC LPC driver in VPL"
Tom Rini8a1ab5e2022-05-10 12:51:47 -0400216 depends on CROS_EC && VPL_MISC
Simon Glass747093d2022-04-30 00:56:53 -0600217 help
218 Enable I2C access to the Chrome OS EC. This is used on x86
219 Chromebooks such as link and falco. The keyboard is provided
220 through a legacy port interface, so on x86 machines the main
221 function of the EC is power and thermal management.
222
Simon Glass47cb8c62015-03-26 09:29:40 -0600223config CROS_EC_SANDBOX
224 bool "Enable Chrome OS EC sandbox driver"
225 depends on CROS_EC && SANDBOX
226 help
227 Enable a sandbox emulation of the Chrome OS EC. This supports
228 keyboard (use the -l flag to enable the LCD), verified boot context,
229 EC flash read/write/erase support and a few other things. It is
230 enough to perform a Chrome OS verified boot on sandbox.
231
Simon Glassaaba7032018-11-18 08:14:27 -0700232config SPL_CROS_EC_SANDBOX
233 bool "Enable Chrome OS EC sandbox driver in SPL"
234 depends on SPL_CROS_EC && SANDBOX
235 help
236 Enable a sandbox emulation of the Chrome OS EC in SPL. This supports
237 keyboard (use the -l flag to enable the LCD), verified boot context,
238 EC flash read/write/erase support and a few other things. It is
239 enough to perform a Chrome OS verified boot on sandbox.
240
241config TPL_CROS_EC_SANDBOX
242 bool "Enable Chrome OS EC sandbox driver in TPL"
243 depends on TPL_CROS_EC && SANDBOX
244 help
245 Enable a sandbox emulation of the Chrome OS EC in TPL. This supports
246 keyboard (use the -l flag to enable the LCD), verified boot context,
247 EC flash read/write/erase support and a few other things. It is
248 enough to perform a Chrome OS verified boot on sandbox.
249
Simon Glass747093d2022-04-30 00:56:53 -0600250config VPL_CROS_EC_SANDBOX
251 bool "Enable Chrome OS EC sandbox driver in VPL"
252 depends on VPL_CROS_EC && SANDBOX
253 help
254 Enable a sandbox emulation of the Chrome OS EC in VPL. This supports
255 keyboard (use the -l flag to enable the LCD), verified boot context,
256 EC flash read/write/erase support and a few other things. It is
257 enough to perform a Chrome OS verified boot on sandbox.
258
Simon Glass6fb9ac12015-02-13 12:20:47 -0700259config CROS_EC_SPI
260 bool "Enable Chrome OS EC SPI driver"
261 depends on CROS_EC
262 help
263 Enable SPI access to the Chrome OS EC. This is used on newer
264 ARM Chromebooks such as pit, pi and nyan-big. The SPI interface
265 provides a faster and more robust interface than I2C but the bugs
266 are less interesting.
267
Simon Glass879704d2017-05-17 03:25:02 -0600268config DS4510
269 bool "Enable support for DS4510 CPU supervisor"
270 help
271 Enable support for the Maxim DS4510 CPU supervisor. It has an
272 integrated 64-byte EEPROM, four programmable non-volatile I/O pins
273 and a configurable timer for the supervisor function. The device is
274 connected over I2C.
275
Tom Rini060613f2022-11-19 18:45:11 -0500276config FSL_IIM
277 bool "Enable FSL IC Identification Module (IIM) driver"
278 depends on ARCH_MX31 || ARCH_MX5
279
Peng Fanc12e0d92015-08-26 15:41:33 +0800280config FSL_SEC_MON
gaurav ranafe783782015-02-27 09:44:22 +0530281 bool "Enable FSL SEC_MON Driver"
282 help
283 Freescale Security Monitor block is responsible for monitoring
284 system states.
285 Security Monitor can be transitioned on any security failures,
286 like software violations or hardware security violations.
Stefan Roese1cdd9412015-03-12 11:22:46 +0100287
Tom Rinic9f85182022-06-16 14:04:39 -0400288choice
289 prompt "Security monitor interaction endianess"
290 depends on FSL_SEC_MON
291 default SYS_FSL_SEC_MON_BE if PPC
292 default SYS_FSL_SEC_MON_LE
293
294config SYS_FSL_SEC_MON_LE
295 bool "Security monitor interactions are little endian"
296
297config SYS_FSL_SEC_MON_BE
298 bool "Security monitor interactions are big endian"
299
300endchoice
301
Simon Glass79d66a62019-12-06 21:41:58 -0700302config IRQ
Wasim Khan182c5f12021-03-08 16:48:13 +0100303 bool "Interrupt controller"
Simon Glass79d66a62019-12-06 21:41:58 -0700304 help
Wasim Khan182c5f12021-03-08 16:48:13 +0100305 This enables support for interrupt controllers, including ITSS.
Simon Glass79d66a62019-12-06 21:41:58 -0700306 Some devices have extra features, such as Apollo Lake. The
307 device has its own uclass since there are several operations
308 involved.
309
Paul Burtonb5392c52018-12-16 19:25:19 -0300310config JZ4780_EFUSE
311 bool "Ingenic JZ4780 eFUSE support"
312 depends on ARCH_JZ47XX
313 help
314 This selects support for the eFUSE on Ingenic JZ4780 SoCs.
315
Sean Anderson2645bc02022-04-22 14:34:18 -0400316config LS2_SFP
317 bool "Layerscape Security Fuse Processor"
318 depends on FSL_LSCH2 || ARCH_LS1021A
319 depends on MISC
320 imply DM_REGULATOR
321 help
322 This adds support for the Security Fuse Processor found on Layerscape
323 SoCs. It contains various fuses related to secure boot, including the
324 Super Root Key hash, One-Time-Programmable Master Key, Debug
325 Challenge/Response values, and others. Fuses are numbered according
326 to their four-byte offset from the start of the bank.
327
328 If you don't need to read/program fuses, say 'n'.
329
Peng Fan3e020f02015-08-27 14:49:05 +0800330config MXC_OCOTP
331 bool "Enable MXC OCOTP Driver"
Peng Fan994ab732019-07-22 01:24:55 +0000332 depends on ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610
Marcel Ziswiler0a6f6252019-03-25 17:24:57 +0100333 default y
Peng Fan3e020f02015-08-27 14:49:05 +0800334 help
335 If you say Y here, you will get support for the One Time
336 Programmable memory pages that are stored on the some
337 Freescale i.MX processors.
338
Tom Rini6c03a652022-11-19 18:45:28 -0500339config MXS_OCOTP
340 bool "Enable MXS OCOTP Driver"
341 depends on ARCH_MX23 || ARCH_MX28
342 help
343 If you say Y here, you will get support for the One Time
344 Programmable memory pages that are stored on the
345 Freescale i.MXS family of processors.
346
Jim Liu847505a2022-06-24 16:24:37 +0800347config NPCM_HOST
348 bool "Enable support espi or LPC for Host"
349 depends on REGMAP && SYSCON
350 help
351 Enable NPCM BMC espi or LPC support for Host reading and writing.
352
Michael Scott33e9a692021-09-25 19:49:28 +0300353config SPL_MXC_OCOTP
354 bool "Enable MXC OCOTP driver in SPL"
Tom Rini8a1ab5e2022-05-10 12:51:47 -0400355 depends on SPL_MISC && (ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610)
Michael Scott33e9a692021-09-25 19:49:28 +0300356 default y
357 help
358 If you say Y here, you will get support for the One Time
359 Programmable memory pages, that are stored on some
360 Freescale i.MX processors, in SPL.
361
Jim Liu0ae1c772022-06-07 16:33:54 +0800362config NPCM_OTP
363 bool "Nnvoton NPCM BMC On-Chip OTP Memory Support"
364 depends on (ARM && ARCH_NPCM)
365 default n
366 help
367 Support NPCM BMC OTP memory (fuse).
368 To compile this driver as a module, choose M here: the module
369 will be called npcm_otp.
370
Ye Li03fcf962022-07-26 16:40:49 +0800371config IMX_SENTINEL
372 bool "Enable i.MX Sentinel MU driver and API"
373 depends on MISC && (ARCH_IMX9 || ARCH_IMX8ULP)
374 help
375 If you say Y here to enable Message Unit driver to work with
376 Sentinel core on some NXP i.MX processors.
377
Stefan Roese4cf9e462016-07-19 07:45:46 +0200378config NUVOTON_NCT6102D
379 bool "Enable Nuvoton NCT6102D Super I/O driver"
380 help
381 If you say Y here, you will get support for the Nuvoton
382 NCT6102D Super I/O driver. This can be used to enable or
383 disable the legacy UART, the watchdog or other devices
384 in the Nuvoton Super IO chips on X86 platforms.
385
Simon Glass5bee27a2019-12-06 21:41:55 -0700386config P2SB
Wolfgang Wallnerd872e7d2020-07-01 13:37:23 +0200387 bool "Intel Primary to Sideband Bridge"
Simon Glass5bee27a2019-12-06 21:41:55 -0700388 depends on X86 || SANDBOX
389 help
Wolfgang Wallnerd872e7d2020-07-01 13:37:23 +0200390 This enables support for the Intel Primary to Sideband Bridge,
Simon Glass5bee27a2019-12-06 21:41:55 -0700391 abbreviated to P2SB. The P2SB is used to access various peripherals
392 such as eSPI, GPIO, through memory-mapped I/O in a large chunk of PCI
393 space. The space is segmented into different channels and peripherals
394 are accessed by device-specific means within those channels. Devices
395 should be added in the device tree as subnodes of the P2SB. A
396 Peripheral Channel Register? (PCR) API is provided to access those
397 devices - see pcr_readl(), etc.
398
399config SPL_P2SB
Wolfgang Wallnerd872e7d2020-07-01 13:37:23 +0200400 bool "Intel Primary to Sideband Bridge in SPL"
Tom Rini8a1ab5e2022-05-10 12:51:47 -0400401 depends on SPL_MISC && (X86 || SANDBOX)
Simon Glass5bee27a2019-12-06 21:41:55 -0700402 help
Wolfgang Wallnerd872e7d2020-07-01 13:37:23 +0200403 The Primary to Sideband Bridge is used to access various peripherals
Simon Glass5bee27a2019-12-06 21:41:55 -0700404 through memory-mapped I/O in a large chunk of PCI space. The space is
405 segmented into different channels and peripherals are accessed by
406 device-specific means within those channels. Devices should be added
407 in the device tree as subnodes of the p2sb.
408
409config TPL_P2SB
Wolfgang Wallnerd872e7d2020-07-01 13:37:23 +0200410 bool "Intel Primary to Sideband Bridge in TPL"
Tom Rini8a1ab5e2022-05-10 12:51:47 -0400411 depends on TPL_MISC && (X86 || SANDBOX)
Simon Glass5bee27a2019-12-06 21:41:55 -0700412 help
Wolfgang Wallnerd872e7d2020-07-01 13:37:23 +0200413 The Primary to Sideband Bridge is used to access various peripherals
Simon Glass5bee27a2019-12-06 21:41:55 -0700414 through memory-mapped I/O in a large chunk of PCI space. The space is
415 segmented into different channels and peripherals are accessed by
416 device-specific means within those channels. Devices should be added
417 in the device tree as subnodes of the p2sb.
418
Simon Glass5fd6bad2016-01-21 19:43:31 -0700419config PWRSEQ
420 bool "Enable power-sequencing drivers"
421 depends on DM
422 help
423 Power-sequencing drivers provide support for controlling power for
424 devices. They are typically referenced by a phandle from another
425 device. When the device is started up, its power sequence can be
426 initiated.
427
428config SPL_PWRSEQ
429 bool "Enable power-sequencing drivers for SPL"
Tom Rini8a1ab5e2022-05-10 12:51:47 -0400430 depends on SPL_MISC && PWRSEQ
Simon Glass5fd6bad2016-01-21 19:43:31 -0700431 help
432 Power-sequencing drivers provide support for controlling power for
433 devices. They are typically referenced by a phandle from another
434 device. When the device is started up, its power sequence can be
435 initiated.
436
Stefan Roese1cdd9412015-03-12 11:22:46 +0100437config PCA9551_LED
438 bool "Enable PCA9551 LED driver"
439 help
440 Enable driver for PCA9551 LED controller. This controller
441 is connected via I2C. So I2C needs to be enabled.
442
443config PCA9551_I2C_ADDR
444 hex "I2C address of PCA9551 LED controller"
445 depends on PCA9551_LED
446 default 0x60
447 help
448 The I2C address of the PCA9551 LED controller.
Simon Glassf9917452015-06-23 15:39:13 -0600449
Patrick Delaunayc3600e12018-05-17 15:24:06 +0200450config STM32MP_FUSE
451 bool "Enable STM32MP fuse wrapper providing the fuse API"
452 depends on ARCH_STM32MP && MISC
453 default y if CMD_FUSE
454 help
455 If you say Y here, you will get support for the fuse API (OTP)
456 for STM32MP architecture.
457 This API is needed for CMD_FUSE.
458
Christophe Kerello4e280b92017-09-13 18:00:08 +0200459config STM32_RCC
460 bool "Enable RCC driver for the STM32 SoC's family"
Trevor Woerner71f63542020-05-06 08:02:42 -0400461 depends on (ARCH_STM32 || ARCH_STM32MP) && MISC
Christophe Kerello4e280b92017-09-13 18:00:08 +0200462 help
463 Enable the STM32 RCC driver. The RCC block (Reset and Clock Control
464 block) is responsible of the management of the clock and reset
465 generation.
466 This driver is similar to an MFD driver in the Linux kernel.
467
Stephen Warrenbd3ee842016-09-13 10:45:57 -0600468config TEGRA_CAR
469 bool "Enable support for the Tegra CAR driver"
470 depends on TEGRA_NO_BPMP
471 help
472 The Tegra CAR (Clock and Reset Controller) is a HW module that
473 controls almost all clocks and resets in a Tegra SoC.
474
Stephen Warren73dd5c42016-08-08 09:41:34 -0600475config TEGRA186_BPMP
476 bool "Enable support for the Tegra186 BPMP driver"
477 depends on TEGRA186
478 help
479 The Tegra BPMP (Boot and Power Management Processor) is a separate
480 auxiliary CPU embedded into Tegra to perform power management work,
481 and controls related features such as clocks, resets, power domains,
482 PMIC I2C bus, etc. This driver provides the core low-level
483 communication path by which feature-specific drivers (such as clock)
484 can make requests to the BPMP. This driver is similar to an MFD
485 driver in the Linux kernel.
486
Simon Glass079ac592020-12-23 08:11:18 -0700487config TEST_DRV
488 bool "Enable support for test drivers"
489 default y if SANDBOX
490 help
491 This enables drivers and uclasses that provides a way of testing the
492 operations of memory allocation and driver/uclass methods in driver
493 model. This should only be enabled for testing as it is not useful for
494 anything else.
495
Marek Vasut02544db2022-04-10 06:27:14 +0200496config USB_HUB_USB251XB
497 tristate "USB251XB Hub Controller Configuration Driver"
498 depends on I2C
499 help
500 This option enables support for configuration via SMBus of the
501 Microchip USB251x/xBi USB 2.0 Hub Controller series. Configuration
502 parameters may be set in devicetree or platform data.
503 Say Y or M here if you need to configure such a device via SMBus.
504
Adam Fordcc3fedb2018-08-06 14:26:50 -0500505config TWL4030_LED
506 bool "Enable TWL4030 LED controller"
507 help
508 Enable this to add support for the TWL4030 LED controller.
509
Stefan Roese85056932016-01-19 14:05:10 +0100510config WINBOND_W83627
511 bool "Enable Winbond Super I/O driver"
512 help
513 If you say Y here, you will get support for the Winbond
514 W83627 Super I/O driver. This can be used to enable the
515 legacy UART or other devices in the Winbond Super IO chips
516 on X86 platforms.
517
Miao Yanfcf5c042016-05-22 19:37:14 -0700518config QFW
519 bool
520 help
Asherah Connor5b0b43e2021-03-19 18:21:40 +1100521 Hidden option to enable QEMU fw_cfg interface and uclass. This will
522 be selected by either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE.
523
524config QFW_PIO
525 bool
526 depends on QFW
527 help
528 Hidden option to enable PIO QEMU fw_cfg interface. This will be
529 selected by the appropriate QEMU board.
Miao Yanfcf5c042016-05-22 19:37:14 -0700530
Asherah Connor5830b572021-03-19 18:21:42 +1100531config QFW_MMIO
532 bool
533 depends on QFW
534 help
535 Hidden option to enable MMIO QEMU fw_cfg interface. This will be
536 selected by the appropriate QEMU board.
537
mario.six@gdsys.ccd7e28912016-06-22 15:14:16 +0200538config I2C_EEPROM
539 bool "Enable driver for generic I2C-attached EEPROMs"
540 depends on MISC
541 help
542 Enable a generic driver for EEPROMs attached via I2C.
Adam Forde3f24d42017-08-13 09:00:28 -0500543
Wenyou Yangd81a1de2017-09-06 13:08:14 +0800544
545config SPL_I2C_EEPROM
546 bool "Enable driver for generic I2C-attached EEPROMs for SPL"
Tom Rini8a1ab5e2022-05-10 12:51:47 -0400547 depends on SPL_MISC
Wenyou Yangd81a1de2017-09-06 13:08:14 +0800548 help
549 This option is an SPL-variant of the I2C_EEPROM option.
550 See the help of I2C_EEPROM for details.
551
Adam Forde3f24d42017-08-13 09:00:28 -0500552config SYS_I2C_EEPROM_ADDR
553 hex "Chip address of the EEPROM device"
Tom Rini88cd7d02021-08-17 17:59:45 -0400554 depends on ID_EEPROM || I2C_EEPROM || SPL_I2C_EEPROM || CMD_EEPROM || ENV_IS_IN_EEPROM
Adam Forde3f24d42017-08-13 09:00:28 -0500555 default 0
556
Tom Rini88cd7d02021-08-17 17:59:45 -0400557if I2C_EEPROM
Adam Forde3f24d42017-08-13 09:00:28 -0500558
559config SYS_I2C_EEPROM_ADDR_OVERFLOW
560 hex "EEPROM Address Overflow"
Tom Rini5fd4a7e2021-12-11 14:55:47 -0500561 default 0x0
Adam Forde3f24d42017-08-13 09:00:28 -0500562 help
563 EEPROM chips that implement "address overflow" are ones
564 like Catalyst 24WC04/08/16 which has 9/10/11 bits of
565 address and the extra bits end up in the "chip address" bit
566 slots. This makes a 24WC08 (1Kbyte) chip look like four 256
567 byte chips.
568
569endif
570
Mario Six86da8c12018-04-27 14:53:33 +0200571config GDSYS_RXAUI_CTRL
572 bool "Enable gdsys RXAUI control driver"
573 depends on MISC
574 help
575 Support gdsys FPGA's RXAUI control.
Mario Six7e862422018-07-31 14:24:15 +0200576
577config GDSYS_IOEP
578 bool "Enable gdsys IOEP driver"
579 depends on MISC
580 help
581 Support gdsys FPGA's IO endpoint driver.
Mario Sixd2166312018-08-06 10:23:46 +0200582
583config MPC83XX_SERDES
584 bool "Enable MPC83xx serdes driver"
585 depends on MISC
586 help
587 Support for serdes found on MPC83xx SoCs.
588
Tien Fong Chee62030002018-07-06 16:28:03 +0800589config FS_LOADER
590 bool "Enable loader driver for file system"
591 help
592 This is file system generic loader which can be used to load
593 the file image from the storage into target such as memory.
594
595 The consumer driver would then use this loader to program whatever,
596 ie. the FPGA device.
597
Keerthyb071a072022-01-27 13:16:53 +0100598config SPL_FS_LOADER
599 bool "Enable loader driver for file system"
Tom Rini8a1ab5e2022-05-10 12:51:47 -0400600 depends on SPL
Keerthyb071a072022-01-27 13:16:53 +0100601 help
602 This is file system generic loader which can be used to load
603 the file image from the storage into target such as memory.
604
605 The consumer driver would then use this loader to program whatever,
606 ie. the FPGA device.
607
Mario Sixc0a2b082018-10-04 09:00:54 +0200608config GDSYS_SOC
609 bool "Enable gdsys SOC driver"
610 depends on MISC
611 help
612 Support for gdsys IHS SOC, a simple bus associated with each gdsys
613 IHS (Integrated Hardware Systems) FPGA, which holds all devices whose
614 register maps are contained within the FPGA's register map.
615
Mario Sixab88bd22018-10-04 09:00:55 +0200616config IHS_FPGA
617 bool "Enable IHS FPGA driver"
618 depends on MISC
619 help
620 Support IHS (Integrated Hardware Systems) FPGA, the main FPGAs on
621 gdsys devices, which supply the majority of the functionality offered
622 by the devices. This driver supports both CON and CPU variants of the
623 devices, depending on the device tree entry.
Tero Kristo344eb6d2020-02-14 11:18:15 +0200624config ESM_K3
625 bool "Enable K3 ESM driver"
626 depends on ARCH_K3
627 help
628 Support ESM (Error Signaling Module) on TI K3 SoCs.
Mario Sixab88bd22018-10-04 09:00:55 +0200629
Eugen Hristevf8164952019-10-09 09:23:39 +0000630config MICROCHIP_FLEXCOM
631 bool "Enable Microchip Flexcom driver"
632 depends on MISC
633 help
634 The Atmel Flexcom is just a wrapper which embeds a SPI controller,
635 an I2C controller and an USART.
636 Only one function can be used at a time and is chosen at boot time
637 according to the device tree.
638
Tero Kristo9d233b42019-10-24 15:00:46 +0530639config K3_AVS0
640 depends on ARCH_K3 && SPL_DM_REGULATOR
641 bool "AVS class 0 support for K3 devices"
642 help
643 K3 devices have the optimized voltage values for the main voltage
644 domains stored in efuse within the VTM IP. This driver reads the
645 optimized voltage from the efuse, so that it can be programmed
646 to the PMIC on board.
647
Tero Kristo3b36b382020-02-14 11:18:16 +0200648config ESM_PMIC
649 bool "Enable PMIC ESM driver"
650 depends on DM_PMIC
651 help
652 Support ESM (Error Signal Monitor) on PMIC devices. ESM is used
653 typically to reboot the board in error condition.
654
Tom Rini98ab8312021-12-11 14:55:49 -0500655config FSL_IFC
656 bool
657
Michael Walle42595eb2022-02-25 18:06:24 +0530658config SL28CPLD
659 bool "Enable Kontron sl28cpld multi-function driver"
660 depends on DM_I2C
661 help
662 Support for the Kontron sl28cpld management controller. This is
663 the base driver which provides common access methods for the
664 sub-drivers.
665
Masahiro Yamada0b11dbf2015-07-26 02:46:26 +0900666endmenu