blob: daf18e015709829d486a4e45354920d082e8366c [file] [log] [blame]
Louis Su30f57472008-07-09 11:01:37 +08001/* ax88180.h: ASIX AX88180 Non-PCI Gigabit Ethernet u-boot driver */
2/*
3 *
4 * This program is free software; you can distribute it and/or modify it
5 * under the terms of the GNU General Public License (Version 2) as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
11 * for more details.
12 *
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
16 *
17 */
18
19#ifndef _AX88180_H_
20#define _AX88180_H_
21
Mike Frysingercafb14f2010-06-02 21:03:50 -040022#include <asm/io.h>
Louis Su30f57472008-07-09 11:01:37 +080023#include <asm/types.h>
24#include <config.h>
25
26typedef enum _ax88180_link_state {
27 INS_LINK_DOWN,
28 INS_LINK_UP,
29 INS_LINK_UNKNOWN
30} ax88180_link_state;
31
32struct ax88180_private {
33 unsigned char BusWidth;
34 unsigned char PadSize;
35 unsigned short PhyAddr;
36 unsigned short PhyID0;
Hoan Hoang25667062010-05-11 02:42:38 -040037 unsigned short PhyID1;
Louis Su30f57472008-07-09 11:01:37 +080038 unsigned short FirstTxDesc;
39 unsigned short NextTxDesc;
40 ax88180_link_state LinkState;
41};
42
43#define BUS_WIDTH_16 1
44#define BUS_WIDTH_32 2
45
46#define ENABLE_JUMBO 1
47#define DISABLE_JUMBO 0
48
49#define ENABLE_BURST 1
50#define DISABLE_BURST 0
51
52#define NORMAL_RX_MODE 0
53#define RX_LOOPBACK_MODE 1
54#define RX_INIFINIT_LOOP_MODE 2
55#define TX_INIFINIT_LOOP_MODE 3
56
57#define DEFAULT_ETH_MTU 1500
58
59/* Jumbo packet size 4086 bytes included 4 bytes CRC*/
60#define MAX_JUMBO_MTU 4072
61
62/* Max Tx Jumbo size 4086 bytes included 4 bytes CRC */
63#define MAX_TX_JUMBO_SIZE 4086
64
65/* Max Rx Jumbo size is 15K Bytes */
66#define MAX_RX_SIZE 0x3C00
67
Hoan Hoang25667062010-05-11 02:42:38 -040068#define MARVELL_ALASKA_PHYSID0 0x141
69#define MARVELL_88E1118_PHYSID1 0xE40
Louis Su30f57472008-07-09 11:01:37 +080070
Mike Frysingerf9abdfe2010-05-10 16:47:36 -040071#define CICADA_CIS8201_PHYSID0 0x000F
Louis Su30f57472008-07-09 11:01:37 +080072
73#define MEDIA_AUTO 0
74#define MEDIA_1000FULL 1
75#define MEDIA_1000HALF 2
76#define MEDIA_100FULL 3
77#define MEDIA_100HALF 4
78#define MEDIA_10FULL 5
79#define MEDIA_10HALF 6
80#define MEDIA_UNKNOWN 7
81
82#define AUTO_MEDIA 0
83#define FORCE_MEDIA 1
84
85#define TXDP_MASK 3
86#define TXDP0 0
87#define TXDP1 1
88#define TXDP2 2
89#define TXDP3 3
90
91#define CMD_MAP_SIZE 0x100
92
93#if defined (CONFIG_DRIVER_AX88180_16BIT)
94 #define AX88180_MEMORY_SIZE 0x00004000
95 #define START_BASE 0x1000
96
97 #define RX_BUF_SIZE 0x1000
98 #define TX_BUF_SIZE 0x0F00
99
100 #define TX_BASE START_BASE
101 #define CMD_BASE (TX_BASE + TX_BUF_SIZE)
102 #define RX_BASE (CMD_BASE + CMD_MAP_SIZE)
103#else
104 #define AX88180_MEMORY_SIZE 0x00010000
105
106 #define RX_BUF_SIZE 0x8000
107 #define TX_BUF_SIZE 0x7C00
108
109 #define RX_BASE 0x0000
110 #define TX_BASE (RX_BASE + RX_BUF_SIZE)
111 #define CMD_BASE (TX_BASE + TX_BUF_SIZE)
112#endif
113
114/* AX88180 Memory Mapping Definition */
115#define RXBUFFER_START RX_BASE
116 #define RX_PACKET_LEN_OFFSET 0
117 #define RX_PAGE_NUM_MASK 0x7FF /* RX pages 0~7FFh */
118#define TXBUFFER_START TX_BASE
119
120/* AX88180 MAC Register Definition */
121#define DECODE (0)
122 #define DECODE_EN 0x00000001
123#define BASE (6)
124#define CMD (CMD_BASE + 0x0000)
125 #define WAKEMOD 0x00000001
126 #define TXEN 0x00000100
127 #define RXEN 0x00000200
128 #define DEFAULT_CMD WAKEMOD
129#define IMR (CMD_BASE + 0x0004)
130 #define IMR_RXBUFFOVR 0x00000001
131 #define IMR_WATCHDOG 0x00000002
132 #define IMR_TX 0x00000008
133 #define IMR_RX 0x00000010
134 #define IMR_PHY 0x00000020
135 #define CLEAR_IMR 0x00000000
136 #define DEFAULT_IMR (IMR_PHY | IMR_RX | IMR_TX |\
137 IMR_RXBUFFOVR | IMR_WATCHDOG)
138#define ISR (CMD_BASE + 0x0008)
139 #define ISR_RXBUFFOVR 0x00000001
140 #define ISR_WATCHDOG 0x00000002
141 #define ISR_TX 0x00000008
142 #define ISR_RX 0x00000010
143 #define ISR_PHY 0x00000020
144#define TXCFG (CMD_BASE + 0x0010)
145 #define AUTOPAD_CRC 0x00000050
146 #define DEFAULT_TXCFG AUTOPAD_CRC
147#define TXCMD (CMD_BASE + 0x0014)
148 #define TXCMD_TXDP_MASK 0x00006000
149 #define TXCMD_TXDP0 0x00000000
150 #define TXCMD_TXDP1 0x00002000
151 #define TXCMD_TXDP2 0x00004000
152 #define TXCMD_TXDP3 0x00006000
153 #define TX_START_WRITE 0x00008000
154 #define TX_STOP_WRITE 0x00000000
155 #define DEFAULT_TXCMD 0x00000000
156#define TXBS (CMD_BASE + 0x0018)
157 #define TXDP0_USED 0x00000001
158 #define TXDP1_USED 0x00000002
159 #define TXDP2_USED 0x00000004
160 #define TXDP3_USED 0x00000008
161 #define DEFAULT_TXBS 0x00000000
162#define TXDES0 (CMD_BASE + 0x0020)
163 #define TXDPx_ENABLE 0x00008000
164 #define TXDPx_LEN_MASK 0x00001FFF
165 #define DEFAULT_TXDES0 0x00000000
166#define TXDES1 (CMD_BASE + 0x0024)
167 #define TXDPx_ENABLE 0x00008000
168 #define TXDPx_LEN_MASK 0x00001FFF
169 #define DEFAULT_TXDES1 0x00000000
170#define TXDES2 (CMD_BASE + 0x0028)
171 #define TXDPx_ENABLE 0x00008000
172 #define TXDPx_LEN_MASK 0x00001FFF
173 #define DEFAULT_TXDES2 0x00000000
174#define TXDES3 (CMD_BASE + 0x002C)
175 #define TXDPx_ENABLE 0x00008000
176 #define TXDPx_LEN_MASK 0x00001FFF
177 #define DEFAULT_TXDES3 0x00000000
178#define RXCFG (CMD_BASE + 0x0030)
179 #define RXBUFF_PROTECT 0x00000001
180 #define RXTCPCRC_CHECK 0x00000010
181 #define RXFLOW_ENABLE 0x00000100
182 #define DEFAULT_RXCFG RXBUFF_PROTECT
183#define RXCURT (CMD_BASE + 0x0034)
184 #define DEFAULT_RXCURT 0x00000000
185#define RXBOUND (CMD_BASE + 0x0038)
Wolfgang Denkb4dbacf2008-10-15 15:50:45 +0200186 #define DEFAULT_RXBOUND 0x7FF /* RX pages 0~7FFh */
Louis Su30f57472008-07-09 11:01:37 +0800187#define MACCFG0 (CMD_BASE + 0x0040)
188 #define MACCFG0_BIT3_0 0x00000007
189 #define IPGT_VAL 0x00000150
190 #define TXFLOW_ENABLE 0x00001000
191 #define SPEED100 0x00008000
192 #define DEFAULT_MACCFG0 (IPGT_VAL | MACCFG0_BIT3_0)
193#define MACCFG1 (CMD_BASE + 0x0044)
194 #define RGMII_EN 0x00000002
195 #define RXFLOW_EN 0x00000020
196 #define FULLDUPLEX 0x00000040
197 #define MAX_JUMBO_LEN 0x00000780
198 #define RXJUMBO_EN 0x00000800
199 #define GIGA_MODE_EN 0x00001000
200 #define RXCRC_CHECK 0x00002000
201 #define RXPAUSE_DA_CHECK 0x00004000
202
203 #define JUMBO_LEN_4K 0x00000200
204 #define JUMBO_LEN_15K 0x00000780
205 #define DEFAULT_MACCFG1 (RXCRC_CHECK | RXPAUSE_DA_CHECK | \
206 RGMII_EN)
207 #define CICADA_DEFAULT_MACCFG1 (RXCRC_CHECK | RXPAUSE_DA_CHECK)
208#define MACCFG2 (CMD_BASE + 0x0048)
209 #define MACCFG2_BIT15_8 0x00000100
210 #define JAM_LIMIT_MASK 0x000000FC
211 #define DEFAULT_JAM_LIMIT 0x00000064
212 #define DEFAULT_MACCFG2 MACCFG2_BIT15_8
213#define MACCFG3 (CMD_BASE + 0x004C)
214 #define IPGR2_VAL 0x0000000E
215 #define IPGR1_VAL 0x00000600
216 #define NOABORT 0x00008000
217 #define DEFAULT_MACCFG3 (IPGR1_VAL | IPGR2_VAL)
218#define TXPAUT (CMD_BASE + 0x0054)
219 #define DEFAULT_TXPAUT 0x001FE000
220#define RXBTHD0 (CMD_BASE + 0x0058)
221 #define DEFAULT_RXBTHD0 0x00000300
222#define RXBTHD1 (CMD_BASE + 0x005C)
223 #define DEFAULT_RXBTHD1 0x00000600
224#define RXFULTHD (CMD_BASE + 0x0060)
225 #define DEFAULT_RXFULTHD 0x00000100
226#define MISC (CMD_BASE + 0x0068)
227 /* Normal operation mode */
228 #define MISC_NORMAL 0x00000003
229 /* Clear bit 0 to reset MAC */
230 #define MISC_RESET_MAC 0x00000002
231 /* Clear bit 1 to reset PHY */
232 #define MISC_RESET_PHY 0x00000001
233 /* Clear bit 0 and 1 to reset MAC and PHY */
234 #define MISC_RESET_MAC_PHY 0x00000000
235 #define DEFAULT_MISC MISC_NORMAL
236#define MACID0 (CMD_BASE + 0x0070)
237#define MACID1 (CMD_BASE + 0x0074)
238#define MACID2 (CMD_BASE + 0x0078)
239#define TXLEN (CMD_BASE + 0x007C)
240 #define DEFAULT_TXLEN 0x000005FC
241#define RXFILTER (CMD_BASE + 0x0080)
242 #define RX_RXANY 0x00000001
243 #define RX_MULTICAST 0x00000002
244 #define RX_UNICAST 0x00000004
245 #define RX_BROADCAST 0x00000008
246 #define RX_MULTI_HASH 0x00000010
247 #define DISABLE_RXFILTER 0x00000000
248 #define DEFAULT_RXFILTER (RX_BROADCAST + RX_UNICAST)
249#define MDIOCTRL (CMD_BASE + 0x0084)
250 #define PHY_ADDR_MASK 0x0000001F
251 #define REG_ADDR_MASK 0x00001F00
252 #define READ_PHY 0x00004000
253 #define WRITE_PHY 0x00008000
254#define MDIODP (CMD_BASE + 0x0088)
255#define GPIOCTRL (CMD_BASE + 0x008C)
256#define RXINDICATOR (CMD_BASE + 0x0090)
257 #define RX_START_READ 0x00000001
258 #define RX_STOP_READ 0x00000000
259 #define DEFAULT_RXINDICATOR RX_STOP_READ
260#define TXST (CMD_BASE + 0x0094)
261#define MDCCLKPAT (CMD_BASE + 0x00A0)
262#define RXIPCRCCNT (CMD_BASE + 0x00A4)
263#define RXCRCCNT (CMD_BASE + 0x00A8)
264#define TXFAILCNT (CMD_BASE + 0x00AC)
265#define PROMDP (CMD_BASE + 0x00B0)
266#define PROMCTRL (CMD_BASE + 0x00B4)
267 #define RELOAD_EEPROM 0x00000200
268#define MAXRXLEN (CMD_BASE + 0x00B8)
269#define HASHTAB0 (CMD_BASE + 0x00C0)
270#define HASHTAB1 (CMD_BASE + 0x00C4)
271#define HASHTAB2 (CMD_BASE + 0x00C8)
272#define HASHTAB3 (CMD_BASE + 0x00CC)
273#define DOGTHD0 (CMD_BASE + 0x00E0)
274 #define DEFAULT_DOGTHD0 0x0000FFFF
275#define DOGTHD1 (CMD_BASE + 0x00E4)
276 #define START_WATCHDOG_TIMER 0x00008000
277 #define DEFAULT_DOGTHD1 0x00000FFF
278#define SOFTRST (CMD_BASE + 0x00EC)
279 #define SOFTRST_NORMAL 0x00000003
280 #define SOFTRST_RESET_MAC 0x00000002
281
Louis Su30f57472008-07-09 11:01:37 +0800282/* Marvell 88E1111 Gigabit PHY Register Definition */
283#define M88_SSR 0x0011
284 #define SSR_SPEED_MASK 0xC000
285 #define SSR_SPEED_1000 0x8000
286 #define SSR_SPEED_100 0x4000
287 #define SSR_SPEED_10 0x0000
288 #define SSR_DUPLEX 0x2000
289 #define SSR_MEDIA_RESOLVED_OK 0x0800
290
291 #define SSR_MEDIA_MASK (SSR_SPEED_MASK | SSR_DUPLEX)
292 #define SSR_1000FULL (SSR_SPEED_1000 | SSR_DUPLEX)
293 #define SSR_1000HALF SSR_SPEED_1000
294 #define SSR_100FULL (SSR_SPEED_100 | SSR_DUPLEX)
295 #define SSR_100HALF SSR_SPEED_100
296 #define SSR_10FULL (SSR_SPEED_10 | SSR_DUPLEX)
297 #define SSR_10HALF SSR_SPEED_10
298#define M88_IER 0x0012
299 #define LINK_CHANGE_INT 0x0400
300#define M88_ISR 0x0013
301 #define LINK_CHANGE_STATUS 0x0400
Hoan Hoang25667062010-05-11 02:42:38 -0400302#define M88E1111_EXT_SCR 0x0014
Louis Su30f57472008-07-09 11:01:37 +0800303 #define RGMII_RXCLK_DELAY 0x0080
304 #define RGMII_TXCLK_DELAY 0x0002
305 #define DEFAULT_EXT_SCR (RGMII_TXCLK_DELAY | RGMII_RXCLK_DELAY)
Hoan Hoang25667062010-05-11 02:42:38 -0400306#define M88E1111_EXT_SSR 0x001B
Louis Su30f57472008-07-09 11:01:37 +0800307 #define HWCFG_MODE_MASK 0x000F
308 #define RGMII_COPPER_MODE 0x000B
309
Hoan Hoang25667062010-05-11 02:42:38 -0400310/* Marvell 88E1118 Gigabit PHY Register Definition */
311#define M88E1118_CR 0x14
312 #define M88E1118_CR_RGMII_RXCLK_DELAY 0x0020
313 #define M88E1118_CR_RGMII_TXCLK_DELAY 0x0010
314 #define M88E1118_CR_DEFAULT (M88E1118_CR_RGMII_TXCLK_DELAY | \
315 M88E1118_CR_RGMII_RXCLK_DELAY)
316#define M88E1118_LEDCTL 0x10 /* Reg 16 on page 3 */
317 #define M88E1118_LEDCTL_LED2INT 0x200
318 #define M88E1118_LEDCTL_LED2BLNK 0x400
319 #define M88E1118_LEDCTL_LED0DUALMODE1 0xc
320 #define M88E1118_LEDCTL_LED0DUALMODE2 0xd
321 #define M88E1118_LEDCTL_LED0DUALMODE3 0xe
322 #define M88E1118_LEDCTL_LED0DUALMODE4 0xf
323 #define M88E1118_LEDCTL_DEFAULT (M88E1118_LEDCTL_LED2BLNK | \
324 M88E1118_LEDCTL_LED0DUALMODE4)
325
326#define M88E1118_LEDMIX 0x11 /* Reg 17 on page 3 */
327 #define M88E1118_LEDMIX_LED050 0x4
328 #define M88E1118_LEDMIX_LED150 0x8
329
330#define M88E1118_PAGE_SEL 0x16 /* Reg page select */
331
Louis Su30f57472008-07-09 11:01:37 +0800332/* CICADA CIS8201 Gigabit PHY Register Definition */
333#define CIS_IMR 0x0019
334 #define CIS_INT_ENABLE 0x8000
335 #define CIS_LINK_CHANGE_INT 0x2000
336#define CIS_ISR 0x001A
337 #define CIS_INT_PENDING 0x8000
338 #define CIS_LINK_CHANGE_STATUS 0x2000
339#define CIS_AUX_CTRL_STATUS 0x001C
340 #define CIS_AUTONEG_COMPLETE 0x8000
341 #define CIS_SPEED_MASK 0x0018
342 #define CIS_SPEED_1000 0x0010
343 #define CIS_SPEED_100 0x0008
344 #define CIS_SPEED_10 0x0000
345 #define CIS_DUPLEX 0x0020
346
347 #define CIS_MEDIA_MASK (CIS_SPEED_MASK | CIS_DUPLEX)
348 #define CIS_1000FULL (CIS_SPEED_1000 | CIS_DUPLEX)
349 #define CIS_1000HALF CIS_SPEED_1000
350 #define CIS_100FULL (CIS_SPEED_100 | CIS_DUPLEX)
351 #define CIS_100HALF CIS_SPEED_100
352 #define CIS_10FULL (CIS_SPEED_10 | CIS_DUPLEX)
353 #define CIS_10HALF CIS_SPEED_10
354 #define CIS_SMI_PRIORITY 0x0004
355
356static inline unsigned short INW (struct eth_device *dev, unsigned long addr)
357{
Mike Frysingercafb14f2010-06-02 21:03:50 -0400358 return le16_to_cpu(readw(addr + (void *)dev->iobase));
Louis Su30f57472008-07-09 11:01:37 +0800359}
360
Hoan Hoang14f637f2010-05-11 02:43:07 -0400361/*
362 Access RXBUFFER_START/TXBUFFER_START to read RX buffer/write TX buffer
363*/
364#if defined (CONFIG_DRIVER_AX88180_16BIT)
Louis Su30f57472008-07-09 11:01:37 +0800365static inline void OUTW (struct eth_device *dev, unsigned short command, unsigned long addr)
366{
Mike Frysingercafb14f2010-06-02 21:03:50 -0400367 writew(cpu_to_le16(command), addr + (void *)dev->iobase);
Louis Su30f57472008-07-09 11:01:37 +0800368}
369
Louis Su30f57472008-07-09 11:01:37 +0800370static inline unsigned short READ_RXBUF (struct eth_device *dev)
371{
Mike Frysingercafb14f2010-06-02 21:03:50 -0400372 return le16_to_cpu(readw(RXBUFFER_START + (void *)dev->iobase));
Louis Su30f57472008-07-09 11:01:37 +0800373}
374
375static inline void WRITE_TXBUF (struct eth_device *dev, unsigned short data)
376{
Mike Frysingercafb14f2010-06-02 21:03:50 -0400377 writew(cpu_to_le16(data), TXBUFFER_START + (void *)dev->iobase);
Louis Su30f57472008-07-09 11:01:37 +0800378}
379#else
Hoan Hoang14f637f2010-05-11 02:43:07 -0400380static inline void OUTW (struct eth_device *dev, unsigned short command, unsigned long addr)
381{
Mike Frysingercafb14f2010-06-02 21:03:50 -0400382 writel(cpu_to_le32(command), addr + (void *)dev->iobase);
Hoan Hoang14f637f2010-05-11 02:43:07 -0400383}
384
Louis Su30f57472008-07-09 11:01:37 +0800385static inline unsigned long READ_RXBUF (struct eth_device *dev)
386{
Mike Frysingercafb14f2010-06-02 21:03:50 -0400387 return le32_to_cpu(readl(RXBUFFER_START + (void *)dev->iobase));
Louis Su30f57472008-07-09 11:01:37 +0800388}
389
390static inline void WRITE_TXBUF (struct eth_device *dev, unsigned long data)
391{
Mike Frysingercafb14f2010-06-02 21:03:50 -0400392 writel(cpu_to_le32(data), TXBUFFER_START + (void *)dev->iobase);
Louis Su30f57472008-07-09 11:01:37 +0800393}
394#endif
395
396#endif /* _AX88180_H_ */