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wdenkc6097192002-11-03 00:24:07 +00001/*
2 * (C) Copyright 2001
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
Stefan Roese82f4c6a2005-08-12 16:52:47 +020035#define CONFIG_IDENT_STRING " $Name: $"
wdenkc6097192002-11-03 00:24:07 +000036
37#define CONFIG_405GP 1 /* This is a PPC405 CPU */
wdenkc837dcb2004-01-20 23:12:12 +000038#define CONFIG_4xx 1 /* ...member of PPC4xx family */
39#define CONFIG_DU405 1 /* ...on a DU405 board */
wdenkc6097192002-11-03 00:24:07 +000040
wdenkc837dcb2004-01-20 23:12:12 +000041#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
Stefan Roese82f4c6a2005-08-12 16:52:47 +020042#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
wdenkc6097192002-11-03 00:24:07 +000043
wdenkc837dcb2004-01-20 23:12:12 +000044#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
wdenkc6097192002-11-03 00:24:07 +000045
46#define CONFIG_BAUDRATE 9600
47#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
48
49#undef CONFIG_BOOTARGS
50#define CONFIG_BOOTCOMMAND "bootm fff00000"
51
stroesea20b27a2004-12-16 18:05:42 +000052#define CONFIG_PREBOOT /* enable preboot variable */
53
wdenkc6097192002-11-03 00:24:07 +000054#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
55#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
56
57#define CONFIG_MII 1 /* MII PHY management */
wdenkc837dcb2004-01-20 23:12:12 +000058#define CONFIG_PHY_ADDR 0 /* PHY address */
stroesea20b27a2004-12-16 18:05:42 +000059#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
wdenkc6097192002-11-03 00:24:07 +000060
61#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
62 CFG_CMD_PCI | \
63 CFG_CMD_IRQ | \
64 CFG_CMD_IDE | \
65 CFG_CMD_ELF | \
stroesea20b27a2004-12-16 18:05:42 +000066 CFG_CMD_MII | \
wdenkc6097192002-11-03 00:24:07 +000067 CFG_CMD_DATE | \
wdenkc837dcb2004-01-20 23:12:12 +000068 CFG_CMD_EEPROM )
wdenkc6097192002-11-03 00:24:07 +000069
70#define CONFIG_MAC_PARTITION
71#define CONFIG_DOS_PARTITION
72
73/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
74#include <cmd_confdefs.h>
75
76#undef CONFIG_WATCHDOG /* watchdog disabled */
77
wdenkc837dcb2004-01-20 23:12:12 +000078#define CONFIG_RTC_MC146818 /* BQ3285 is MC146818 compatible*/
79#define CFG_RTC_REG_BASE_ADDR 0xF0000080 /* RTC Base Address */
wdenkc6097192002-11-03 00:24:07 +000080
wdenkc837dcb2004-01-20 23:12:12 +000081#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
wdenkc6097192002-11-03 00:24:07 +000082
83/*
84 * Miscellaneous configurable options
85 */
86#define CFG_LONGHELP /* undef to save memory */
87#define CFG_PROMPT "=> " /* Monitor Command Prompt */
88#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
wdenkc837dcb2004-01-20 23:12:12 +000089#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkc6097192002-11-03 00:24:07 +000090#else
wdenkc837dcb2004-01-20 23:12:12 +000091#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
wdenkc6097192002-11-03 00:24:07 +000092#endif
93#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
94#define CFG_MAXARGS 16 /* max number of command args */
95#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
96
wdenkc837dcb2004-01-20 23:12:12 +000097#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
wdenkc6097192002-11-03 00:24:07 +000098
99#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
100#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
101
wdenkc837dcb2004-01-20 23:12:12 +0000102#define CFG_EXT_SERIAL_CLOCK 11059200 /* use external serial clock */
wdenkc6097192002-11-03 00:24:07 +0000103
104/* The following table includes the supported baudrates */
wdenkc837dcb2004-01-20 23:12:12 +0000105#define CFG_BAUDRATE_TABLE \
wdenk8bde7f72003-06-27 21:31:46 +0000106 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
107 57600, 115200, 230400, 460800, 921600 }
wdenkc6097192002-11-03 00:24:07 +0000108
109#define CFG_LOAD_ADDR 0x100000 /* default load address */
110#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
111
wdenkc837dcb2004-01-20 23:12:12 +0000112#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenkc6097192002-11-03 00:24:07 +0000113
114#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
115
stroesea20b27a2004-12-16 18:05:42 +0000116#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
117
wdenkc6097192002-11-03 00:24:07 +0000118/*-----------------------------------------------------------------------
119 * PCI stuff
120 *-----------------------------------------------------------------------
121 */
wdenkc837dcb2004-01-20 23:12:12 +0000122#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
123#define PCI_HOST_FORCE 1 /* configure as pci host */
124#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
wdenkc6097192002-11-03 00:24:07 +0000125
wdenkc837dcb2004-01-20 23:12:12 +0000126#define CONFIG_PCI /* include pci support */
127#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
128#define CONFIG_PCI_PNP /* do pci plug-and-play */
129 /* resource configuration */
wdenkc6097192002-11-03 00:24:07 +0000130
wdenkc837dcb2004-01-20 23:12:12 +0000131#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
stroesead10dd92003-02-14 11:21:23 +0000132
wdenkc837dcb2004-01-20 23:12:12 +0000133#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
stroesead10dd92003-02-14 11:21:23 +0000134
wdenkc837dcb2004-01-20 23:12:12 +0000135#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
136#define CFG_PCI_SUBSYS_DEVICEID 0x0404 /* PCI Device ID: CPCI-ISER4 */
137#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
138#define CFG_PCI_PTM1MS 0xff000001 /* 16MB, enable hard-wired to 1 */
139#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
140#define CFG_PCI_PTM2LA 0xffe00000 /* point to flash */
141#define CFG_PCI_PTM2MS 0xffe00001 /* 2MB, enable */
142#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
wdenkc6097192002-11-03 00:24:07 +0000143
144/*-----------------------------------------------------------------------
145 * IDE/ATA stuff
146 *-----------------------------------------------------------------------
147 */
wdenkc837dcb2004-01-20 23:12:12 +0000148#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
149#undef CONFIG_IDE_LED /* no led for ide supported */
150#undef CONFIG_IDE_RESET /* no reset for ide supported */
wdenkc6097192002-11-03 00:24:07 +0000151
wdenkc837dcb2004-01-20 23:12:12 +0000152#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */
153#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
wdenkc6097192002-11-03 00:24:07 +0000154
wdenkc837dcb2004-01-20 23:12:12 +0000155#define CFG_ATA_BASE_ADDR 0xF0100000
156#define CFG_ATA_IDE0_OFFSET 0x0000
wdenkc6097192002-11-03 00:24:07 +0000157
158#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
wdenkc837dcb2004-01-20 23:12:12 +0000159#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
wdenkc6097192002-11-03 00:24:07 +0000160#define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
161
162/*-----------------------------------------------------------------------
163 * Start addresses for the final memory configuration
164 * (Set up by the startup code)
165 * Please note that CFG_SDRAM_BASE _must_ start at 0
166 */
167#define CFG_SDRAM_BASE 0x00000000
168#define CFG_FLASH_BASE 0xFFFD0000
169#define CFG_MONITOR_BASE CFG_FLASH_BASE
170#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 192 kB for Monitor */
171#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
172
173/*
174 * For booting Linux, the board info and command line data
175 * have to be in the first 8 MB of memory, since this is
176 * the maximum mapped by the Linux kernel during initialization.
177 */
178#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
179/*-----------------------------------------------------------------------
180 * FLASH organization
181 */
182#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
183#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
184
185#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
186#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
187
wdenkc837dcb2004-01-20 23:12:12 +0000188#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
189#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
190#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
wdenkc6097192002-11-03 00:24:07 +0000191/*
192 * The following defines are added for buggy IOP480 byte interface.
193 * All other boards should use the standard values (CPCI405 etc.)
194 */
wdenkc837dcb2004-01-20 23:12:12 +0000195#define CFG_FLASH_READ0 0x0000 /* 0 is standard */
196#define CFG_FLASH_READ1 0x0001 /* 1 is standard */
197#define CFG_FLASH_READ2 0x0002 /* 2 is standard */
wdenkc6097192002-11-03 00:24:07 +0000198
wdenkc837dcb2004-01-20 23:12:12 +0000199#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
wdenkc6097192002-11-03 00:24:07 +0000200
201/*-----------------------------------------------------------------------
202 * I2C EEPROM (CAT24WC08) for environment
203 */
204#define CONFIG_HARD_I2C /* I2c with hardware support */
205#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
206#define CFG_I2C_SLAVE 0x7F
207
208#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
wdenkc837dcb2004-01-20 23:12:12 +0000209#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
210/* mask of address bits that overflow into the "EEPROM chip address" */
wdenkc6097192002-11-03 00:24:07 +0000211#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
212#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
213 /* 16 byte page write mode using*/
wdenkc837dcb2004-01-20 23:12:12 +0000214 /* last 4 bits of the address */
wdenkc6097192002-11-03 00:24:07 +0000215#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
216#define CFG_EEPROM_PAGE_WRITE_ENABLE
217
wdenkc837dcb2004-01-20 23:12:12 +0000218#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
219#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
220#define CFG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars */
wdenk8bde7f72003-06-27 21:31:46 +0000221 /* total size of a CAT24WC08 is 1024 bytes */
wdenkc6097192002-11-03 00:24:07 +0000222
223/*-----------------------------------------------------------------------
224 * Cache Configuration
225 */
Wolfgang Denk0c8721a2005-09-23 11:05:55 +0200226#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
wdenkc6097192002-11-03 00:24:07 +0000227#define CFG_CACHELINE_SIZE 32 /* ... */
228#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
229#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
230#endif
231
232/*
233 * Init Memory Controller:
234 *
235 * BR0/1 and OR0/1 (FLASH)
236 */
237
238#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */
239#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */
240
241/*-----------------------------------------------------------------------
242 * External Bus Controller (EBC) Setup
243 */
244
wdenkc837dcb2004-01-20 23:12:12 +0000245#define FLASH0_BA 0xFFC00000 /* FLASH 0 Base Address */
246#define FLASH1_BA 0xFF800000 /* FLASH 1 Base Address */
247#define CAN_BA 0xF0000000 /* CAN Base Address */
248#define DUART_BA 0xF0300000 /* DUART Base Address */
249#define CF_BA 0xF0100000 /* CompactFlash Base Address */
250#define SRAM_BA 0xF0200000 /* SRAM Base Address */
251#define DURAG_IO_BA 0xF0400000 /* DURAG Bus IO Base Address */
252#define DURAG_MEM_BA 0xF0500000 /* DURAG Bus Mem Base Address */
wdenkc6097192002-11-03 00:24:07 +0000253
wdenkc837dcb2004-01-20 23:12:12 +0000254#define FPGA_MODE_REG (DUART_BA+0x80) /* FPGA Mode Register */
wdenkc6097192002-11-03 00:24:07 +0000255
wdenkc837dcb2004-01-20 23:12:12 +0000256/* Memory Bank 0 (Flash Bank 0) initialization */
257#define CFG_EBC_PB0AP 0x92015480
258#define CFG_EBC_PB0CR FLASH0_BA | 0x5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
wdenkc6097192002-11-03 00:24:07 +0000259
wdenkc837dcb2004-01-20 23:12:12 +0000260/* Memory Bank 1 (Flash Bank 1) initialization */
261#define CFG_EBC_PB1AP 0x92015480
262#define CFG_EBC_PB1CR FLASH1_BA | 0x5A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
wdenkc6097192002-11-03 00:24:07 +0000263
wdenkc837dcb2004-01-20 23:12:12 +0000264/* Memory Bank 2 (CAN0) initialization */
265#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
266#define CFG_EBC_PB2CR CAN_BA | 0x18000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
wdenkc6097192002-11-03 00:24:07 +0000267
wdenkc837dcb2004-01-20 23:12:12 +0000268/* Memory Bank 3 (DUART) initialization */
269#define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
270#define CFG_EBC_PB3CR DUART_BA | 0x18000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */
wdenkc6097192002-11-03 00:24:07 +0000271
wdenkc837dcb2004-01-20 23:12:12 +0000272/* Memory Bank 4 (CompactFlash IDE) initialization */
273#define CFG_EBC_PB4AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
274#define CFG_EBC_PB4CR CF_BA | 0x1A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
wdenkc6097192002-11-03 00:24:07 +0000275
wdenkc837dcb2004-01-20 23:12:12 +0000276/* Memory Bank 5 (SRAM) initialization */
277#define CFG_EBC_PB5AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
278#define CFG_EBC_PB5CR SRAM_BA | 0x1A000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=16bit */
wdenkc6097192002-11-03 00:24:07 +0000279
wdenkc837dcb2004-01-20 23:12:12 +0000280/* Memory Bank 6 (DURAG Bus IO Space) initialization */
281#define CFG_EBC_PB6AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
282#define CFG_EBC_PB6CR DURAG_IO_BA | 0x18000 /* BAS=0xF04,BS=1MB,BU=R/W,BW=8bit*/
wdenkc6097192002-11-03 00:24:07 +0000283
wdenkc837dcb2004-01-20 23:12:12 +0000284/* Memory Bank 7 (DURAG Bus Mem Space) initialization */
285#define CFG_EBC_PB7AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
286#define CFG_EBC_PB7CR DURAG_MEM_BA | 0x18000 /* BAS=0xF05,BS=1MB,BU=R/W,BW=8bit */
wdenkc6097192002-11-03 00:24:07 +0000287
288
289/*-----------------------------------------------------------------------
290 * Definitions for initial stack pointer and data area (in DPRAM)
291 */
292
293/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
wdenkc837dcb2004-01-20 23:12:12 +0000294#define CFG_TEMP_STACK_OCM 1
wdenkc6097192002-11-03 00:24:07 +0000295
296/* On Chip Memory location */
297#define CFG_OCM_DATA_ADDR 0xF8000000
298#define CFG_OCM_DATA_SIZE 0x1000
299
300#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
301#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
302#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
303#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
wdenkc837dcb2004-01-20 23:12:12 +0000304#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
wdenkc6097192002-11-03 00:24:07 +0000305
306
307/*
308 * Internal Definitions
309 *
310 * Boot Flags
311 */
312#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
313#define BOOTFLAG_WARM 0x02 /* Software reboot */
314
315#endif /* __CONFIG_H */