blob: 9926235b52e0067626e332cc3f2c0d272bfd698e [file] [log] [blame]
Vikas Manocha94d53082017-02-12 10:25:49 -08001#include <common.h>
Vikas Manocha94d53082017-02-12 10:25:49 -08002#include <dm.h>
Benjamin Gaignard075b0182018-11-27 13:49:53 +01003#include <hwspinlock.h>
Simon Glass336d4612020-02-03 07:36:16 -07004#include <malloc.h>
Vikas Manocha77417102017-04-10 15:02:57 -07005#include <asm/arch/gpio.h>
6#include <asm/gpio.h>
7#include <asm/io.h>
Simon Glass336d4612020-02-03 07:36:16 -07008#include <dm/device_compat.h>
Patrice Chotard73858262019-07-30 19:16:10 +02009#include <dm/lists.h>
10#include <dm/pinctrl.h>
Simon Glass61b29b82020-02-03 07:36:15 -070011#include <linux/err.h>
Vikas Manocha94d53082017-02-12 10:25:49 -080012
13DECLARE_GLOBAL_DATA_PTR;
14
Vikas Manocha58fb3c82017-04-10 15:03:04 -070015#define MAX_PINS_ONE_IP 70
Vikas Manocha77417102017-04-10 15:02:57 -070016#define MODE_BITS_MASK 3
17#define OSPEED_MASK 3
18#define PUPD_MASK 3
19#define OTYPE_MSK 1
20#define AFR_MASK 0xF
21
Patrice Chotard8f651ca2018-10-24 14:10:18 +020022struct stm32_pinctrl_priv {
Benjamin Gaignard075b0182018-11-27 13:49:53 +010023 struct hwspinlock hws;
Patrice Chotard8f651ca2018-10-24 14:10:18 +020024 int pinctrl_ngpios;
25 struct list_head gpio_dev;
26};
27
28struct stm32_gpio_bank {
29 struct udevice *gpio_dev;
30 struct list_head list;
31};
32
Benjamin Gaignard075b0182018-11-27 13:49:53 +010033#ifndef CONFIG_SPL_BUILD
34
Patrice Chotard4ff1c202018-10-24 14:10:19 +020035static char pin_name[PINNAME_SIZE];
Patrice Chotardb42d9382018-10-24 14:10:20 +020036#define PINMUX_MODE_COUNT 5
37static const char * const pinmux_mode[PINMUX_MODE_COUNT] = {
38 "gpio input",
39 "gpio output",
40 "analog",
41 "unknown",
42 "alt function",
43};
44
45static int stm32_pinctrl_get_af(struct udevice *dev, unsigned int offset)
46{
47 struct stm32_gpio_priv *priv = dev_get_priv(dev);
48 struct stm32_gpio_regs *regs = priv->regs;
49 u32 af;
50 u32 alt_shift = (offset % 8) * 4;
51 u32 alt_index = offset / 8;
52
53 af = (readl(&regs->afr[alt_index]) &
54 GENMASK(alt_shift + 3, alt_shift)) >> alt_shift;
55
56 return af;
57}
58
Patrice Chotard04355042018-12-03 10:52:50 +010059static int stm32_populate_gpio_dev_list(struct udevice *dev)
60{
61 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
62 struct udevice *gpio_dev;
63 struct udevice *child;
64 struct stm32_gpio_bank *gpio_bank;
65 int ret;
66
67 /*
68 * parse pin-controller sub-nodes (ie gpio bank nodes) and fill
69 * a list with all gpio device reference which belongs to the
70 * current pin-controller. This list is used to find pin_name and
71 * pin muxing
72 */
73 list_for_each_entry(child, &dev->child_head, sibling_node) {
74 ret = uclass_get_device_by_name(UCLASS_GPIO, child->name,
75 &gpio_dev);
76 if (ret < 0)
77 continue;
78
79 gpio_bank = malloc(sizeof(*gpio_bank));
80 if (!gpio_bank) {
81 dev_err(dev, "Not enough memory\n");
82 return -ENOMEM;
83 }
84
85 gpio_bank->gpio_dev = gpio_dev;
86 list_add_tail(&gpio_bank->list, &priv->gpio_dev);
87 }
88
89 return 0;
90}
91
Patrice Chotard8f651ca2018-10-24 14:10:18 +020092static int stm32_pinctrl_get_pins_count(struct udevice *dev)
93{
94 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
95 struct gpio_dev_priv *uc_priv;
96 struct stm32_gpio_bank *gpio_bank;
97
98 /*
99 * if get_pins_count has already been executed once on this
100 * pin-controller, no need to run it again
101 */
102 if (priv->pinctrl_ngpios)
103 return priv->pinctrl_ngpios;
104
Patrice Chotard04355042018-12-03 10:52:50 +0100105 if (list_empty(&priv->gpio_dev))
106 stm32_populate_gpio_dev_list(dev);
Patrice Chotard8f651ca2018-10-24 14:10:18 +0200107 /*
108 * walk through all banks to retrieve the pin-controller
109 * pins number
110 */
111 list_for_each_entry(gpio_bank, &priv->gpio_dev, list) {
112 uc_priv = dev_get_uclass_priv(gpio_bank->gpio_dev);
113
114 priv->pinctrl_ngpios += uc_priv->gpio_count;
115 }
116
117 return priv->pinctrl_ngpios;
118}
119
Patrice Chotard4ff1c202018-10-24 14:10:19 +0200120static struct udevice *stm32_pinctrl_get_gpio_dev(struct udevice *dev,
Patrice Chotard530b63c2018-12-03 10:52:54 +0100121 unsigned int selector,
122 unsigned int *idx)
Patrice Chotard4ff1c202018-10-24 14:10:19 +0200123{
124 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
125 struct stm32_gpio_bank *gpio_bank;
126 struct gpio_dev_priv *uc_priv;
Patrice Chotard530b63c2018-12-03 10:52:54 +0100127 int pin_count = 0;
Patrice Chotard4ff1c202018-10-24 14:10:19 +0200128
Patrice Chotard04355042018-12-03 10:52:50 +0100129 if (list_empty(&priv->gpio_dev))
130 stm32_populate_gpio_dev_list(dev);
131
Patrice Chotard4ff1c202018-10-24 14:10:19 +0200132 /* look up for the bank which owns the requested pin */
133 list_for_each_entry(gpio_bank, &priv->gpio_dev, list) {
134 uc_priv = dev_get_uclass_priv(gpio_bank->gpio_dev);
135
Patrice Chotard530b63c2018-12-03 10:52:54 +0100136 if (selector < (pin_count + uc_priv->gpio_count)) {
137 /*
138 * we found the bank, convert pin selector to
139 * gpio bank index
140 */
141 *idx = stm32_offset_to_index(gpio_bank->gpio_dev,
142 selector - pin_count);
Patrick Delaunay91ca91e2019-06-21 15:26:52 +0200143 if (IS_ERR_VALUE(*idx))
Patrice Chotard530b63c2018-12-03 10:52:54 +0100144 return NULL;
Patrice Chotard4ff1c202018-10-24 14:10:19 +0200145
Patrice Chotard530b63c2018-12-03 10:52:54 +0100146 return gpio_bank->gpio_dev;
147 }
148 pin_count += uc_priv->gpio_count;
Patrice Chotard4ff1c202018-10-24 14:10:19 +0200149 }
150
151 return NULL;
152}
153
154static const char *stm32_pinctrl_get_pin_name(struct udevice *dev,
155 unsigned int selector)
156{
157 struct gpio_dev_priv *uc_priv;
158 struct udevice *gpio_dev;
Patrice Chotard530b63c2018-12-03 10:52:54 +0100159 unsigned int gpio_idx;
Patrice Chotard4ff1c202018-10-24 14:10:19 +0200160
161 /* look up for the bank which owns the requested pin */
Patrice Chotard530b63c2018-12-03 10:52:54 +0100162 gpio_dev = stm32_pinctrl_get_gpio_dev(dev, selector, &gpio_idx);
Patrice Chotard4ff1c202018-10-24 14:10:19 +0200163 if (!gpio_dev) {
164 snprintf(pin_name, PINNAME_SIZE, "Error");
165 } else {
166 uc_priv = dev_get_uclass_priv(gpio_dev);
167
168 snprintf(pin_name, PINNAME_SIZE, "%s%d",
169 uc_priv->bank_name,
Patrice Chotard530b63c2018-12-03 10:52:54 +0100170 gpio_idx);
Patrice Chotard4ff1c202018-10-24 14:10:19 +0200171 }
172
173 return pin_name;
174}
Patrice Chotardb42d9382018-10-24 14:10:20 +0200175
176static int stm32_pinctrl_get_pin_muxing(struct udevice *dev,
177 unsigned int selector,
178 char *buf,
179 int size)
180{
181 struct udevice *gpio_dev;
182 const char *label;
Patrice Chotardb42d9382018-10-24 14:10:20 +0200183 int mode;
184 int af_num;
Patrice Chotard530b63c2018-12-03 10:52:54 +0100185 unsigned int gpio_idx;
Patrice Chotardb42d9382018-10-24 14:10:20 +0200186
187 /* look up for the bank which owns the requested pin */
Patrice Chotard530b63c2018-12-03 10:52:54 +0100188 gpio_dev = stm32_pinctrl_get_gpio_dev(dev, selector, &gpio_idx);
Patrice Chotardb42d9382018-10-24 14:10:20 +0200189
190 if (!gpio_dev)
191 return -ENODEV;
192
Patrice Chotard530b63c2018-12-03 10:52:54 +0100193 mode = gpio_get_raw_function(gpio_dev, gpio_idx, &label);
Patrice Chotardb42d9382018-10-24 14:10:20 +0200194
Patrice Chotard530b63c2018-12-03 10:52:54 +0100195 dev_dbg(dev, "selector = %d gpio_idx = %d mode = %d\n",
196 selector, gpio_idx, mode);
Patrice Chotardb42d9382018-10-24 14:10:20 +0200197
Patrice Chotardb42d9382018-10-24 14:10:20 +0200198
199 switch (mode) {
200 case GPIOF_UNKNOWN:
201 /* should never happen */
202 return -EINVAL;
203 case GPIOF_UNUSED:
204 snprintf(buf, size, "%s", pinmux_mode[mode]);
205 break;
206 case GPIOF_FUNC:
Patrice Chotard530b63c2018-12-03 10:52:54 +0100207 af_num = stm32_pinctrl_get_af(gpio_dev, gpio_idx);
Patrice Chotardb42d9382018-10-24 14:10:20 +0200208 snprintf(buf, size, "%s %d", pinmux_mode[mode], af_num);
209 break;
210 case GPIOF_OUTPUT:
211 case GPIOF_INPUT:
212 snprintf(buf, size, "%s %s",
213 pinmux_mode[mode], label ? label : "");
214 break;
215 }
216
217 return 0;
218}
219
Benjamin Gaignard075b0182018-11-27 13:49:53 +0100220#endif
221
Patrick Delaunay91ca91e2019-06-21 15:26:52 +0200222static int stm32_pinctrl_probe(struct udevice *dev)
Patrice Chotard8f651ca2018-10-24 14:10:18 +0200223{
224 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
Patrice Chotard8f651ca2018-10-24 14:10:18 +0200225 int ret;
226
227 INIT_LIST_HEAD(&priv->gpio_dev);
228
Benjamin Gaignard075b0182018-11-27 13:49:53 +0100229 /* hwspinlock property is optional, just log the error */
230 ret = hwspinlock_get_by_index(dev, 0, &priv->hws);
231 if (ret)
232 debug("%s: hwspinlock_get_by_index may have failed (%d)\n",
233 __func__, ret);
234
Patrice Chotard8f651ca2018-10-24 14:10:18 +0200235 return 0;
236}
Patrice Chotard8f651ca2018-10-24 14:10:18 +0200237
Vikas Manocha77417102017-04-10 15:02:57 -0700238static int stm32_gpio_config(struct gpio_desc *desc,
239 const struct stm32_gpio_ctl *ctl)
240{
241 struct stm32_gpio_priv *priv = dev_get_priv(desc->dev);
242 struct stm32_gpio_regs *regs = priv->regs;
Benjamin Gaignard075b0182018-11-27 13:49:53 +0100243 struct stm32_pinctrl_priv *ctrl_priv;
244 int ret;
Vikas Manocha77417102017-04-10 15:02:57 -0700245 u32 index;
246
247 if (!ctl || ctl->af > 15 || ctl->mode > 3 || ctl->otype > 1 ||
248 ctl->pupd > 2 || ctl->speed > 3)
249 return -EINVAL;
250
Benjamin Gaignard075b0182018-11-27 13:49:53 +0100251 ctrl_priv = dev_get_priv(dev_get_parent(desc->dev));
252 ret = hwspinlock_lock_timeout(&ctrl_priv->hws, 10);
253 if (ret == -ETIME) {
254 dev_err(desc->dev, "HWSpinlock timeout\n");
255 return ret;
256 }
257
Vikas Manocha77417102017-04-10 15:02:57 -0700258 index = (desc->offset & 0x07) * 4;
259 clrsetbits_le32(&regs->afr[desc->offset >> 3], AFR_MASK << index,
260 ctl->af << index);
261
262 index = desc->offset * 2;
263 clrsetbits_le32(&regs->moder, MODE_BITS_MASK << index,
264 ctl->mode << index);
265 clrsetbits_le32(&regs->ospeedr, OSPEED_MASK << index,
266 ctl->speed << index);
267 clrsetbits_le32(&regs->pupdr, PUPD_MASK << index, ctl->pupd << index);
268
269 index = desc->offset;
270 clrsetbits_le32(&regs->otyper, OTYPE_MSK << index, ctl->otype << index);
271
Benjamin Gaignard075b0182018-11-27 13:49:53 +0100272 hwspinlock_unlock(&ctrl_priv->hws);
273
Vikas Manocha77417102017-04-10 15:02:57 -0700274 return 0;
275}
Patrick Delaunay8aeba622018-03-12 10:46:13 +0100276
Vikas Manocha94d53082017-02-12 10:25:49 -0800277static int prep_gpio_dsc(struct stm32_gpio_dsc *gpio_dsc, u32 port_pin)
278{
Patrick Delaunay8aeba622018-03-12 10:46:13 +0100279 gpio_dsc->port = (port_pin & 0x1F000) >> 12;
Vikas Manocha94d53082017-02-12 10:25:49 -0800280 gpio_dsc->pin = (port_pin & 0x0F00) >> 8;
281 debug("%s: GPIO:port= %d, pin= %d\n", __func__, gpio_dsc->port,
282 gpio_dsc->pin);
283
284 return 0;
285}
286
287static int prep_gpio_ctl(struct stm32_gpio_ctl *gpio_ctl, u32 gpio_fn, int node)
288{
289 gpio_fn &= 0x00FF;
Vikas Manocha77417102017-04-10 15:02:57 -0700290 gpio_ctl->af = 0;
Vikas Manocha94d53082017-02-12 10:25:49 -0800291
292 switch (gpio_fn) {
293 case 0:
294 gpio_ctl->mode = STM32_GPIO_MODE_IN;
295 break;
296 case 1 ... 16:
297 gpio_ctl->mode = STM32_GPIO_MODE_AF;
298 gpio_ctl->af = gpio_fn - 1;
299 break;
300 case 17:
301 gpio_ctl->mode = STM32_GPIO_MODE_AN;
302 break;
303 default:
304 gpio_ctl->mode = STM32_GPIO_MODE_OUT;
305 break;
306 }
307
308 gpio_ctl->speed = fdtdec_get_int(gd->fdt_blob, node, "slew-rate", 0);
309
310 if (fdtdec_get_bool(gd->fdt_blob, node, "drive-open-drain"))
311 gpio_ctl->otype = STM32_GPIO_OTYPE_OD;
312 else
313 gpio_ctl->otype = STM32_GPIO_OTYPE_PP;
314
315 if (fdtdec_get_bool(gd->fdt_blob, node, "bias-pull-up"))
316 gpio_ctl->pupd = STM32_GPIO_PUPD_UP;
317 else if (fdtdec_get_bool(gd->fdt_blob, node, "bias-pull-down"))
318 gpio_ctl->pupd = STM32_GPIO_PUPD_DOWN;
319 else
320 gpio_ctl->pupd = STM32_GPIO_PUPD_NO;
321
322 debug("%s: gpio fn= %d, slew-rate= %x, op type= %x, pull-upd is = %x\n",
323 __func__, gpio_fn, gpio_ctl->speed, gpio_ctl->otype,
324 gpio_ctl->pupd);
325
326 return 0;
327}
328
Christophe Kerelload0376e2017-06-20 17:04:18 +0200329static int stm32_pinctrl_config(int offset)
Vikas Manocha94d53082017-02-12 10:25:49 -0800330{
Vikas Manocha58fb3c82017-04-10 15:03:04 -0700331 u32 pin_mux[MAX_PINS_ONE_IP];
Vikas Manocha94d53082017-02-12 10:25:49 -0800332 int rv, len;
333
Vikas Manocha94d53082017-02-12 10:25:49 -0800334 /*
335 * check for "pinmux" property in each subnode (e.g. pins1 and pins2 for
336 * usart1) of pin controller phandle "pinctrl-0"
337 * */
Christophe Kerelload0376e2017-06-20 17:04:18 +0200338 fdt_for_each_subnode(offset, gd->fdt_blob, offset) {
Vikas Manocha94d53082017-02-12 10:25:49 -0800339 struct stm32_gpio_dsc gpio_dsc;
340 struct stm32_gpio_ctl gpio_ctl;
341 int i;
342
Christophe Kerelload0376e2017-06-20 17:04:18 +0200343 len = fdtdec_get_int_array_count(gd->fdt_blob, offset,
Vikas Manocha94d53082017-02-12 10:25:49 -0800344 "pinmux", pin_mux,
345 ARRAY_SIZE(pin_mux));
Christophe Kerelload0376e2017-06-20 17:04:18 +0200346 debug("%s: no of pinmux entries= %d\n", __func__, len);
Vikas Manocha94d53082017-02-12 10:25:49 -0800347 if (len < 0)
348 return -EINVAL;
349 for (i = 0; i < len; i++) {
Vikas Manocha280057b2017-04-10 15:02:59 -0700350 struct gpio_desc desc;
Patrick Delaunay8aeba622018-03-12 10:46:13 +0100351
Vikas Manocha94d53082017-02-12 10:25:49 -0800352 debug("%s: pinmux = %x\n", __func__, *(pin_mux + i));
353 prep_gpio_dsc(&gpio_dsc, *(pin_mux + i));
Christophe Kerelload0376e2017-06-20 17:04:18 +0200354 prep_gpio_ctl(&gpio_ctl, *(pin_mux + i), offset);
Vikas Manocha280057b2017-04-10 15:02:59 -0700355 rv = uclass_get_device_by_seq(UCLASS_GPIO,
Patrick Delaunay8aeba622018-03-12 10:46:13 +0100356 gpio_dsc.port,
357 &desc.dev);
Vikas Manocha280057b2017-04-10 15:02:59 -0700358 if (rv)
359 return rv;
360 desc.offset = gpio_dsc.pin;
361 rv = stm32_gpio_config(&desc, &gpio_ctl);
Vikas Manocha94d53082017-02-12 10:25:49 -0800362 debug("%s: rv = %d\n\n", __func__, rv);
363 if (rv)
364 return rv;
365 }
366 }
367
368 return 0;
369}
370
Patrice Chotard158abbf2019-06-21 15:39:23 +0200371static int stm32_pinctrl_bind(struct udevice *dev)
372{
373 ofnode node;
374 const char *name;
375 int ret;
376
377 dev_for_each_subnode(node, dev) {
378 debug("%s: bind %s\n", __func__, ofnode_get_name(node));
379
380 ofnode_get_property(node, "gpio-controller", &ret);
381 if (ret < 0)
382 continue;
383 /* Get the name of each gpio node */
384 name = ofnode_get_name(node);
385 if (!name)
386 return -EINVAL;
387
388 /* Bind each gpio node */
389 ret = device_bind_driver_to_node(dev, "gpio_stm32",
390 name, node, NULL);
391 if (ret)
392 return ret;
393
394 debug("%s: bind %s\n", __func__, name);
395 }
396
397 return 0;
398}
399
Christophe Kerellobb44b962017-06-20 17:04:19 +0200400#if CONFIG_IS_ENABLED(PINCTRL_FULL)
401static int stm32_pinctrl_set_state(struct udevice *dev, struct udevice *config)
402{
403 return stm32_pinctrl_config(dev_of_offset(config));
404}
405#else /* PINCTRL_FULL */
Christophe Kerelload0376e2017-06-20 17:04:18 +0200406static int stm32_pinctrl_set_state_simple(struct udevice *dev,
407 struct udevice *periph)
408{
409 const void *fdt = gd->fdt_blob;
410 const fdt32_t *list;
411 uint32_t phandle;
412 int config_node;
413 int size, i, ret;
414
415 list = fdt_getprop(fdt, dev_of_offset(periph), "pinctrl-0", &size);
416 if (!list)
417 return -EINVAL;
418
419 debug("%s: periph->name = %s\n", __func__, periph->name);
420
421 size /= sizeof(*list);
422 for (i = 0; i < size; i++) {
423 phandle = fdt32_to_cpu(*list++);
424
425 config_node = fdt_node_offset_by_phandle(fdt, phandle);
426 if (config_node < 0) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900427 pr_err("prop pinctrl-0 index %d invalid phandle\n", i);
Christophe Kerelload0376e2017-06-20 17:04:18 +0200428 return -EINVAL;
429 }
430
431 ret = stm32_pinctrl_config(config_node);
432 if (ret)
433 return ret;
434 }
435
436 return 0;
437}
Christophe Kerellobb44b962017-06-20 17:04:19 +0200438#endif /* PINCTRL_FULL */
Christophe Kerelload0376e2017-06-20 17:04:18 +0200439
Vikas Manocha94d53082017-02-12 10:25:49 -0800440static struct pinctrl_ops stm32_pinctrl_ops = {
Christophe Kerellobb44b962017-06-20 17:04:19 +0200441#if CONFIG_IS_ENABLED(PINCTRL_FULL)
442 .set_state = stm32_pinctrl_set_state,
443#else /* PINCTRL_FULL */
Vikas Manocha94d53082017-02-12 10:25:49 -0800444 .set_state_simple = stm32_pinctrl_set_state_simple,
Christophe Kerellobb44b962017-06-20 17:04:19 +0200445#endif /* PINCTRL_FULL */
Patrice Chotard8f651ca2018-10-24 14:10:18 +0200446#ifndef CONFIG_SPL_BUILD
Patrice Chotard4ff1c202018-10-24 14:10:19 +0200447 .get_pin_name = stm32_pinctrl_get_pin_name,
Patrice Chotard8f651ca2018-10-24 14:10:18 +0200448 .get_pins_count = stm32_pinctrl_get_pins_count,
Patrice Chotardb42d9382018-10-24 14:10:20 +0200449 .get_pin_muxing = stm32_pinctrl_get_pin_muxing,
Patrice Chotard8f651ca2018-10-24 14:10:18 +0200450#endif
Vikas Manocha94d53082017-02-12 10:25:49 -0800451};
452
453static const struct udevice_id stm32_pinctrl_ids[] = {
Patrice Chotard98693c22017-12-12 09:49:35 +0100454 { .compatible = "st,stm32f429-pinctrl" },
455 { .compatible = "st,stm32f469-pinctrl" },
Vikas Manocha94d53082017-02-12 10:25:49 -0800456 { .compatible = "st,stm32f746-pinctrl" },
Patrice Chotarddd18df42018-12-11 14:49:18 +0100457 { .compatible = "st,stm32f769-pinctrl" },
Patrice Chotard092e72c2017-09-13 18:00:04 +0200458 { .compatible = "st,stm32h743-pinctrl" },
Patrick Delaunay8aeba622018-03-12 10:46:13 +0100459 { .compatible = "st,stm32mp157-pinctrl" },
460 { .compatible = "st,stm32mp157-z-pinctrl" },
Vikas Manocha94d53082017-02-12 10:25:49 -0800461 { }
462};
463
464U_BOOT_DRIVER(pinctrl_stm32) = {
Patrice Chotard8f651ca2018-10-24 14:10:18 +0200465 .name = "pinctrl_stm32",
466 .id = UCLASS_PINCTRL,
467 .of_match = stm32_pinctrl_ids,
468 .ops = &stm32_pinctrl_ops,
Patrice Chotard158abbf2019-06-21 15:39:23 +0200469 .bind = stm32_pinctrl_bind,
Patrice Chotard8f651ca2018-10-24 14:10:18 +0200470 .probe = stm32_pinctrl_probe,
471 .priv_auto_alloc_size = sizeof(struct stm32_pinctrl_priv),
Vikas Manocha94d53082017-02-12 10:25:49 -0800472};