blob: 1251bc938b5e14d63bd1c4a63dde2f7a25d47574 [file] [log] [blame]
Stefan Roeseb79316f2005-08-15 12:31:23 +02001/*
2 * Copyright (C) 2005 Sandburst Corporation
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22#include <config.h>
23#include <common.h>
24#include <command.h>
25#include <asm/processor.h>
26#include <asm/io.h>
27#include <spd_sdram.h>
28#include <i2c.h>
29#include "ppc440gx_i2c.h"
30#include "sb_common.h"
31
32long int fixed_sdram (void);
33
34/*************************************************************************
35 * metrobox_get_master
36 *
37 * PRI_N - active low signal. If the GPIO pin is low we are the master
38 *
39 ************************************************************************/
40int sbcommon_get_master(void)
41{
42 ppc440_gpio_regs_t *gpio_regs;
43
44 gpio_regs = (ppc440_gpio_regs_t *)CFG_GPIO_BASE;
45
46 if (gpio_regs->in & SBCOMMON_GPIO_PRI_N) {
47 return 0;
48 }
49 else {
50 return 1;
51 }
52}
53
54/*************************************************************************
55 * metrobox_secondary_present
56 *
57 * Figure out if secondary/slave board is present
58 *
59 ************************************************************************/
60int sbcommon_secondary_present(void)
61{
62 ppc440_gpio_regs_t *gpio_regs;
63
64 gpio_regs = (ppc440_gpio_regs_t *)CFG_GPIO_BASE;
65
66 if (gpio_regs->in & SBCOMMON_GPIO_SEC_PRES)
67 return 0;
68 else
69 return 1;
70}
71
72/*************************************************************************
73 * sbcommon_get_serial_number
74 *
75 * Retrieve the board serial number via the mac address in eeprom
76 *
77 ************************************************************************/
78unsigned short sbcommon_get_serial_number(void)
79{
80 unsigned char buff[0x100];
81 unsigned short sernum;
82
83 /* Get the board serial number from eeprom */
84 /* Initialize I2C */
85 i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
86
87 /* Read 256 bytes in EEPROM */
88 i2c_read (0x50, 0, 1, buff, 0x100);
89
90 memcpy(&sernum, &buff[0xF4], 2);
91 sernum /= 32;
92
93 return (sernum);
94}
95
96/*************************************************************************
97 * sbcommon_fans
98 *
99 * Spin up fans 2 & 3 to get some air moving. OS will take care
100 * of the rest. This is mostly a precaution...
101 *
102 * Assumes i2c bus 1 is ready.
103 *
104 ************************************************************************/
105void sbcommon_fans(void)
106{
107 /*
108 * Attempt to turn on 2 of the fans...
109 * Need to go through the bridge
110 */
111 puts ("FANS: ");
112
113 /* select fan4 through the bridge */
114 i2c_reg_write1(0x73, /* addr */
115 0x00, /* reg */
116 0x08); /* val = bus 4 */
117
118 /* Turn on FAN 4 */
119 i2c_reg_write1(0x2e,
120 1,
121 0x80);
122
123 i2c_reg_write1(0x2e,
124 0,
125 0x19);
126
127 /* Deselect bus 4 on the bridge */
128 i2c_reg_write1(0x73,
129 0x00,
130 0x00);
131
132 /* select fan3 through the bridge */
133 i2c_reg_write1(0x73, /* addr */
134 0x00, /* reg */
135 0x04); /* val = bus 3 */
136
137 /* Turn on FAN 3 */
138 i2c_reg_write1(0x2e,
139 1,
140 0x80);
141
142 i2c_reg_write1(0x2e,
143 0,
144 0x19);
145
146 /* Deselect bus 3 on the bridge */
147 i2c_reg_write1(0x73,
148 0x00,
149 0x00);
150
151 /* select fan2 through the bridge */
152 i2c_reg_write1(0x73, /* addr */
153 0x00, /* reg */
154 0x02); /* val = bus 4 */
155
156 /* Turn on FAN 2 */
157 i2c_reg_write1(0x2e,
158 1,
159 0x80);
160
161 i2c_reg_write1(0x2e,
162 0,
163 0x19);
164
165 /* Deselect bus 2 on the bridge */
166 i2c_reg_write1(0x73,
167 0x00,
168 0x00);
169
170 /* select fan1 through the bridge */
171 i2c_reg_write1(0x73, /* addr */
172 0x00, /* reg */
173 0x01); /* val = bus 0 */
174
175 /* Turn on FAN 1 */
176 i2c_reg_write1(0x2e,
177 1,
178 0x80);
179
180 i2c_reg_write1(0x2e,
181 0,
182 0x19);
183
184 /* Deselect bus 1 on the bridge */
185 i2c_reg_write1(0x73,
186 0x00,
187 0x00);
188
189 puts ("on\n");
190
191 return;
192
193}
194
195/*************************************************************************
196 * initdram
197 *
198 * Initialize sdram
199 *
200 ************************************************************************/
201long int initdram (int board_type)
202{
203 long dram_size = 0;
204
205#if defined(CONFIG_SPD_EEPROM)
206 dram_size = spd_sdram (0);
207#else
208 dram_size = fixed_sdram ();
209#endif
210 return dram_size;
211}
212
213
214/*************************************************************************
215 * testdram
216 *
217 *
218 ************************************************************************/
219#if defined(CFG_DRAM_TEST)
220int testdram (void)
221{
222 uint *pstart = (uint *) CFG_MEMTEST_START;
223 uint *pend = (uint *) CFG_MEMTEST_END;
224 uint *p;
225
226 printf("Testing SDRAM: ");
227 for (p = pstart; p < pend; p++)
228 *p = 0xaaaaaaaa;
229
230 for (p = pstart; p < pend; p++) {
231 if (*p != 0xaaaaaaaa) {
232 printf ("SDRAM test fails at: %08x\n", (uint) p);
233 return 1;
234 }
235 }
236
237 for (p = pstart; p < pend; p++)
238 *p = 0x55555555;
239
240 for (p = pstart; p < pend; p++) {
241 if (*p != 0x55555555) {
242 printf ("SDRAM test fails at: %08x\n", (uint) p);
243 return 1;
244 }
245 }
246
247 printf("OK\n");
248 return 0;
249}
250#endif
251
252#if !defined(CONFIG_SPD_EEPROM)
253/*************************************************************************
254 * fixed sdram init -- doesn't use serial presence detect.
255 *
256 * Assumes: 128 MB, non-ECC, non-registered
257 * PLB @ 133 MHz
258 *
259 ************************************************************************/
260long int fixed_sdram (void)
261{
262 uint reg;
263
264 /*--------------------------------------------------------------------
265 * Setup some default
266 *------------------------------------------------------------------*/
267 mtsdram (mem_uabba, 0x00000000); /* ubba=0 (default) */
268 mtsdram (mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
269 mtsdram (mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
270 mtsdram (mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */
271 mtsdram (mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
272
273 /*--------------------------------------------------------------------
274 * Setup for board-specific specific mem
275 *------------------------------------------------------------------*/
276 /*
277 * Following for CAS Latency = 2.5 @ 133 MHz PLB
278 */
279 mtsdram (mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
280 mtsdram (mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
281 /* RA=10 RD=3 */
282 mtsdram (mem_tr1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
283 mtsdram (mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */
284 mtsdram (mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
285 udelay (400); /* Delay 200 usecs (min) */
286
287 /*--------------------------------------------------------------------
288 * Enable the controller, then wait for DCEN to complete
289 *------------------------------------------------------------------*/
290 mtsdram (mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
291 for (;;) {
292 mfsdram (mem_mcsts, reg);
293 if (reg & 0x80000000)
294 break;
295 }
296
297 return (128 * 1024 * 1024); /* 128 MB */
298}
299#endif /* !defined(CONFIG_SPD_EEPROM) */
300
301
302/*************************************************************************
303 * pci_pre_init
304 *
305 * This routine is called just prior to registering the hose and gives
306 * the board the opportunity to check things. Returning a value of zero
307 * indicates that things are bad & PCI initialization should be aborted.
308 *
309 * Different boards may wish to customize the pci controller structure
310 * (add regions, override default access routines, etc) or perform
311 * certain pre-initialization actions.
312 *
313 ************************************************************************/
314#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
315int pci_pre_init(struct pci_controller * hose )
316{
317 unsigned long strap;
318
319 /*--------------------------------------------------------------------------+
320 * The metrobox is always configured as the host & requires the
321 * PCI arbiter to be enabled.
322 *--------------------------------------------------------------------------*/
323 mfsdr(sdr_sdstp1, strap);
324 if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){
325 printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
326 return 0;
327 }
328
329 return 1;
330}
331#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
332
333/*************************************************************************
334 * pci_target_init
335 *
336 * The bootstrap configuration provides default settings for the pci
337 * inbound map (PIM). But the bootstrap config choices are limited and
338 * may not be sufficient for a given board.
339 *
340 ************************************************************************/
341#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
342void pci_target_init(struct pci_controller * hose )
343{
344 DECLARE_GLOBAL_DATA_PTR;
345
346 /*--------------------------------------------------------------------------+
347 * Disable everything
348 *--------------------------------------------------------------------------*/
349 out32r( PCIX0_PIM0SA, 0 ); /* disable */
350 out32r( PCIX0_PIM1SA, 0 ); /* disable */
351 out32r( PCIX0_PIM2SA, 0 ); /* disable */
352 out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
353
354 /*--------------------------------------------------------------------------+
355 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
356 * options to not support sizes such as 128/256 MB.
357 *--------------------------------------------------------------------------*/
358 out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
359 out32r( PCIX0_PIM0LAH, 0 );
360 out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
361
362 out32r( PCIX0_BAR0, 0 );
363
364 /*--------------------------------------------------------------------------+
365 * Program the board's subsystem id/vendor id
366 *--------------------------------------------------------------------------*/
367 out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
368 out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
369
370 out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
371}
372#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
373
374
375/*************************************************************************
376 * is_pci_host
377 *
378 *
379 ************************************************************************/
380#if defined(CONFIG_PCI)
381int is_pci_host(struct pci_controller *hose)
382{
383 /* The metrobox is always configured as host. */
384 return(1);
385}
386#endif /* defined(CONFIG_PCI) */
387
388/*************************************************************************
389 * board_get_enetaddr
390 *
391 * Get the ethernet MAC address for the management ethernet from the
392 * strap EEPROM. Note that is the BASE address for the range of
393 * external ethernet MACs on the board. The base + 31 is the actual
394 * mgmt mac address.
395 *
396 ************************************************************************/
397static int macaddr_idx = 0;
398
399void board_get_enetaddr (uchar * enet)
400{
401 int i;
402 unsigned short tmp;
403 unsigned char buff[0x100], *cp;
404
405 if (0 == macaddr_idx) {
406
407 /* Initialize I2C */
408 i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
409
410 /* Read 256 bytes in EEPROM */
411 i2c_read (0x50, 0, 1, buff, 0x100);
412
413 cp = &buff[0xF0];
414
415 for (i = 0; i < 6; i++,cp++)
416 enet[i] = *cp;
417
418 memcpy(&tmp, &enet[4], 2);
419 tmp += 31;
420 memcpy(&enet[4], &tmp, 2);
421
422 macaddr_idx++;
423 } else {
424 enet[0] = 0x02;
425 enet[1] = 0x00;
426 enet[2] = 0x00;
427 enet[3] = 0x00;
428 enet[4] = 0x00;
429 if (1 == sbcommon_get_master() ) {
430 /* Master/Primary card */
431 enet[5] = 0x01;
432 } else {
433 /* Slave/Secondary card */
434 enet [5] = 0x02;
435 }
436 }
437
438 return;
439}
440
441#ifdef CONFIG_POST
442/*
443 * Returns 1 if keys pressed to start the power-on long-running tests
444 * Called from board_init_f().
445 */
446int post_hotkeys_pressed(void)
447{
448
449 return (ctrlc());
450}
451#endif