blob: c61dbf3557019e8a134a246dd2752d5cc3626ab8 [file] [log] [blame]
Angelo Dureghellob5867b12019-03-13 21:46:41 +01001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
4 */
5
6/ {
7 compatible = "fsl,mcf5208";
8
9 aliases {
10 serial0 = &uart0;
Angelo Durgehello04e5dd52019-11-15 23:54:12 +010011 fec0 = &fec0;
Angelo Dureghellob5867b12019-03-13 21:46:41 +010012 };
13
14 soc {
15 compatible = "simple-bus";
16 #address-cells = <1>;
17 #size-cells = <1>;
18
Angelo Dureghello67d39af2023-06-24 23:38:55 +020019 wdog0: watchdog@fc08c000 {
20 compatible = "fsl,mcf5208-wdt";
21 reg = <0xfc08c000 0x10>;
22 status = "disabled";
23 };
24
Angelo Dureghellob5867b12019-03-13 21:46:41 +010025 uart0: uart@fc060000 {
26 compatible = "fsl,mcf-uart";
27 reg = <0xfc060000 0x40>;
28 status = "disabled";
29 };
30
31 uart1: uart@fc064000 {
32 compatible = "fsl,mcf-uart";
33 reg = <0xfc064000 0x40>;
34 status = "disabled";
35 };
36
37 uart2: uart@fc068000 {
38 compatible = "fsl,mcf-uart";
39 reg = <0xfc068000 0x40>;
40 status = "disabled";
41 };
Angelo Durgehello04e5dd52019-11-15 23:54:12 +010042
43 fec0: ethernet@fc030000 {
44 compatible = "fsl,mcf-fec";
45 reg = <0xfc030000 0x400>;
46 mii-base = <0>;
47 max-speed = <100>;
48 timeout-loop = <50000>;
49 status = "disabled";
50 };
Angelo Dureghello96283b82023-04-05 00:59:27 +020051
52 i2c0: i2c@fc058000 {
53 compatible = "fsl-i2c";
54 #address-cells=<1>;
55 #size-cells=<0>;
56 cell-index = <0>;
57 reg = <0xfc058000 0x14>;
58 clock-frequency = <100000>;
59 status = "disabled";
60 };
Angelo Dureghellob5867b12019-03-13 21:46:41 +010061 };
62};