blob: e0b1fe71a83a24340b6f913825ed63c42a2b27ca [file] [log] [blame]
wdenk024a26b2002-08-21 21:35:08 +00001/*
2 * (C) Copyright 2002
3 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 *
23 */
24
Wolfgang Denk53677ef2008-05-20 16:00:29 +020025#include <linux/types.h> /* for ulong typedef */
wdenk024a26b2002-08-21 21:35:08 +000026
27#ifndef _FPGA_H_
28#define _FPGA_H_
29
30#ifndef CONFIG_MAX_FPGA_DEVICES
31#define CONFIG_MAX_FPGA_DEVICES 5
32#endif
33
34/* these probably belong somewhere else */
35#ifndef FALSE
Wolfgang Denk53677ef2008-05-20 16:00:29 +020036#define FALSE (0)
wdenk024a26b2002-08-21 21:35:08 +000037#endif
38#ifndef TRUE
Wolfgang Denk53677ef2008-05-20 16:00:29 +020039#define TRUE (!FALSE)
wdenk024a26b2002-08-21 21:35:08 +000040#endif
41
42/* CONFIG_FPGA bit assignments */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020043#define CONFIG_SYS_FPGA_MAN(x) (x)
44#define CONFIG_SYS_FPGA_DEV(x) ((x) << 8 )
45#define CONFIG_SYS_FPGA_IF(x) ((x) << 16 )
wdenk024a26b2002-08-21 21:35:08 +000046
47/* FPGA Manufacturer bits in CONFIG_FPGA */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020048#define CONFIG_SYS_FPGA_XILINX CONFIG_SYS_FPGA_MAN( 0x1 )
49#define CONFIG_SYS_FPGA_ALTERA CONFIG_SYS_FPGA_MAN( 0x2 )
wdenk024a26b2002-08-21 21:35:08 +000050
51
52/* fpga_xxxx function return value definitions */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020053#define FPGA_SUCCESS 0
54#define FPGA_FAIL -1
wdenk024a26b2002-08-21 21:35:08 +000055
56/* device numbers must be non-negative */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020057#define FPGA_INVALID_DEVICE -1
wdenk024a26b2002-08-21 21:35:08 +000058
59/* root data type defintions */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020060typedef enum { /* typedef fpga_type */
61 fpga_min_type, /* range check value */
62 fpga_xilinx, /* Xilinx Family) */
63 fpga_altera, /* unimplemented */
Stefano Babic3b8ac462010-06-29 11:47:48 +020064 fpga_lattice, /* Lattice family */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020065 fpga_undefined /* invalid range check value */
66} fpga_type; /* end, typedef fpga_type */
wdenk024a26b2002-08-21 21:35:08 +000067
Wolfgang Denk53677ef2008-05-20 16:00:29 +020068typedef struct { /* typedef fpga_desc */
69 fpga_type devtype; /* switch value to select sub-functions */
70 void *devdesc; /* real device descriptor */
71} fpga_desc; /* end, typedef fpga_desc */
wdenk024a26b2002-08-21 21:35:08 +000072
73
74/* root function definitions */
Wolfgang Denke6a857d2011-07-30 13:33:49 +000075extern void fpga_init(void);
76extern int fpga_add(fpga_type devtype, void *desc);
77extern int fpga_count(void);
78extern int fpga_load(int devnum, const void *buf, size_t bsize);
79extern int fpga_dump(int devnum, const void *buf, size_t bsize);
80extern int fpga_info(int devnum);
wdenk024a26b2002-08-21 21:35:08 +000081
82#endif /* _FPGA_H_ */