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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Bin Meng9c7dea62015-05-25 22:35:04 +08002/*
3 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
Bin Meng9c7dea62015-05-25 22:35:04 +08004 */
5
6#include <common.h>
Simon Glasse76187a2016-01-19 21:32:25 -07007#include <dm.h>
Bin Meng9c7dea62015-05-25 22:35:04 +08008#include <errno.h>
9#include <fdtdec.h>
Simon Glass69c2dc92020-02-06 09:54:58 -070010#include <irq.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060011#include <log.h>
Bin Meng9c7dea62015-05-25 22:35:04 +080012#include <malloc.h>
13#include <asm/io.h>
14#include <asm/irq.h>
15#include <asm/pci.h>
16#include <asm/pirq_routing.h>
Bin Meng10d569e2016-05-11 07:44:57 -070017#include <asm/tables.h>
Bin Meng9c7dea62015-05-25 22:35:04 +080018
19DECLARE_GLOBAL_DATA_PTR;
20
Bin Meng51050ff2018-06-12 01:26:46 -070021/**
22 * pirq_reg_to_linkno() - Convert a PIRQ routing register offset to link number
23 *
24 * @priv: IRQ router driver's priv data
25 * @reg: PIRQ routing register offset from the base address
26 * @return: PIRQ link number (0 for PIRQA, 1 for PIRQB, etc)
27 */
28static inline int pirq_reg_to_linkno(struct irq_router *priv, int reg)
29{
30 int linkno = 0;
31
32 if (priv->has_regmap) {
33 struct pirq_regmap *map = priv->regmap;
34 int i;
35
36 for (i = 0; i < priv->link_num; i++) {
37 if (reg - priv->link_base == map->offset) {
38 linkno = map->link;
39 break;
40 }
41 map++;
42 }
43 } else {
44 linkno = reg - priv->link_base;
45 }
46
47 return linkno;
48}
49
50/**
51 * pirq_linkno_to_reg() - Convert a PIRQ link number to routing register offset
52 *
53 * @priv: IRQ router driver's priv data
54 * @linkno: PIRQ link number (0 for PIRQA, 1 for PIRQB, etc)
55 * @return: PIRQ routing register offset from the base address
56 */
57static inline int pirq_linkno_to_reg(struct irq_router *priv, int linkno)
58{
59 int reg = 0;
60
61 if (priv->has_regmap) {
62 struct pirq_regmap *map = priv->regmap;
63 int i;
64
65 for (i = 0; i < priv->link_num; i++) {
66 if (linkno == map->link) {
67 reg = map->offset + priv->link_base;
68 break;
69 }
70 map++;
71 }
72 } else {
73 reg = linkno + priv->link_base;
74 }
75
76 return reg;
77}
78
Bin Mengb46c2082016-02-01 01:40:51 -080079bool pirq_check_irq_routed(struct udevice *dev, int link, u8 irq)
Bin Meng9c7dea62015-05-25 22:35:04 +080080{
Bin Mengb46c2082016-02-01 01:40:51 -080081 struct irq_router *priv = dev_get_priv(dev);
Bin Meng9c7dea62015-05-25 22:35:04 +080082 u8 pirq;
Bin Meng9c7dea62015-05-25 22:35:04 +080083
Bin Mengb46c2082016-02-01 01:40:51 -080084 if (priv->config == PIRQ_VIA_PCI)
Bin Meng594d0892018-06-03 19:04:23 -070085 dm_pci_read_config8(dev->parent,
Bin Meng51050ff2018-06-12 01:26:46 -070086 pirq_linkno_to_reg(priv, link), &pirq);
Bin Meng9c7dea62015-05-25 22:35:04 +080087 else
Bin Meng594d0892018-06-03 19:04:23 -070088 pirq = readb((uintptr_t)priv->ibase +
Bin Meng51050ff2018-06-12 01:26:46 -070089 pirq_linkno_to_reg(priv, link));
Bin Meng9c7dea62015-05-25 22:35:04 +080090
91 pirq &= 0xf;
92
93 /* IRQ# 0/1/2/8/13 are reserved */
94 if (pirq < 3 || pirq == 8 || pirq == 13)
95 return false;
96
97 return pirq == irq ? true : false;
98}
99
Bin Mengb46c2082016-02-01 01:40:51 -0800100int pirq_translate_link(struct udevice *dev, int link)
Bin Meng9c7dea62015-05-25 22:35:04 +0800101{
Bin Mengb46c2082016-02-01 01:40:51 -0800102 struct irq_router *priv = dev_get_priv(dev);
103
Bin Meng51050ff2018-06-12 01:26:46 -0700104 return pirq_reg_to_linkno(priv, link);
Bin Meng9c7dea62015-05-25 22:35:04 +0800105}
106
Bin Mengb46c2082016-02-01 01:40:51 -0800107void pirq_assign_irq(struct udevice *dev, int link, u8 irq)
Bin Meng9c7dea62015-05-25 22:35:04 +0800108{
Bin Mengb46c2082016-02-01 01:40:51 -0800109 struct irq_router *priv = dev_get_priv(dev);
Bin Meng9c7dea62015-05-25 22:35:04 +0800110
111 /* IRQ# 0/1/2/8/13 are reserved */
112 if (irq < 3 || irq == 8 || irq == 13)
113 return;
114
Bin Mengb46c2082016-02-01 01:40:51 -0800115 if (priv->config == PIRQ_VIA_PCI)
Bin Meng594d0892018-06-03 19:04:23 -0700116 dm_pci_write_config8(dev->parent,
Bin Meng51050ff2018-06-12 01:26:46 -0700117 pirq_linkno_to_reg(priv, link), irq);
Bin Meng9c7dea62015-05-25 22:35:04 +0800118 else
Bin Meng594d0892018-06-03 19:04:23 -0700119 writeb(irq, (uintptr_t)priv->ibase +
Bin Meng51050ff2018-06-12 01:26:46 -0700120 pirq_linkno_to_reg(priv, link));
Bin Meng9c7dea62015-05-25 22:35:04 +0800121}
122
Bin Mengdf817492015-06-23 12:18:47 +0800123static struct irq_info *check_dup_entry(struct irq_info *slot_base,
124 int entry_num, int bus, int device)
Bin Meng9c7dea62015-05-25 22:35:04 +0800125{
Bin Mengdf817492015-06-23 12:18:47 +0800126 struct irq_info *slot = slot_base;
127 int i;
Bin Meng9c7dea62015-05-25 22:35:04 +0800128
Bin Mengdf817492015-06-23 12:18:47 +0800129 for (i = 0; i < entry_num; i++) {
130 if (slot->bus == bus && slot->devfn == (device << 3))
131 break;
132 slot++;
133 }
134
135 return (i == entry_num) ? NULL : slot;
136}
137
Bin Mengb46c2082016-02-01 01:40:51 -0800138static inline void fill_irq_info(struct irq_router *priv, struct irq_info *slot,
139 int bus, int device, int pin, int pirq)
Bin Mengdf817492015-06-23 12:18:47 +0800140{
Bin Meng9c7dea62015-05-25 22:35:04 +0800141 slot->bus = bus;
Bin Meng8c38e4d2015-06-23 12:18:46 +0800142 slot->devfn = (device << 3) | 0;
Bin Meng51050ff2018-06-12 01:26:46 -0700143 slot->irq[pin - 1].link = pirq_linkno_to_reg(priv, pirq);
Bin Mengb46c2082016-02-01 01:40:51 -0800144 slot->irq[pin - 1].bitmap = priv->irq_mask;
Bin Meng9c7dea62015-05-25 22:35:04 +0800145}
146
Simon Glassb565d662016-01-19 21:32:28 -0700147static int create_pirq_routing_table(struct udevice *dev)
Bin Meng9c7dea62015-05-25 22:35:04 +0800148{
Bin Mengb46c2082016-02-01 01:40:51 -0800149 struct irq_router *priv = dev_get_priv(dev);
Bin Meng9c7dea62015-05-25 22:35:04 +0800150 const void *blob = gd->fdt_blob;
Bin Meng9c7dea62015-05-25 22:35:04 +0800151 int node;
152 int len, count;
153 const u32 *cell;
Bin Meng51050ff2018-06-12 01:26:46 -0700154 struct pirq_regmap *map;
Bin Meng9c7dea62015-05-25 22:35:04 +0800155 struct irq_routing_table *rt;
Bin Mengdf817492015-06-23 12:18:47 +0800156 struct irq_info *slot, *slot_base;
Bin Meng9c7dea62015-05-25 22:35:04 +0800157 int irq_entries = 0;
158 int i;
159 int ret;
160
Simon Glasse160f7d2017-01-17 16:52:55 -0700161 node = dev_of_offset(dev);
Bin Meng9c7dea62015-05-25 22:35:04 +0800162
163 /* extract the bdf from fdt_pci_addr */
Bin Mengb46c2082016-02-01 01:40:51 -0800164 priv->bdf = dm_pci_get_bdf(dev->parent);
Bin Meng9c7dea62015-05-25 22:35:04 +0800165
Simon Glassb02e4042016-10-02 17:59:28 -0600166 ret = fdt_stringlist_search(blob, node, "intel,pirq-config", "pci");
Bin Meng9c7dea62015-05-25 22:35:04 +0800167 if (!ret) {
Bin Mengb46c2082016-02-01 01:40:51 -0800168 priv->config = PIRQ_VIA_PCI;
Bin Meng9c7dea62015-05-25 22:35:04 +0800169 } else {
Simon Glassb02e4042016-10-02 17:59:28 -0600170 ret = fdt_stringlist_search(blob, node, "intel,pirq-config",
171 "ibase");
Bin Meng9c7dea62015-05-25 22:35:04 +0800172 if (!ret)
Bin Mengb46c2082016-02-01 01:40:51 -0800173 priv->config = PIRQ_VIA_IBASE;
Bin Meng9c7dea62015-05-25 22:35:04 +0800174 else
175 return -EINVAL;
176 }
177
Bin Mengdcec5d52018-06-12 01:26:45 -0700178 cell = fdt_getprop(blob, node, "intel,pirq-link", &len);
179 if (!cell || len != 8)
180 return -EINVAL;
181 priv->link_base = fdt_addr_to_cpu(cell[0]);
182 priv->link_num = fdt_addr_to_cpu(cell[1]);
183 if (priv->link_num > CONFIG_MAX_PIRQ_LINKS) {
184 debug("Limiting supported PIRQ link number from %d to %d\n",
185 priv->link_num, CONFIG_MAX_PIRQ_LINKS);
186 priv->link_num = CONFIG_MAX_PIRQ_LINKS;
187 }
Bin Meng9c7dea62015-05-25 22:35:04 +0800188
Bin Meng51050ff2018-06-12 01:26:46 -0700189 cell = fdt_getprop(blob, node, "intel,pirq-regmap", &len);
190 if (cell) {
191 if (len % sizeof(struct pirq_regmap))
192 return -EINVAL;
193
194 count = len / sizeof(struct pirq_regmap);
195 if (count < priv->link_num) {
196 printf("Number of pirq-regmap entires is wrong\n");
197 return -EINVAL;
198 }
199
200 count = priv->link_num;
201 priv->regmap = calloc(count, sizeof(struct pirq_regmap));
202 if (!priv->regmap)
203 return -ENOMEM;
204
205 priv->has_regmap = true;
206 map = priv->regmap;
207 for (i = 0; i < count; i++) {
208 map->link = fdt_addr_to_cpu(cell[0]);
209 map->offset = fdt_addr_to_cpu(cell[1]);
210
211 cell += sizeof(struct pirq_regmap) / sizeof(u32);
212 map++;
213 }
214 }
215
Bin Mengb46c2082016-02-01 01:40:51 -0800216 priv->irq_mask = fdtdec_get_int(blob, node,
217 "intel,pirq-mask", PIRQ_BITMAP);
Bin Meng9c7dea62015-05-25 22:35:04 +0800218
Bin Meng07ac84e2016-05-07 07:46:13 -0700219 if (IS_ENABLED(CONFIG_GENERATE_ACPI_TABLE)) {
220 /* Reserve IRQ9 for SCI */
221 priv->irq_mask &= ~(1 << 9);
222 }
223
Bin Mengb46c2082016-02-01 01:40:51 -0800224 if (priv->config == PIRQ_VIA_IBASE) {
Bin Meng9c7dea62015-05-25 22:35:04 +0800225 int ibase_off;
226
227 ibase_off = fdtdec_get_int(blob, node, "intel,ibase-offset", 0);
228 if (!ibase_off)
229 return -EINVAL;
230
231 /*
232 * Here we assume that the IBASE register has already been
233 * properly configured by U-Boot before.
234 *
235 * By 'valid' we mean:
236 * 1) a valid memory space carved within system memory space
237 * assigned to IBASE register block.
238 * 2) memory range decoding is enabled.
239 * Hence we don't do any santify test here.
240 */
Bin Meng248c4fa2016-02-01 01:40:52 -0800241 dm_pci_read_config32(dev->parent, ibase_off, &priv->ibase);
Bin Mengb46c2082016-02-01 01:40:51 -0800242 priv->ibase &= ~0xf;
Bin Meng9c7dea62015-05-25 22:35:04 +0800243 }
244
Bin Mengd4e61f52016-05-07 07:46:14 -0700245 priv->actl_8bit = fdtdec_get_bool(blob, node, "intel,actl-8bit");
246 priv->actl_addr = fdtdec_get_int(blob, node, "intel,actl-addr", 0);
247
Bin Meng9c7dea62015-05-25 22:35:04 +0800248 cell = fdt_getprop(blob, node, "intel,pirq-routing", &len);
Simon Glass9e3ff9c2015-08-10 07:05:06 -0600249 if (!cell || len % sizeof(struct pirq_routing))
Bin Meng9c7dea62015-05-25 22:35:04 +0800250 return -EINVAL;
Simon Glass9e3ff9c2015-08-10 07:05:06 -0600251 count = len / sizeof(struct pirq_routing);
Bin Meng9c7dea62015-05-25 22:35:04 +0800252
Simon Glass9e3ff9c2015-08-10 07:05:06 -0600253 rt = calloc(1, sizeof(struct irq_routing_table));
Bin Meng9c7dea62015-05-25 22:35:04 +0800254 if (!rt)
255 return -ENOMEM;
Bin Meng9c7dea62015-05-25 22:35:04 +0800256
257 /* Populate the PIRQ table fields */
258 rt->signature = PIRQ_SIGNATURE;
259 rt->version = PIRQ_VERSION;
Bin Mengb46c2082016-02-01 01:40:51 -0800260 rt->rtr_bus = PCI_BUS(priv->bdf);
261 rt->rtr_devfn = (PCI_DEV(priv->bdf) << 3) | PCI_FUNC(priv->bdf);
Bin Meng9c7dea62015-05-25 22:35:04 +0800262 rt->rtr_vendor = PCI_VENDOR_ID_INTEL;
263 rt->rtr_device = PCI_DEVICE_ID_INTEL_ICH7_31;
264
Bin Mengdf817492015-06-23 12:18:47 +0800265 slot_base = rt->slots;
Bin Meng9c7dea62015-05-25 22:35:04 +0800266
267 /* Now fill in the irq_info entries in the PIRQ table */
Simon Glass9e3ff9c2015-08-10 07:05:06 -0600268 for (i = 0; i < count;
269 i++, cell += sizeof(struct pirq_routing) / sizeof(u32)) {
Bin Meng9c7dea62015-05-25 22:35:04 +0800270 struct pirq_routing pr;
271
272 pr.bdf = fdt_addr_to_cpu(cell[0]);
273 pr.pin = fdt_addr_to_cpu(cell[1]);
274 pr.pirq = fdt_addr_to_cpu(cell[2]);
275
276 debug("irq_info %d: b.d.f %x.%x.%x INT%c PIRQ%c\n",
277 i, PCI_BUS(pr.bdf), PCI_DEV(pr.bdf),
278 PCI_FUNC(pr.bdf), 'A' + pr.pin - 1,
279 'A' + pr.pirq);
Bin Mengdf817492015-06-23 12:18:47 +0800280
281 slot = check_dup_entry(slot_base, irq_entries,
282 PCI_BUS(pr.bdf), PCI_DEV(pr.bdf));
283 if (slot) {
284 debug("found entry for bus %d device %d, ",
285 PCI_BUS(pr.bdf), PCI_DEV(pr.bdf));
286
287 if (slot->irq[pr.pin - 1].link) {
288 debug("skipping\n");
289
290 /*
291 * Sanity test on the routed PIRQ pin
292 *
293 * If they don't match, show a warning to tell
294 * there might be something wrong with the PIRQ
295 * routing information in the device tree.
296 */
297 if (slot->irq[pr.pin - 1].link !=
Bin Meng51050ff2018-06-12 01:26:46 -0700298 pirq_linkno_to_reg(priv, pr.pirq))
Bin Mengdf817492015-06-23 12:18:47 +0800299 debug("WARNING: Inconsistent PIRQ routing information\n");
Bin Mengdf817492015-06-23 12:18:47 +0800300 continue;
301 }
Simon Glass9e3ff9c2015-08-10 07:05:06 -0600302 } else {
303 slot = slot_base + irq_entries++;
Bin Mengdf817492015-06-23 12:18:47 +0800304 }
Simon Glass9e3ff9c2015-08-10 07:05:06 -0600305 debug("writing INT%c\n", 'A' + pr.pin - 1);
Bin Mengb46c2082016-02-01 01:40:51 -0800306 fill_irq_info(priv, slot, PCI_BUS(pr.bdf), PCI_DEV(pr.bdf),
307 pr.pin, pr.pirq);
Bin Meng9c7dea62015-05-25 22:35:04 +0800308 }
309
310 rt->size = irq_entries * sizeof(struct irq_info) + 32;
311
Bin Meng10d569e2016-05-11 07:44:57 -0700312 /* Fix up the table checksum */
313 rt->checksum = table_compute_checksum(rt, rt->size);
314
Simon Glass1bff8362017-01-16 07:04:16 -0700315 gd->arch.pirq_routing_table = rt;
Bin Meng9c7dea62015-05-25 22:35:04 +0800316
317 return 0;
318}
319
Bin Mengd4e61f52016-05-07 07:46:14 -0700320static void irq_enable_sci(struct udevice *dev)
321{
322 struct irq_router *priv = dev_get_priv(dev);
323
324 if (priv->actl_8bit) {
325 /* Bit7 must be turned on to enable ACPI */
326 dm_pci_write_config8(dev->parent, priv->actl_addr, 0x80);
327 } else {
328 /* Write 0 to enable SCI on IRQ9 */
329 if (priv->config == PIRQ_VIA_PCI)
330 dm_pci_write_config32(dev->parent, priv->actl_addr, 0);
331 else
Bin Meng63767072017-01-18 03:32:56 -0800332 writel(0, (uintptr_t)priv->ibase + priv->actl_addr);
Bin Mengd4e61f52016-05-07 07:46:14 -0700333 }
334}
335
Bin Mengbc728b12018-06-03 19:04:22 -0700336int irq_router_probe(struct udevice *dev)
Simon Glasse76187a2016-01-19 21:32:25 -0700337{
Simon Glass7e4be122015-08-10 07:05:08 -0600338 int ret;
339
Simon Glassb565d662016-01-19 21:32:28 -0700340 ret = create_pirq_routing_table(dev);
Simon Glass7e4be122015-08-10 07:05:08 -0600341 if (ret) {
Bin Meng9c7dea62015-05-25 22:35:04 +0800342 debug("Failed to create pirq routing table\n");
Simon Glass7e4be122015-08-10 07:05:08 -0600343 return ret;
Bin Meng9c7dea62015-05-25 22:35:04 +0800344 }
Simon Glass7e4be122015-08-10 07:05:08 -0600345 /* Route PIRQ */
Simon Glass1bff8362017-01-16 07:04:16 -0700346 pirq_route_irqs(dev, gd->arch.pirq_routing_table->slots,
347 get_irq_slot_count(gd->arch.pirq_routing_table));
Simon Glass7e4be122015-08-10 07:05:08 -0600348
Bin Mengd4e61f52016-05-07 07:46:14 -0700349 if (IS_ENABLED(CONFIG_GENERATE_ACPI_TABLE))
350 irq_enable_sci(dev);
351
Simon Glass7e4be122015-08-10 07:05:08 -0600352 return 0;
Bin Meng9c7dea62015-05-25 22:35:04 +0800353}
354
Simon Glasse76187a2016-01-19 21:32:25 -0700355static const struct udevice_id irq_router_ids[] = {
Simon Glass69c2dc92020-02-06 09:54:58 -0700356 { .compatible = "intel,irq-router", .data = X86_IRQT_BASE },
Simon Glasse76187a2016-01-19 21:32:25 -0700357 { }
358};
359
360U_BOOT_DRIVER(irq_router_drv) = {
361 .name = "intel_irq",
362 .id = UCLASS_IRQ,
363 .of_match = irq_router_ids,
364 .probe = irq_router_probe,
Bin Mengb46c2082016-02-01 01:40:51 -0800365 .priv_auto_alloc_size = sizeof(struct irq_router),
Simon Glasse76187a2016-01-19 21:32:25 -0700366};