Gitiles
Code Review Sign In
gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 0e0ef590b263927a62d399dce0cf1b7aa8dee42e / . / cpu / mcf52x2 / start.S
blob: 9a13491fbd3b3d65ea0116cf247d212a24320190 [file] [log] [blame]
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]1/*
2 * Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
3 * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <config.h>
25#include "version.h"
26
27#ifndef CONFIG_IDENT_STRING
28#define CONFIG_IDENT_STRING ""
29#endif
30
31
32#define _START _start
33#define _FAULT _fault
34
35
36#define SAVE_ALL \
37 move.w #0x2700,%sr; /* disable intrs */ \
38 subl #60,%sp; /* space for 15 regs */ \
39 moveml %d0-%d7/%a0-%a6,%sp@; \
40
41#define RESTORE_ALL \
42 moveml %sp@,%d0-%d7/%a0-%a6; \
43 addl #60,%sp; /* space for 15 regs */ \
44 rte
45
46/* If we come from a pre-loader we don't need an initial exception
47 * table.
48 */
49#if !defined(CONFIG_MONITOR_IS_IN_RAM)
50
51.text
52/*
53 * Vector table. This is used for initial platform startup.
54 * These vectors are to catch any un-intended traps.
55 */
56_vectors:
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]57 .long 0x00000000
58#ifndef CONFIG_M5282
59.long _START
60#else
61.long _start - TEXT_BASE
62#endif
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]63.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
64.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
65.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
66.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
67.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
68.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
69.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
70.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
71
72.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
73.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
74.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
75.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
76.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
77.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
78.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
79.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
80
81.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
82.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
83.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
84.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
85.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
86.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
87.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
88.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
89
90.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
91.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
92.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
93.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
94.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
95.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
96.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
97.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
98
99#endif
100
101 .text
102
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]103
104#if defined(CFG_INT_FLASH_BASE) && \
105 (defined(CONFIG_M5282) || defined(CONFIG_M5281))
106 #if (TEXT_BASE == CFG_INT_FLASH_BASE)
107 .long 0x55AA55AA,0xAA55AA55 /* CFM Backdoorkey */
108 .long 0xFFFFFFFF /* all sectors protected */
109 .long 0x00000000 /* supervisor/User restriction */
110 .long 0x00000000 /* programm/data space restriction */
111 .long 0x00000000 /* Flash security */
112 #endif
113#endif
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]114 .globl _start
115_start:
116 nop
117 nop
118 move.w #0x2700,%sr
119
stroese8c725b92004-12-16 18:09:49 +0000[diff] [blame]120#if defined(CONFIG_M5272) || defined(CONFIG_M5249)
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]121 move.l #(CFG_MBAR + 1), %d0 /* set MBAR address + valid flag */
122 move.c %d0, %MBAR
123
stroese8c725b92004-12-16 18:09:49 +0000[diff] [blame]124 /*** The 5249 has MBAR2 as well ***/
125#ifdef CFG_MBAR2
126 move.l #(CFG_MBAR2 + 1), %d0 /* Get MBAR2 address */
127 movec %d0, #0xc0e /* Set MBAR2 */
128#endif
129
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]130 move.l #(CFG_INIT_RAM_ADDR + 1), %d0
131 movec %d0, %RAMBAR0
stroese8c725b92004-12-16 18:09:49 +0000[diff] [blame]132#endif /* #if defined(CONFIG_M5272) || defined(CONFIG_M5249) */
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]133
134#ifdef CONFIG_M5282
135 /* Initialize IPSBAR */
136 move.l #(CFG_MBAR + 1), %d0 /* set IPSBAR address + valid flag */
137 move.l %d0, 0x40000000
138
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]139 /* Initialize RAMBAR1: locate SRAM and validate it */
140 move.l #(CFG_INIT_RAM_ADDR + 0x21), %d0
141 movec %d0, %RAMBAR1
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]142
143#if (TEXT_BASE == CFG_INT_FLASH_BASE)
144 /* Setup code in SRAM to initialize FLASHBAR, if start from internal Flash */
145
146 move.l #(_flashbar_setup-CFG_INT_FLASH_BASE), %a0
147 move.l #(_flashbar_setup_end-CFG_INT_FLASH_BASE), %a1
148 move.l #(CFG_INIT_RAM_ADDR), %a2
149_copy_flash:
150 move.l (%a0)+, (%a2)+
151 cmp.l %a0, %a1
152 bgt.s _copy_flash
153 jmp CFG_INIT_RAM_ADDR
154
155_flashbar_setup:
156 /* Initialize FLASHBAR: locate internal Flash and validate it */
157 move.l #(CFG_INT_FLASH_BASE + 0x21), %d0
158 movec %d0, %RAMBAR0
159 jmp _after_flashbar_copy.L /* Force jump to absolute address */
160_flashbar_setup_end:
161 nop
162_after_flashbar_copy:
163#else
164 /* Setup code to initialize FLASHBAR, if start from external Memory */
165 move.l #(CFG_INT_FLASH_BASE + 0x21), %d0
166 movec %d0, %RAMBAR0
167#endif /* (TEXT_BASE == CFG_INT_FLASH_BASE) */
168
169#endif
170 /* if we come from a pre-loader we have no exception table and
171 * therefore no VBR to set
172 */
173#if !defined(CONFIG_MONITOR_IS_IN_RAM)
174 move.l #CFG_FLASH_BASE, %d0
175 movec %d0, %VBR
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]176#endif
177
178 /* invalidate and disable cache */
179 move.l #0x01000000, %d0 /* Invalidate cache cmd */
180 movec %d0, %CACR /* Invalidate cache */
181 move.l #0, %d0
182 movec %d0, %ACR0
183 movec %d0, %ACR1
184
185 /* set stackpointer to end of internal ram to get some stackspace for the first c-code */
186 move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp
187 clr.l %sp@-
188
189 move.l #__got_start, %a5 /* put relocation table address to a5 */
190
191 bsr cpu_init_f /* run low-level CPU init code (from flash) */
192 bsr board_init_f /* run low-level board init code (from flash) */
193
194 /* board_init_f() does not return
195
196/*------------------------------------------------------------------------------*/
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]197/*
198 * void relocate_code (addr_sp, gd, addr_moni)
199 *
200 * This "function" does not return, instead it continues in RAM
201 * after relocating the monitor code.
202 *
203 * r3 = dest
204 * r4 = src
205 * r5 = length in bytes
206 * r6 = cachelinesize
207 */
208 .globl relocate_code
209relocate_code:
210 link.w %a6,#0
211 move.l 8(%a6), %sp /* set new stack pointer */
212
213 move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
214 move.l 16(%a6), %a0 /* Save copy of Destination Address */
215
216 move.l #CFG_MONITOR_BASE, %a1
217 move.l #__init_end, %a2
218 move.l %a0, %a3
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]219 /* copy the code to RAM */
2201:
221 move.l (%a1)+, (%a3)+
222 cmp.l %a1,%a2
223 bgt.s 1b
224
225/*
226 * We are done. Do not return, instead branch to second part of board
227 * initialization, now running from RAM.
228 */
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]229 move.l %a0, %a1
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]230 add.l #(in_ram - CFG_MONITOR_BASE), %a1
231 jmp (%a1)
232
233in_ram:
234
235clear_bss:
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]236 /*
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]237 * Now clear BSS segment
238 */
239 move.l %a0, %a1
240 add.l #(_sbss - CFG_MONITOR_BASE),%a1
241 move.l %a0, %d1
242 add.l #(_ebss - CFG_MONITOR_BASE),%d1
2436:
244 clr.l (%a1)+
245 cmp.l %a1,%d1
246 bgt.s 6b
247
248 /*
249 * fix got table in RAM
250 */
251 move.l %a0, %a1
252 add.l #(__got_start - CFG_MONITOR_BASE),%a1
253 move.l %a1,%a5 /* * fix got pointer register a5 */
254
255 move.l %a0, %a2
256 add.l #(__got_end - CFG_MONITOR_BASE),%a2
257
2587:
259 move.l (%a1),%d1
260 sub.l #_start,%d1
261 add.l %a0,%d1
262 move.l %d1,(%a1)+
263 cmp.l %a2, %a1
264 bne 7b
265
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]266#if defined(CONFIG_M5281) || defined(CONFIG_M5282)
267 /* patch the 3 accesspoints to 3 ichache_state */
268 /* quick and dirty */
269
270 move.l %a0,%d1
271 add.l #(icache_state - CFG_MONITOR_BASE),%d1
272 move.l %a0,%a1
273 add.l #(icache_state_access_1+2 - CFG_MONITOR_BASE),%a1
274 move.l %d1,(%a1)
275 move.l %a0,%a1
276 add.l #(icache_state_access_2+2 - CFG_MONITOR_BASE),%a1
277 move.l %d1,(%a1)
278 move.l %a0,%a1
279 add.l #(icache_state_access_3+2 - CFG_MONITOR_BASE),%a1
280 move.l %d1,(%a1)
281#endif
282
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]283 /* calculate relative jump to board_init_r in ram */
284 move.l %a0, %a1
285 add.l #(board_init_r - CFG_MONITOR_BASE), %a1
286
287 /* set parameters for board_init_r */
288 move.l %a0,-(%sp) /* dest_addr */
289 move.l %d0,-(%sp) /* gd */
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]290 #if defined(DEBUG) && (TEXT_BASE != CFG_INT_FLASH_BASE) && \
291 defined(CFG_HALT_BEFOR_RAM_JUMP)
292 halt
293 #endif
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]294 jsr (%a1)
295
296/*------------------------------------------------------------------------------*/
297/* exception code */
298 .globl _fault
299_fault:
300 jmp _fault
301
302 .globl _exc_handler
303_exc_handler:
304 SAVE_ALL
305 movel %sp,%sp@-
306 bsr exc_handler
307 addql #4,%sp
308 RESTORE_ALL
309
310 .globl _int_handler
311_int_handler:
312 SAVE_ALL
313 movel %sp,%sp@-
314 bsr int_handler
315 addql #4,%sp
316 RESTORE_ALL
317
318/*------------------------------------------------------------------------------*/
319/* cache functions */
320#ifdef CONFIG_M5272
321 .globl icache_enable
322icache_enable:
323 move.l #0x01000000, %d0 /* Invalidate cache cmd */
324 movec %d0, %CACR /* Invalidate cache */
325 move.l #0x0000c000, %d0 /* Setup cache mask */
326 movec %d0, %ACR0 /* Enable cache */
327 move.l #0xff00c000, %d0 /* Setup cache mask */
328 movec %d0, %ACR1 /* Enable cache */
329 move.l #0x80000100, %d0 /* Setup cache mask */
330 movec %d0, %CACR /* Enable cache */
331 moveq #1, %d0
332 move.l %d0, icache_state
333 rts
334#endif
335
336#ifdef CONFIG_M5282
337 .globl icache_enable
338icache_enable:
339 move.l #0x01000000, %d0 /* Invalidate cache cmd */
340 movec %d0, %CACR /* Invalidate cache */
341 move.l #0x0000c000, %d0 /* Setup cache mask */
342 movec %d0, %ACR0 /* Enable cache */
343 move.l #0xff00c000, %d0 /* Setup cache mask */
344 movec %d0, %ACR1 /* Enable cache */
345 move.l #0x80400100, %d0 /* Setup cache mask, data cache disabel*/
346 movec %d0, %CACR /* Enable cache */
347 moveq #1, %d0
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]348icache_state_access_1:
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]349 move.l %d0, icache_state
350 rts
351#endif
352
stroese8c725b92004-12-16 18:09:49 +0000[diff] [blame]353#ifdef CONFIG_M5249
354 .globl icache_enable
355icache_enable:
356 /*
357 * Note: The 5249 Documentation doesn't give a bit position for CINV!
358 * From the 5272 and the 5307 documentation, I have deduced that it is
359 * probably CACR[24]. Should someone say something to Motorola?
360 * ~Jeremy
361 */
362 move.l #0x01000000, %d0 /* Invalidate whole cache */
363 move.c %d0,%CACR
364 move.l #0xff00c000, %d0 /* Set FLASH cachable: always match (SM=0b10) */
365 move.c %d0, %ACR0
366 move.l #0x0000c000, %d0 /* Set SDRAM cachable: always match (SM=0b10) */
367 move.c %d0, %ACR1
368 move.l #0x90000200, %d0 /* Set cache enable cmd */
369 move.c %d0,%CACR
370 moveq #1, %d0
371 move.l %d0, icache_state
372 rts
373#endif
374
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]375 .globl icache_disable
376icache_disable:
377 move.l #0x00000100, %d0 /* Setup cache mask */
378 movec %d0, %CACR /* Enable cache */
379 clr.l %d0 /* Setup cache mask */
380 movec %d0, %ACR0 /* Enable cache */
381 movec %d0, %ACR1 /* Enable cache */
382 moveq #0, %d0
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]383icache_state_access_2:
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]384 move.l %d0, icache_state
385 rts
386
387 .globl icache_status
388icache_status:
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]389icache_state_access_3:
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]390 move.l icache_state, %d0
391 rts
392
393 .data
394icache_state:
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]395 .long 0 /* cache is diabled on inirialization */
stroese8c725b92004-12-16 18:09:49 +0000[diff] [blame]396
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]397/*------------------------------------------------------------------------------*/
398
399 .globl version_string
400version_string:
401 .ascii U_BOOT_VERSION
402 .ascii " (", __DATE__, " - ", __TIME__, ")"
403 .ascii CONFIG_IDENT_STRING, "\0"