Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 2 | /* |
| 3 | * Configuation settings for the Freescale MCF5329 FireEngine board. |
| 4 | * |
| 5 | * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. |
| 6 | * TsiChung Liew (Tsi-Chung.Liew@freescale.com) |
TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | /* |
| 10 | * board/config.h - configuration options, board specific |
| 11 | */ |
| 12 | |
| 13 | #ifndef _M5235EVB_H |
| 14 | #define _M5235EVB_H |
| 15 | |
| 16 | /* |
| 17 | * High Level Configuration Options |
| 18 | * (easy to change) |
| 19 | */ |
TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 20 | |
Tom Rini | 65cc0e2 | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 21 | #define CFG_SYS_UART_PORT (0) |
TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 22 | |
TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 23 | /* I2C */ |
Tom Rini | 65cc0e2 | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 24 | #define CFG_SYS_I2C_PINMUX_REG (gpio->par_qspi) |
| 25 | #define CFG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK) |
| 26 | #define CFG_SYS_I2C_PINMUX_SET (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA) |
TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 27 | |
Patrick Delaunay | ff07cc9 | 2021-10-04 11:59:50 +0200 | [diff] [blame] | 28 | /* this must be included AFTER the definition of CONFIG COMMANDS (if any) */ |
TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 29 | |
Tom Rini | 0613c36 | 2022-12-04 10:03:50 -0500 | [diff] [blame] | 30 | #define CFG_EXTRA_ENV_SETTINGS \ |
TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 31 | "netdev=eth0\0" \ |
| 32 | "loadaddr=10000\0" \ |
| 33 | "u-boot=u-boot.bin\0" \ |
| 34 | "load=tftp ${loadaddr) ${u-boot}\0" \ |
| 35 | "upd=run load; run prog\0" \ |
| 36 | "prog=prot off ffe00000 ffe3ffff;" \ |
| 37 | "era ffe00000 ffe3ffff;" \ |
| 38 | "cp.b ${loadaddr} ffe00000 ${filesize};"\ |
| 39 | "save\0" \ |
| 40 | "" |
| 41 | |
Tom Rini | 7c5c137 | 2022-12-04 10:13:37 -0500 | [diff] [blame] | 42 | #define CFG_PRAM 512 /* 512 KB */ |
TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 43 | |
Tom Rini | 65cc0e2 | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 44 | #define CFG_SYS_CLK 75000000 |
| 45 | #define CFG_SYS_CPU_CLK CFG_SYS_CLK * 2 |
TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 46 | |
Tom Rini | 65cc0e2 | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 47 | #define CFG_SYS_MBAR 0x40000000 |
TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 48 | |
| 49 | /* |
| 50 | * Low Level Configuration Settings |
| 51 | * (address mappings, register initial values, etc.) |
| 52 | * You should know what you are doing if you make changes here. |
| 53 | */ |
| 54 | /*----------------------------------------------------------------------- |
| 55 | * Definitions for initial stack pointer and data area (in DPRAM) |
| 56 | */ |
Tom Rini | 65cc0e2 | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 57 | #define CFG_SYS_INIT_RAM_ADDR 0x20000000 |
| 58 | #define CFG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ |
| 59 | #define CFG_SYS_INIT_RAM_CTRL 0x21 |
TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 60 | |
| 61 | /*----------------------------------------------------------------------- |
| 62 | * Start addresses for the final memory configuration |
| 63 | * (Set up by the startup code) |
Tom Rini | aa6e94d | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 64 | * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0 |
TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 65 | */ |
Tom Rini | aa6e94d | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 66 | #define CFG_SYS_SDRAM_BASE 0x00000000 |
| 67 | #define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ |
TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 68 | |
TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 69 | /* |
| 70 | * For booting Linux, the board info and command line data |
| 71 | * have to be in the first 8 MB of memory, since this is |
| 72 | * the maximum mapped by the Linux kernel during initialization ?? |
| 73 | */ |
| 74 | /* Initial Memory map for Linux */ |
Tom Rini | 65cc0e2 | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 75 | #define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) |
TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 76 | |
| 77 | /*----------------------------------------------------------------------- |
| 78 | * FLASH organization |
| 79 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 80 | #ifdef CONFIG_SYS_FLASH_CFI |
Tom Rini | 65cc0e2 | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 81 | # define CFG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ |
TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 82 | #endif |
| 83 | |
Tom Rini | 65cc0e2 | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 84 | #define CFG_SYS_FLASH_BASE (CFG_SYS_CS0_BASE) |
TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 85 | |
| 86 | /* Configuration for environment |
| 87 | * Environment is embedded in u-boot in the second sector of the flash |
| 88 | */ |
angelo@sysam.it | 5296cb1 | 2015-03-29 22:54:16 +0200 | [diff] [blame] | 89 | |
| 90 | #define LDS_BOARD_TEXT \ |
| 91 | . = DEFINED(env_offset) ? env_offset : .; \ |
Simon Glass | 0649cd0 | 2017-08-03 12:21:49 -0600 | [diff] [blame] | 92 | env/embedded.o(.text); |
angelo@sysam.it | 5296cb1 | 2015-03-29 22:54:16 +0200 | [diff] [blame] | 93 | |
TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 94 | /*----------------------------------------------------------------------- |
| 95 | * Cache Configuration |
| 96 | */ |
TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 97 | |
Tom Rini | 65cc0e2 | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 98 | #define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ |
| 99 | CFG_SYS_INIT_RAM_SIZE - 8) |
| 100 | #define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ |
| 101 | CFG_SYS_INIT_RAM_SIZE - 4) |
| 102 | #define CFG_SYS_ICACHE_INV (CF_CACR_CINV) |
| 103 | #define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ |
Tom Rini | aa6e94d | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 104 | CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ |
TsiChung Liew | dd9f054 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 105 | CF_ACR_EN | CF_ACR_SM_ALL) |
Tom Rini | 65cc0e2 | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 106 | #define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ |
TsiChung Liew | dd9f054 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 107 | CF_CACR_CEIB | CF_CACR_DCM | \ |
| 108 | CF_CACR_EUSP) |
| 109 | |
TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 110 | /*----------------------------------------------------------------------- |
| 111 | * Chipselect bank definitions |
| 112 | */ |
| 113 | /* |
| 114 | * CS0 - NOR Flash 1, 2, 4, or 8MB |
| 115 | * CS1 - Available |
| 116 | * CS2 - Available |
| 117 | * CS3 - Available |
| 118 | * CS4 - Available |
| 119 | * CS5 - Available |
| 120 | * CS6 - Available |
| 121 | * CS7 - Available |
| 122 | */ |
Tom Rini | d4a2c40 | 2022-03-24 17:18:04 -0400 | [diff] [blame] | 123 | #ifdef CONFIG_NORFLASH_PS32BIT |
Tom Rini | 65cc0e2 | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 124 | # define CFG_SYS_CS0_BASE 0xFFC00000 |
| 125 | # define CFG_SYS_CS0_MASK 0x003f0001 |
| 126 | # define CFG_SYS_CS0_CTRL 0x00001D00 |
TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 127 | #else |
Tom Rini | 65cc0e2 | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 128 | # define CFG_SYS_CS0_BASE 0xFFE00000 |
| 129 | # define CFG_SYS_CS0_MASK 0x001f0001 |
| 130 | # define CFG_SYS_CS0_CTRL 0x00001D80 |
TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 131 | #endif |
| 132 | |
| 133 | #endif /* _M5329EVB_H */ |