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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Nobuhiro Iwamatsu6a994e52014-11-06 15:39:28 +09002/*
3 * board/renesas/gose/gose.c
4 *
5 * Copyright (C) 2014 Renesas Electronics Corporation
Nobuhiro Iwamatsu6a994e52014-11-06 15:39:28 +09006 */
7
8#include <common.h>
Tom Rini2f8a6db2021-12-14 13:36:40 -05009#include <clock_legacy.h>
Simon Glass9a3b4ce2019-12-28 10:45:01 -070010#include <cpu_func.h>
Simon Glass7b51b572019-08-01 09:46:52 -060011#include <env.h>
Simon Glassdb41d652019-12-28 10:45:07 -070012#include <hang.h>
Simon Glass691d7192020-05-10 11:40:02 -060013#include <init.h>
Nobuhiro Iwamatsu6a994e52014-11-06 15:39:28 +090014#include <malloc.h>
Nobuhiro Iwamatsu9d86e482014-12-09 11:24:01 +090015#include <dm.h>
Simon Glass401d1c42020-10-30 21:38:53 -060016#include <asm/global_data.h>
Nobuhiro Iwamatsu9d86e482014-12-09 11:24:01 +090017#include <dm/platform_data/serial_sh.h>
Simon Glassf3998fd2019-08-02 09:44:25 -060018#include <env_internal.h>
Nobuhiro Iwamatsu6a994e52014-11-06 15:39:28 +090019#include <asm/processor.h>
20#include <asm/mach-types.h>
21#include <asm/io.h>
Simon Glasscd93d622020-05-10 11:40:13 -060022#include <linux/bitops.h>
Simon Glassc05ed002020-05-10 11:40:11 -060023#include <linux/delay.h>
Masahiro Yamada1221ce42016-09-21 11:28:55 +090024#include <linux/errno.h>
Nobuhiro Iwamatsu6a994e52014-11-06 15:39:28 +090025#include <asm/arch/sys_proto.h>
26#include <asm/gpio.h>
27#include <asm/arch/rmobile.h>
Nobuhiro Iwamatsu44e1eeb2014-12-02 16:52:19 +090028#include <asm/arch/rcar-mstp.h>
Nobuhiro Iwamatsue2abab62014-11-12 11:29:39 +090029#include <asm/arch/sh_sdhi.h>
Nobuhiro Iwamatsuf0261242014-11-06 15:42:24 +090030#include <netdev.h>
31#include <miiphy.h>
Nobuhiro Iwamatsu6a994e52014-11-06 15:39:28 +090032#include <i2c.h>
33#include "qos.h"
34
35DECLARE_GLOBAL_DATA_PTR;
36
37#define CLK2MHZ(clk) (clk / 1000 / 1000)
38void s_init(void)
39{
40 struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
41 struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
42 u32 stc;
43
44 /* Watchdog init */
45 writel(0xA5A5A500, &rwdt->rwtcsra);
46 writel(0xA5A5A500, &swdt->swtcsra);
47
48 /* CPU frequency setting. Set to 1.5GHz */
Tom Rini2f8a6db2021-12-14 13:36:40 -050049 stc = ((1500 / CLK2MHZ(get_board_sys_clk())) - 1) << PLL0_STC_BIT;
Nobuhiro Iwamatsu6a994e52014-11-06 15:39:28 +090050 clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
51
52 /* QoS */
53 qos_init();
54}
55
Marek Vasut49aefe32018-04-23 20:24:10 +020056#define TMU0_MSTP125 BIT(25)
Nobuhiro Iwamatsue2abab62014-11-12 11:29:39 +090057
58#define SD1CKCR 0xE6150078
59#define SD2CKCR 0xE615026C
60#define SD_97500KHZ 0x7
61
Nobuhiro Iwamatsu6a994e52014-11-06 15:39:28 +090062int board_early_init_f(void)
63{
Nobuhiro Iwamatsu6a994e52014-11-06 15:39:28 +090064 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
65
Marek Vasut49aefe32018-04-23 20:24:10 +020066 /*
67 * SD0 clock is set to 97.5MHz by default.
68 * Set SD1 and SD2 to the 97.5MHz as well.
69 */
Nobuhiro Iwamatsue2abab62014-11-12 11:29:39 +090070 writel(SD_97500KHZ, SD1CKCR);
71 writel(SD_97500KHZ, SD2CKCR);
72
Nobuhiro Iwamatsu6a994e52014-11-06 15:39:28 +090073 return 0;
74}
75
Marek Vasut49aefe32018-04-23 20:24:10 +020076#define ETHERNET_PHY_RESET 176 /* GPIO 5 22 */
Nobuhiro Iwamatsuf0261242014-11-06 15:42:24 +090077
Nobuhiro Iwamatsu6a994e52014-11-06 15:39:28 +090078int board_init(void)
79{
80 /* adress of boot parameters */
Tom Riniaa6e94d2022-11-16 13:10:37 -050081 gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
Nobuhiro Iwamatsu6a994e52014-11-06 15:39:28 +090082
Marek Vasut49aefe32018-04-23 20:24:10 +020083 /* Force ethernet PHY out of reset */
84 gpio_request(ETHERNET_PHY_RESET, "phy_reset");
85 gpio_direction_output(ETHERNET_PHY_RESET, 0);
86 mdelay(10);
87 gpio_direction_output(ETHERNET_PHY_RESET, 1);
Nobuhiro Iwamatsuf0261242014-11-06 15:42:24 +090088
Nobuhiro Iwamatsu6a994e52014-11-06 15:39:28 +090089 return 0;
90}
91
Nobuhiro Iwamatsu6a994e52014-11-06 15:39:28 +090092int dram_init(void)
93{
Siva Durga Prasad Paladugu12308b12018-07-16 15:56:11 +053094 if (fdtdec_setup_mem_size_base() != 0)
Marek Vasut49aefe32018-04-23 20:24:10 +020095 return -EINVAL;
96
97 return 0;
98}
99
100int dram_init_banksize(void)
101{
102 fdtdec_setup_memory_banksize();
103
104 return 0;
105}
106
107/* KSZ8041RNLI */
108#define PHY_CONTROL1 0x1E
Marek Vasut4bbd4642019-03-30 07:05:09 +0100109#define PHY_LED_MODE 0xC000
Marek Vasut49aefe32018-04-23 20:24:10 +0200110#define PHY_LED_MODE_ACK 0x4000
111int board_phy_config(struct phy_device *phydev)
112{
113 int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
114 ret &= ~PHY_LED_MODE;
115 ret |= PHY_LED_MODE_ACK;
116 ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
Nobuhiro Iwamatsu6a994e52014-11-06 15:39:28 +0900117
118 return 0;
119}
120
Harald Seiler35b65dd2020-12-15 16:47:52 +0100121void reset_cpu(void)
Nobuhiro Iwamatsu6a994e52014-11-06 15:39:28 +0900122{
Marek Vasut49aefe32018-04-23 20:24:10 +0200123 struct udevice *dev;
124 const u8 pmic_bus = 6;
125 const u8 pmic_addr = 0x58;
126 u8 data;
127 int ret;
Nobuhiro Iwamatsu6a994e52014-11-06 15:39:28 +0900128
Marek Vasut49aefe32018-04-23 20:24:10 +0200129 ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev);
130 if (ret)
131 hang();
132
133 ret = dm_i2c_read(dev, 0x13, &data, 1);
134 if (ret)
135 hang();
136
137 data |= BIT(1);
138
139 ret = dm_i2c_write(dev, 0x13, &data, 1);
140 if (ret)
141 hang();
Nobuhiro Iwamatsu6a994e52014-11-06 15:39:28 +0900142}
Nobuhiro Iwamatsu9d86e482014-12-09 11:24:01 +0900143
Marek Vasut49aefe32018-04-23 20:24:10 +0200144enum env_location env_get_location(enum env_operation op, int prio)
145{
146 const u32 load_magic = 0xb33fc0de;
Nobuhiro Iwamatsu9d86e482014-12-09 11:24:01 +0900147
Marek Vasut49aefe32018-04-23 20:24:10 +0200148 /* Block environment access if loaded using JTAG */
149 if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) &&
150 (op != ENVOP_INIT))
151 return ENVL_UNKNOWN;
152
153 if (prio)
154 return ENVL_UNKNOWN;
155
156 return ENVL_SPI_FLASH;
157}