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Wolfgang Denk6cb142f2006-03-12 02:12:27 +01001/*
2 * U-boot - psd4256.h
3 *
Aubrey Li155fd762007-04-05 18:31:18 +08004 * Copyright (c) 2005-2007 Analog Devices Inc.
Wolfgang Denk6cb142f2006-03-12 02:12:27 +01005 *
6 * (C) Copyright 2000-2004
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02009 * SPDX-License-Identifier: GPL-2.0+
Wolfgang Denk6cb142f2006-03-12 02:12:27 +010010 */
11
12/*
13 * Flash A/B Port A configuration registers.
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020014 * Addresses are offset values to CONFIG_SYS_FLASH1_BASE
15 * for Flash A and CONFIG_SYS_FLASH2_BASE for Flash B.
Wolfgang Denk6cb142f2006-03-12 02:12:27 +010016 */
17
18#define PSD_PORTA_DIN 0x070000
19#define PSD_PORTA_DOUT 0x070004
20#define PSD_PORTA_DIR 0x070006
21
22/*
23 * Flash A/B Port B configuration registers
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020024 * Addresses are offset values to CONFIG_SYS_FLASH1_BASE
25 * for Flash A and CONFIG_SYS_FLASH2_BASE for Flash B.
Wolfgang Denk6cb142f2006-03-12 02:12:27 +010026 */
27
28#define PSD_PORTB_DIN 0x070001
29#define PSD_PORTB_DOUT 0x070005
30#define PSD_PORTB_DIR 0x070007
31
32/*
33 * Flash A Port A Bit definitions
34 */
35
Aubrey.Li3f0606a2007-03-09 13:38:44 +080036#define PSDA_PPICLK1 0x20 /* PPI Clock select bit 1 */
37#define PSDA_PPICLK0 0x10 /* PPI Clock select bit 0 */
38#define PSDA_VDEC_RST 0x08 /* Video decoder reset, 0 = RESET */
39#define PSDA_VENC_RST 0x04 /* Video encoder reset, 0 = RESET */
40#define PSDA_CODEC_RST 0x01 /* Codec reset, 0 = RESET */
Wolfgang Denk6cb142f2006-03-12 02:12:27 +010041
42/*
43 * Flash A Port B Bit definitions
44 */
45
Aubrey.Li3f0606a2007-03-09 13:38:44 +080046#define PSDA_LED9 0x20 /* LED 9, 1 = LED ON */
47#define PSDA_LED8 0x10 /* LED 8, 1 = LED ON */
48#define PSDA_LED7 0x08 /* LED 7, 1 = LED ON */
49#define PSDA_LED6 0x04 /* LED 6, 1 = LED ON */
50#define PSDA_LED5 0x02 /* LED 5, 1 = LED ON */
51#define PSDA_LED4 0x01 /* LED 4, 1 = LED ON */