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wdenk945af8d2003-07-16 21:53:01 +00001/*
2 * (C) Copyright 2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <mpc5xxx.h>
wdenk96e48cf2003-08-05 18:22:44 +000026#include <pci.h>
wdenk945af8d2003-07-16 21:53:01 +000027
wdenkd94f92c2003-08-28 09:41:22 +000028#ifndef CFG_RAMBOOT
wdenke0ac62d2003-08-17 18:55:18 +000029static void sdram_start (int hi_addr)
30{
31 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
32
wdenkb2001f22003-12-20 22:45:10 +000033#ifdef CONFIG_MPC5200_DDR
34 /* unlock mode register */
35 *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xf05f0f00 | hi_addr_bit;
36 /* precharge all banks */
37 *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xf05f0f02 | hi_addr_bit;
38 /* set mode register: extended mode */
39 *(vu_long *)MPC5XXX_SDRAM_MODE = 0x40090000;
40 /* set mode register: reset DLL */
41 *(vu_long *)MPC5XXX_SDRAM_MODE = 0x058d0000;
42 /* precharge all banks */
43 *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xf05f0f02 | hi_addr_bit;
44 /* auto refresh */
45 *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xf05f0f04 | hi_addr_bit;
46 /* set mode register */
47 *(vu_long *)MPC5XXX_SDRAM_MODE = 0x018d0000;
48 /* normal operation */
49 *(vu_long *)MPC5XXX_SDRAM_CTRL = 0x705f0f00 | hi_addr_bit;
50#else
wdenke0ac62d2003-08-17 18:55:18 +000051 /* unlock mode register */
52 *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0000 | hi_addr_bit;
53 /* precharge all banks */
54 *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0002 | hi_addr_bit;
55 /* set mode register */
56#if defined(CONFIG_MPC5200)
wdenkf8d813e2004-03-02 14:05:39 +000057 *(vu_long *)MPC5XXX_SDRAM_MODE = 0x00cd0000;
wdenke0ac62d2003-08-17 18:55:18 +000058#elif defined(CONFIG_MGT5100)
59 *(vu_long *)MPC5XXX_SDRAM_MODE = 0x008d0000;
60#endif
wdenkf8d813e2004-03-02 14:05:39 +000061 /* auto refresh */
62 *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0004 | hi_addr_bit;
wdenke0ac62d2003-08-17 18:55:18 +000063 /* auto refresh */
64 *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0004 | hi_addr_bit;
65 /* set mode register */
wdenkf8d813e2004-03-02 14:05:39 +000066 *(vu_long *)MPC5XXX_SDRAM_MODE = 0x00cd0000;
wdenke0ac62d2003-08-17 18:55:18 +000067 /* normal operation */
68 *(vu_long *)MPC5XXX_SDRAM_CTRL = 0x504f0000 | hi_addr_bit;
wdenkb2001f22003-12-20 22:45:10 +000069#endif
wdenke0ac62d2003-08-17 18:55:18 +000070}
wdenkd94f92c2003-08-28 09:41:22 +000071#endif
wdenke0ac62d2003-08-17 18:55:18 +000072
wdenk945af8d2003-07-16 21:53:01 +000073long int initdram (int board_type)
74{
wdenkd94f92c2003-08-28 09:41:22 +000075 ulong dramsize = 0;
wdenkb2001f22003-12-20 22:45:10 +000076#ifdef CONFIG_MPC5200_DDR
77 ulong dramsize2 = 0;
78#endif
wdenk945af8d2003-07-16 21:53:01 +000079#ifndef CFG_RAMBOOT
wdenkd94f92c2003-08-28 09:41:22 +000080 ulong test1, test2;
81
wdenk945af8d2003-07-16 21:53:01 +000082 /* configure SDRAM start/end */
83#if defined(CONFIG_MPC5200)
wdenke0ac62d2003-08-17 18:55:18 +000084 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
85 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
wdenk945af8d2003-07-16 21:53:01 +000086
wdenkb2001f22003-12-20 22:45:10 +000087#ifdef CONFIG_MPC5200_DDR
88 /* setup config registers */
89 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = 0x73722930;
90 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = 0x47770000;
wdenkd4ca31c2004-01-02 14:00:00 +000091
wdenkb2001f22003-12-20 22:45:10 +000092 /* set tap delay to 0x10 */
93 *(vu_long *)MPC5XXX_CDM_PORCFG = 0x10000000;
94#else
wdenk945af8d2003-07-16 21:53:01 +000095 /* setup config registers */
wdenkf8d813e2004-03-02 14:05:39 +000096 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = 0xd2322800;
97 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = 0x8ad70000;
wdenkb2001f22003-12-20 22:45:10 +000098#endif
wdenk945af8d2003-07-16 21:53:01 +000099
wdenk945af8d2003-07-16 21:53:01 +0000100#elif defined(CONFIG_MGT5100)
101 *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
wdenke0ac62d2003-08-17 18:55:18 +0000102 *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
wdenk945af8d2003-07-16 21:53:01 +0000103 *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
104
105 /* setup config registers */
106 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = 0xc2222600;
107 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = 0x88b70004;
108
109 /* address select register */
110 *(vu_long *)MPC5XXX_SDRAM_XLBSEL = 0x03000000;
wdenk945af8d2003-07-16 21:53:01 +0000111#endif
wdenke0ac62d2003-08-17 18:55:18 +0000112 sdram_start(0);
wdenkc83bf6a2004-01-06 22:38:14 +0000113 test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
wdenke0ac62d2003-08-17 18:55:18 +0000114 sdram_start(1);
wdenkc83bf6a2004-01-06 22:38:14 +0000115 test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
wdenke0ac62d2003-08-17 18:55:18 +0000116 if (test1 > test2) {
117 sdram_start(0);
118 dramsize = test1;
119 } else {
120 dramsize = test2;
121 }
122#if defined(CONFIG_MPC5200)
123 *(vu_long *)MPC5XXX_SDRAM_CS0CFG =
124 (0x13 + __builtin_ffs(dramsize >> 20) - 1);
wdenkb2001f22003-12-20 22:45:10 +0000125#ifdef CONFIG_MPC5200_DDR
126 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
127 sdram_start(0);
wdenkc83bf6a2004-01-06 22:38:14 +0000128 test1 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
wdenkb2001f22003-12-20 22:45:10 +0000129 sdram_start(1);
wdenkc83bf6a2004-01-06 22:38:14 +0000130 test2 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
wdenkb2001f22003-12-20 22:45:10 +0000131 if (test1 > test2) {
132 sdram_start(0);
133 dramsize2 = test1;
134 } else {
135 dramsize2 = test2;
136 }
137 *(vu_long *)MPC5XXX_SDRAM_CS1CFG =
138 dramsize + (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
139#else
wdenke0ac62d2003-08-17 18:55:18 +0000140 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
wdenkb2001f22003-12-20 22:45:10 +0000141#endif
wdenke0ac62d2003-08-17 18:55:18 +0000142#elif defined(CONFIG_MGT5100)
143 *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
144#endif
145
wdenk5cf9da42003-11-07 13:42:26 +0000146#else /* CFG_RAMBOOT */
wdenk945af8d2003-07-16 21:53:01 +0000147#ifdef CONFIG_MGT5100
148 *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
wdenkd94f92c2003-08-28 09:41:22 +0000149 dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
150#else
151 dramsize = ((1 << (*(vu_long *)MPC5XXX_SDRAM_CS0CFG - 0x13)) << 20);
wdenkb2001f22003-12-20 22:45:10 +0000152#ifdef CONFIG_MPC5200_DDR
153 dramsize2 = ((1 << (*(vu_long *)MPC5XXX_SDRAM_CS1CFG - 0x13)) << 20);
154#endif
wdenk945af8d2003-07-16 21:53:01 +0000155#endif
wdenkd94f92c2003-08-28 09:41:22 +0000156#endif /* CFG_RAMBOOT */
wdenkb2001f22003-12-20 22:45:10 +0000157
158#ifdef CONFIG_MPC5200_DDR
159 dramsize += dramsize2;
160#endif
wdenk945af8d2003-07-16 21:53:01 +0000161 /* return total ram size */
wdenke0ac62d2003-08-17 18:55:18 +0000162 return dramsize;
wdenk945af8d2003-07-16 21:53:01 +0000163}
164
165int checkboard (void)
166{
167#if defined(CONFIG_MPC5200)
168 puts ("Board: Motorola MPC5200 (IceCube)\n");
169#elif defined(CONFIG_MGT5100)
170 puts ("Board: Motorola MGT5100 (IceCube)\n");
171#endif
172 return 0;
173}
174
175void flash_preinit(void)
176{
177 /*
178 * Now, when we are in RAM, enable flash write
179 * access for detection process.
180 * Note that CS_BOOT cannot be cleared when
181 * executing in flash.
182 */
183#if defined(CONFIG_MGT5100)
184 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
185 *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
186#endif
187 *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
188}
wdenk96e48cf2003-08-05 18:22:44 +0000189
wdenk7152b1d2003-09-05 23:19:14 +0000190void flash_afterinit(ulong size)
191{
192 if (size == 0x800000) { /* adjust mapping */
wdenk42d1f032003-10-15 23:53:47 +0000193 *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
wdenk7152b1d2003-09-05 23:19:14 +0000194 START_REG(CFG_BOOTCS_START | size);
wdenk42d1f032003-10-15 23:53:47 +0000195 *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
wdenk7152b1d2003-09-05 23:19:14 +0000196 STOP_REG(CFG_BOOTCS_START | size, size);
197 }
198}
199
wdenk96e48cf2003-08-05 18:22:44 +0000200#ifdef CONFIG_PCI
201static struct pci_controller hose;
202
203extern void pci_mpc5xxx_init(struct pci_controller *);
204
205void pci_init_board(void)
206{
207 pci_mpc5xxx_init(&hose);
208}
209#endif
wdenkc3f9d492004-03-14 00:59:59 +0000210
211#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
212
wdenk4d13cba2004-03-14 14:09:05 +0000213#define GPIO_PSC1_4 0x01000000UL
wdenkc3f9d492004-03-14 00:59:59 +0000214
215void init_ide_reset (void)
216{
wdenk4d13cba2004-03-14 14:09:05 +0000217 debug ("init_ide_reset\n");
wdenk42dfe7a2004-03-14 22:25:36 +0000218
wdenkc3f9d492004-03-14 00:59:59 +0000219 /* Configure PSC1_4 as GPIO output for ATA reset */
wdenkc3f9d492004-03-14 00:59:59 +0000220 *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
wdenk4d13cba2004-03-14 14:09:05 +0000221 *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
wdenkc3f9d492004-03-14 00:59:59 +0000222}
223
224void ide_set_reset (int idereset)
225{
wdenk4d13cba2004-03-14 14:09:05 +0000226 debug ("ide_reset(%d)\n", idereset);
227
wdenkc3f9d492004-03-14 00:59:59 +0000228 if (idereset) {
229 *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4;
230 } else {
wdenk4d13cba2004-03-14 14:09:05 +0000231 *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4;
wdenkc3f9d492004-03-14 00:59:59 +0000232 }
233}
234#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */