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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Heiko Schocherde044362008-11-20 09:57:47 +01002/*
3 * Copyright (C) 2006 Freescale Semiconductor, Inc.
4 * Dave Liu <daveliu@freescale.com>
5 *
6 * Copyright (C) 2007 Logic Product Development, Inc.
7 * Peter Barada <peterb@logicpd.com>
8 *
9 * Copyright (C) 2007 MontaVista Software, Inc.
10 * Anton Vorontsov <avorontsov@ru.mvista.com>
11 *
Heiko Schocher62ddcf02010-02-18 08:08:25 +010012 * (C) Copyright 2008 - 2010
Heiko Schocherde044362008-11-20 09:57:47 +010013 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
Heiko Schocherde044362008-11-20 09:57:47 +010014 */
15
16#include <common.h>
Simon Glass9fb625c2019-08-01 09:46:51 -060017#include <env.h>
Simon Glass807765b2019-12-28 10:44:54 -070018#include <fdt_support.h>
Simon Glass52559322019-11-14 12:57:46 -070019#include <init.h>
Heiko Schocherde044362008-11-20 09:57:47 +010020#include <ioports.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060021#include <log.h>
Heiko Schocherde044362008-11-20 09:57:47 +010022#include <mpc83xx.h>
23#include <i2c.h>
24#include <miiphy.h>
Simon Glass401d1c42020-10-30 21:38:53 -060025#include <asm/global_data.h>
Heiko Schocherde044362008-11-20 09:57:47 +010026#include <asm/io.h>
27#include <asm/mmu.h>
Heiko Schocher1e7ed252009-02-24 11:30:48 +010028#include <asm/processor.h>
Heiko Schocherde044362008-11-20 09:57:47 +010029#include <pci.h>
Simon Glassc05ed002020-05-10 11:40:11 -060030#include <linux/delay.h>
Masahiro Yamadab08c8c42018-03-05 01:20:11 +090031#include <linux/libfdt.h>
Thomas Herzmann95209b62012-05-04 10:55:56 +020032#include <post.h>
Heiko Schocherde044362008-11-20 09:57:47 +010033
Heiko Schocher210c8c02008-11-21 08:29:40 +010034#include "../common/common.h"
35
Simon Glass088454c2017-03-31 08:40:25 -060036DECLARE_GLOBAL_DATA_PTR;
37
Valentin Longchampf32b3d32015-02-10 17:10:16 +010038static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
39
Karlheinz Jerg1eb95eb2013-01-21 03:55:16 +000040static int piggy_present(void)
41{
42 struct km_bec_fpga __iomem *base =
43 (struct km_bec_fpga __iomem *)CONFIG_SYS_KMBEC_FPGA_BASE;
44
45 return in_8(&base->bprth) & PIGGY_PRESENT;
46}
47
Karlheinz Jerg1eb95eb2013-01-21 03:55:16 +000048int ethernet_present(void)
49{
50 return piggy_present();
51}
Karlheinz Jerg1eb95eb2013-01-21 03:55:16 +000052
Heiko Schocherb11f53f2011-03-15 16:52:29 +010053int board_early_init_r(void)
Heiko Schocherde044362008-11-20 09:57:47 +010054{
Heiko Schocher8ed74342011-03-08 10:47:39 +010055 struct km_bec_fpga *base =
56 (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
Heiko Schocherde044362008-11-20 09:57:47 +010057
Mario Six61abced2019-01-21 09:17:28 +010058#if defined(CONFIG_ARCH_MPC8360)
Heiko Schocher62ddcf02010-02-18 08:08:25 +010059 unsigned short svid;
Heiko Schocherde044362008-11-20 09:57:47 +010060 /*
61 * Because of errata in the UCCs, we have to write to the reserved
62 * registers to slow the clocks down.
63 */
Heiko Schocherb11f53f2011-03-15 16:52:29 +010064 svid = SVR_REV(mfspr(SVR));
Heiko Schocher1e7ed252009-02-24 11:30:48 +010065 switch (svid) {
66 case 0x0020:
Heiko Schocherb11f53f2011-03-15 16:52:29 +010067 /*
68 * MPC8360ECE.pdf QE_ENET10 table 4:
69 * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
70 * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
71 */
Heiko Schocher1e7ed252009-02-24 11:30:48 +010072 setbits_be32((void *)(CONFIG_SYS_IMMR + 0x14a8), 0x0c003000);
73 break;
74 case 0x0021:
Heiko Schocherb11f53f2011-03-15 16:52:29 +010075 /*
76 * MPC8360ECE.pdf QE_ENET10 table 4:
77 * IMMR + 0x14AC[24:27] = 1010
78 */
Heiko Schocher1e7ed252009-02-24 11:30:48 +010079 clrsetbits_be32((void *)(CONFIG_SYS_IMMR + 0x14ac),
80 0x00000050, 0x000000a0);
81 break;
82 }
Heiko Schocher62ddcf02010-02-18 08:08:25 +010083#endif
84
Heiko Schocherde044362008-11-20 09:57:47 +010085 /* enable the PHY on the PIGGY */
Heiko Schocherb11f53f2011-03-15 16:52:29 +010086 setbits_8(&base->pgy_eth, 0x01);
Heiko Schocher4897ee32010-01-07 08:55:50 +010087 /* enable the Unit LED (green) */
Heiko Schocherb11f53f2011-03-15 16:52:29 +010088 setbits_8(&base->oprth, WRL_BOOT);
Stefan Bigler5758dd72012-05-04 10:55:55 +020089 /* enable Application Buffer */
90 setbits_8(&base->oprtl, OPRTL_XBUFENA);
Heiko Schocherde044362008-11-20 09:57:47 +010091
92 return 0;
93}
94
Heiko Schocherb11f53f2011-03-15 16:52:29 +010095int misc_init_r(void)
Heiko Schocher19f0e932009-02-24 11:30:34 +010096{
Holger Brunckfd7c4002019-11-25 17:24:14 +010097 ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN,
98 CONFIG_PIGGY_MAC_ADDRESS_OFFSET);
Heiko Schocher19f0e932009-02-24 11:30:34 +010099 return 0;
100}
101
Heiko Schocherf1fef1d2010-04-26 13:07:28 +0200102int last_stage_init(void)
103{
Mario Six009c87a2019-01-21 09:17:35 +0100104#if defined(CONFIG_TARGET_KMCOGE5NE)
Thomas Herzmann13fff222012-05-04 10:55:57 +0200105 struct bfticu_iomap *base =
106 (struct bfticu_iomap *)CONFIG_SYS_BFTIC3_BASE;
107 u8 dip_switch = in_8((u8 *)&(base->mswitch)) & BFTICU_DIPSWITCH_MASK;
108
109 if (dip_switch != 0) {
110 /* start bootloader */
111 puts("DIP: Enabled\n");
Simon Glass382bee52017-08-03 12:22:09 -0600112 env_set("actual_bank", "0");
Thomas Herzmann13fff222012-05-04 10:55:57 +0200113 }
114#endif
Heiko Schocherf1fef1d2010-04-26 13:07:28 +0200115 set_km_env();
116 return 0;
117}
118
Holger Brunck283857d2013-05-06 15:02:40 +0200119static int fixed_sdram(void)
Heiko Schocherde044362008-11-20 09:57:47 +0100120{
Heiko Schocherb11f53f2011-03-15 16:52:29 +0100121 immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
Heiko Schocherde044362008-11-20 09:57:47 +0100122 u32 msize = 0;
123 u32 ddr_size;
124 u32 ddr_size_log2;
125
Heiko Schocherb11f53f2011-03-15 16:52:29 +0100126 out_be32(&im->sysconf.ddrlaw[0].ar, (LAWAR_EN | 0x1e));
Christian Herzig43afc172012-03-21 13:42:43 +0100127 out_be32(&im->ddr.csbnds[0].csbnds, (CONFIG_SYS_DDR_CS0_BNDS) | 0x7f);
Heiko Schocherb11f53f2011-03-15 16:52:29 +0100128 out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
129 out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
130 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
131 out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
132 out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
133 out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
134 out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2);
135 out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
136 out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2);
137 out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
138 out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL);
139 udelay(200);
Andreas Huber55449a02011-11-10 15:52:43 +0100140 setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
Heiko Schocherde044362008-11-20 09:57:47 +0100141
Heiko Schocher118cbe32009-02-24 11:30:40 +0100142 msize = CONFIG_SYS_DDR_SIZE << 20;
Heiko Schocherb11f53f2011-03-15 16:52:29 +0100143 disable_addr_trans();
Mario Six8a81bfd2019-01-21 09:18:15 +0100144 msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, msize);
Heiko Schocherb11f53f2011-03-15 16:52:29 +0100145 enable_addr_trans();
Heiko Schocher118cbe32009-02-24 11:30:40 +0100146 msize /= (1024 * 1024);
147 if (CONFIG_SYS_DDR_SIZE != msize) {
148 for (ddr_size = msize << 20, ddr_size_log2 = 0;
Heiko Schocherb11f53f2011-03-15 16:52:29 +0100149 (ddr_size > 1);
150 ddr_size = ddr_size >> 1, ddr_size_log2++)
Heiko Schocher118cbe32009-02-24 11:30:40 +0100151 if (ddr_size & 1)
152 return -1;
Heiko Schocherb11f53f2011-03-15 16:52:29 +0100153 out_be32(&im->sysconf.ddrlaw[0].ar,
154 (LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE)));
155 out_be32(&im->ddr.csbnds[0].csbnds,
156 (((msize / 16) - 1) & 0xff));
Heiko Schocher118cbe32009-02-24 11:30:40 +0100157 }
158
Heiko Schocherde044362008-11-20 09:57:47 +0100159 return msize;
160}
161
Simon Glassf1683aa2017-04-06 12:47:05 -0600162int dram_init(void)
Heiko Schocherde044362008-11-20 09:57:47 +0100163{
Heiko Schocherb11f53f2011-03-15 16:52:29 +0100164 immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
Heiko Schocherde044362008-11-20 09:57:47 +0100165 u32 msize = 0;
166
Heiko Schocherb11f53f2011-03-15 16:52:29 +0100167 if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
Simon Glass088454c2017-03-31 08:40:25 -0600168 return -ENXIO;
Heiko Schocherde044362008-11-20 09:57:47 +0100169
Heiko Schocherb11f53f2011-03-15 16:52:29 +0100170 out_be32(&im->sysconf.ddrlaw[0].bar,
Mario Six8a81bfd2019-01-21 09:18:15 +0100171 CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR);
Heiko Schocherb11f53f2011-03-15 16:52:29 +0100172 msize = fixed_sdram();
Heiko Schocherde044362008-11-20 09:57:47 +0100173
Peter Tyser9adda542009-06-30 17:15:50 -0500174#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
Heiko Schocherde044362008-11-20 09:57:47 +0100175 /*
176 * Initialize DDR ECC byte
177 */
Heiko Schocherb11f53f2011-03-15 16:52:29 +0100178 ddr_enable_ecc(msize * 1024 * 1024);
Heiko Schocherde044362008-11-20 09:57:47 +0100179#endif
180
181 /* return total bus SDRAM size(bytes) -- DDR */
Simon Glass088454c2017-03-31 08:40:25 -0600182 gd->ram_size = msize * 1024 * 1024;
183
184 return 0;
Heiko Schocherde044362008-11-20 09:57:47 +0100185}
186
Heiko Schocherb11f53f2011-03-15 16:52:29 +0100187int checkboard(void)
Heiko Schocherde044362008-11-20 09:57:47 +0100188{
Holger Brunck5d57dfa2020-10-08 12:27:22 +0200189 puts("Board: Hitachi " CONFIG_SYS_CONFIG_NAME);
Heiko Schocher62ddcf02010-02-18 08:08:25 +0100190
Karlheinz Jerg1eb95eb2013-01-21 03:55:16 +0000191 if (piggy_present())
Heiko Schocherb11f53f2011-03-15 16:52:29 +0100192 puts(" with PIGGY.");
193 puts("\n");
Heiko Schocherde044362008-11-20 09:57:47 +0100194 return 0;
195}
196
Masahiro Yamadab75d8dc2020-06-26 15:13:33 +0900197int ft_board_setup(void *blob, struct bd_info *bd)
Heiko Schocherde044362008-11-20 09:57:47 +0100198{
Heiko Schocher62ddcf02010-02-18 08:08:25 +0100199 ft_cpu_setup(blob, bd);
Simon Glasse895a4b2014-10-23 18:58:47 -0600200
201 return 0;
Heiko Schocherde044362008-11-20 09:57:47 +0100202}
Heiko Schocher19f0e932009-02-24 11:30:34 +0100203
204#if defined(CONFIG_HUSH_INIT_VAR)
Heiko Schocherb11f53f2011-03-15 16:52:29 +0100205int hush_init_var(void)
Heiko Schocher19f0e932009-02-24 11:30:34 +0100206{
Valentin Longchampf32b3d32015-02-10 17:10:16 +0100207 ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
Heiko Schocher19f0e932009-02-24 11:30:34 +0100208 return 0;
209}
210#endif
Thomas Herzmann95209b62012-05-04 10:55:56 +0200211
212#if defined(CONFIG_POST)
213int post_hotkeys_pressed(void)
214{
215 int testpin = 0;
216 struct km_bec_fpga *base =
217 (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
218 int testpin_reg = in_8(&base->CONFIG_TESTPIN_REG);
219 testpin = (testpin_reg & CONFIG_TESTPIN_MASK) != 0;
220 debug("post_hotkeys_pressed: %d\n", !testpin);
221 return testpin;
222}
223
224ulong post_word_load(void)
225{
226 void* addr = (ulong *) (CPM_POST_WORD_ADDR);
227 debug("post_word_load 0x%08lX: 0x%08X\n", (ulong)addr, in_le32(addr));
228 return in_le32(addr);
229
230}
231void post_word_store(ulong value)
232{
233 void* addr = (ulong *) (CPM_POST_WORD_ADDR);
234 debug("post_word_store 0x%08lX: 0x%08lX\n", (ulong)addr, value);
235 out_le32(addr, value);
236}
237
238int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
239{
Holger Brunckc904a0b2020-10-29 13:54:54 +0100240 *vstart = CONFIG_SYS_MEMTEST_START;
241 *size = CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START;
Thomas Herzmann95209b62012-05-04 10:55:56 +0200242 debug("arch_memory_test_prepare 0x%08X 0x%08X\n", *vstart, *size);
243
244 return 0;
245}
246#endif