Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Heiko Schocher | de04436 | 2008-11-20 09:57:47 +0100 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2006 Freescale Semiconductor, Inc. |
| 4 | * Dave Liu <daveliu@freescale.com> |
| 5 | * |
| 6 | * Copyright (C) 2007 Logic Product Development, Inc. |
| 7 | * Peter Barada <peterb@logicpd.com> |
| 8 | * |
| 9 | * Copyright (C) 2007 MontaVista Software, Inc. |
| 10 | * Anton Vorontsov <avorontsov@ru.mvista.com> |
| 11 | * |
Heiko Schocher | 62ddcf0 | 2010-02-18 08:08:25 +0100 | [diff] [blame] | 12 | * (C) Copyright 2008 - 2010 |
Heiko Schocher | de04436 | 2008-11-20 09:57:47 +0100 | [diff] [blame] | 13 | * Heiko Schocher, DENX Software Engineering, hs@denx.de. |
Heiko Schocher | de04436 | 2008-11-20 09:57:47 +0100 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include <common.h> |
Simon Glass | 9fb625c | 2019-08-01 09:46:51 -0600 | [diff] [blame] | 17 | #include <env.h> |
Simon Glass | 807765b | 2019-12-28 10:44:54 -0700 | [diff] [blame] | 18 | #include <fdt_support.h> |
Simon Glass | 5255932 | 2019-11-14 12:57:46 -0700 | [diff] [blame] | 19 | #include <init.h> |
Heiko Schocher | de04436 | 2008-11-20 09:57:47 +0100 | [diff] [blame] | 20 | #include <ioports.h> |
Simon Glass | f7ae49f | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 21 | #include <log.h> |
Heiko Schocher | de04436 | 2008-11-20 09:57:47 +0100 | [diff] [blame] | 22 | #include <mpc83xx.h> |
| 23 | #include <i2c.h> |
| 24 | #include <miiphy.h> |
Simon Glass | 401d1c4 | 2020-10-30 21:38:53 -0600 | [diff] [blame] | 25 | #include <asm/global_data.h> |
Heiko Schocher | de04436 | 2008-11-20 09:57:47 +0100 | [diff] [blame] | 26 | #include <asm/io.h> |
| 27 | #include <asm/mmu.h> |
Heiko Schocher | 1e7ed25 | 2009-02-24 11:30:48 +0100 | [diff] [blame] | 28 | #include <asm/processor.h> |
Heiko Schocher | de04436 | 2008-11-20 09:57:47 +0100 | [diff] [blame] | 29 | #include <pci.h> |
Simon Glass | c05ed00 | 2020-05-10 11:40:11 -0600 | [diff] [blame] | 30 | #include <linux/delay.h> |
Masahiro Yamada | b08c8c4 | 2018-03-05 01:20:11 +0900 | [diff] [blame] | 31 | #include <linux/libfdt.h> |
Thomas Herzmann | 95209b6 | 2012-05-04 10:55:56 +0200 | [diff] [blame] | 32 | #include <post.h> |
Heiko Schocher | de04436 | 2008-11-20 09:57:47 +0100 | [diff] [blame] | 33 | |
Heiko Schocher | 210c8c0 | 2008-11-21 08:29:40 +0100 | [diff] [blame] | 34 | #include "../common/common.h" |
| 35 | |
Simon Glass | 088454c | 2017-03-31 08:40:25 -0600 | [diff] [blame] | 36 | DECLARE_GLOBAL_DATA_PTR; |
| 37 | |
Valentin Longchamp | f32b3d3 | 2015-02-10 17:10:16 +0100 | [diff] [blame] | 38 | static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN]; |
| 39 | |
Karlheinz Jerg | 1eb95eb | 2013-01-21 03:55:16 +0000 | [diff] [blame] | 40 | static int piggy_present(void) |
| 41 | { |
| 42 | struct km_bec_fpga __iomem *base = |
| 43 | (struct km_bec_fpga __iomem *)CONFIG_SYS_KMBEC_FPGA_BASE; |
| 44 | |
| 45 | return in_8(&base->bprth) & PIGGY_PRESENT; |
| 46 | } |
| 47 | |
Karlheinz Jerg | 1eb95eb | 2013-01-21 03:55:16 +0000 | [diff] [blame] | 48 | int ethernet_present(void) |
| 49 | { |
| 50 | return piggy_present(); |
| 51 | } |
Karlheinz Jerg | 1eb95eb | 2013-01-21 03:55:16 +0000 | [diff] [blame] | 52 | |
Heiko Schocher | b11f53f | 2011-03-15 16:52:29 +0100 | [diff] [blame] | 53 | int board_early_init_r(void) |
Heiko Schocher | de04436 | 2008-11-20 09:57:47 +0100 | [diff] [blame] | 54 | { |
Heiko Schocher | 8ed7434 | 2011-03-08 10:47:39 +0100 | [diff] [blame] | 55 | struct km_bec_fpga *base = |
| 56 | (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE; |
Heiko Schocher | de04436 | 2008-11-20 09:57:47 +0100 | [diff] [blame] | 57 | |
Mario Six | 61abced | 2019-01-21 09:17:28 +0100 | [diff] [blame] | 58 | #if defined(CONFIG_ARCH_MPC8360) |
Heiko Schocher | 62ddcf0 | 2010-02-18 08:08:25 +0100 | [diff] [blame] | 59 | unsigned short svid; |
Heiko Schocher | de04436 | 2008-11-20 09:57:47 +0100 | [diff] [blame] | 60 | /* |
| 61 | * Because of errata in the UCCs, we have to write to the reserved |
| 62 | * registers to slow the clocks down. |
| 63 | */ |
Heiko Schocher | b11f53f | 2011-03-15 16:52:29 +0100 | [diff] [blame] | 64 | svid = SVR_REV(mfspr(SVR)); |
Heiko Schocher | 1e7ed25 | 2009-02-24 11:30:48 +0100 | [diff] [blame] | 65 | switch (svid) { |
| 66 | case 0x0020: |
Heiko Schocher | b11f53f | 2011-03-15 16:52:29 +0100 | [diff] [blame] | 67 | /* |
| 68 | * MPC8360ECE.pdf QE_ENET10 table 4: |
| 69 | * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2) |
| 70 | * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1) |
| 71 | */ |
Heiko Schocher | 1e7ed25 | 2009-02-24 11:30:48 +0100 | [diff] [blame] | 72 | setbits_be32((void *)(CONFIG_SYS_IMMR + 0x14a8), 0x0c003000); |
| 73 | break; |
| 74 | case 0x0021: |
Heiko Schocher | b11f53f | 2011-03-15 16:52:29 +0100 | [diff] [blame] | 75 | /* |
| 76 | * MPC8360ECE.pdf QE_ENET10 table 4: |
| 77 | * IMMR + 0x14AC[24:27] = 1010 |
| 78 | */ |
Heiko Schocher | 1e7ed25 | 2009-02-24 11:30:48 +0100 | [diff] [blame] | 79 | clrsetbits_be32((void *)(CONFIG_SYS_IMMR + 0x14ac), |
| 80 | 0x00000050, 0x000000a0); |
| 81 | break; |
| 82 | } |
Heiko Schocher | 62ddcf0 | 2010-02-18 08:08:25 +0100 | [diff] [blame] | 83 | #endif |
| 84 | |
Heiko Schocher | de04436 | 2008-11-20 09:57:47 +0100 | [diff] [blame] | 85 | /* enable the PHY on the PIGGY */ |
Heiko Schocher | b11f53f | 2011-03-15 16:52:29 +0100 | [diff] [blame] | 86 | setbits_8(&base->pgy_eth, 0x01); |
Heiko Schocher | 4897ee3 | 2010-01-07 08:55:50 +0100 | [diff] [blame] | 87 | /* enable the Unit LED (green) */ |
Heiko Schocher | b11f53f | 2011-03-15 16:52:29 +0100 | [diff] [blame] | 88 | setbits_8(&base->oprth, WRL_BOOT); |
Stefan Bigler | 5758dd7 | 2012-05-04 10:55:55 +0200 | [diff] [blame] | 89 | /* enable Application Buffer */ |
| 90 | setbits_8(&base->oprtl, OPRTL_XBUFENA); |
Heiko Schocher | de04436 | 2008-11-20 09:57:47 +0100 | [diff] [blame] | 91 | |
| 92 | return 0; |
| 93 | } |
| 94 | |
Heiko Schocher | b11f53f | 2011-03-15 16:52:29 +0100 | [diff] [blame] | 95 | int misc_init_r(void) |
Heiko Schocher | 19f0e93 | 2009-02-24 11:30:34 +0100 | [diff] [blame] | 96 | { |
Holger Brunck | fd7c400 | 2019-11-25 17:24:14 +0100 | [diff] [blame] | 97 | ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN, |
| 98 | CONFIG_PIGGY_MAC_ADDRESS_OFFSET); |
Heiko Schocher | 19f0e93 | 2009-02-24 11:30:34 +0100 | [diff] [blame] | 99 | return 0; |
| 100 | } |
| 101 | |
Heiko Schocher | f1fef1d | 2010-04-26 13:07:28 +0200 | [diff] [blame] | 102 | int last_stage_init(void) |
| 103 | { |
Mario Six | 009c87a | 2019-01-21 09:17:35 +0100 | [diff] [blame] | 104 | #if defined(CONFIG_TARGET_KMCOGE5NE) |
Thomas Herzmann | 13fff22 | 2012-05-04 10:55:57 +0200 | [diff] [blame] | 105 | struct bfticu_iomap *base = |
| 106 | (struct bfticu_iomap *)CONFIG_SYS_BFTIC3_BASE; |
| 107 | u8 dip_switch = in_8((u8 *)&(base->mswitch)) & BFTICU_DIPSWITCH_MASK; |
| 108 | |
| 109 | if (dip_switch != 0) { |
| 110 | /* start bootloader */ |
| 111 | puts("DIP: Enabled\n"); |
Simon Glass | 382bee5 | 2017-08-03 12:22:09 -0600 | [diff] [blame] | 112 | env_set("actual_bank", "0"); |
Thomas Herzmann | 13fff22 | 2012-05-04 10:55:57 +0200 | [diff] [blame] | 113 | } |
| 114 | #endif |
Heiko Schocher | f1fef1d | 2010-04-26 13:07:28 +0200 | [diff] [blame] | 115 | set_km_env(); |
| 116 | return 0; |
| 117 | } |
| 118 | |
Holger Brunck | 283857d | 2013-05-06 15:02:40 +0200 | [diff] [blame] | 119 | static int fixed_sdram(void) |
Heiko Schocher | de04436 | 2008-11-20 09:57:47 +0100 | [diff] [blame] | 120 | { |
Heiko Schocher | b11f53f | 2011-03-15 16:52:29 +0100 | [diff] [blame] | 121 | immap_t *im = (immap_t *)CONFIG_SYS_IMMR; |
Heiko Schocher | de04436 | 2008-11-20 09:57:47 +0100 | [diff] [blame] | 122 | u32 msize = 0; |
| 123 | u32 ddr_size; |
| 124 | u32 ddr_size_log2; |
| 125 | |
Heiko Schocher | b11f53f | 2011-03-15 16:52:29 +0100 | [diff] [blame] | 126 | out_be32(&im->sysconf.ddrlaw[0].ar, (LAWAR_EN | 0x1e)); |
Christian Herzig | 43afc17 | 2012-03-21 13:42:43 +0100 | [diff] [blame] | 127 | out_be32(&im->ddr.csbnds[0].csbnds, (CONFIG_SYS_DDR_CS0_BNDS) | 0x7f); |
Heiko Schocher | b11f53f | 2011-03-15 16:52:29 +0100 | [diff] [blame] | 128 | out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG); |
| 129 | out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); |
| 130 | out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); |
| 131 | out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); |
| 132 | out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); |
| 133 | out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG); |
| 134 | out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2); |
| 135 | out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE); |
| 136 | out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2); |
| 137 | out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL); |
| 138 | out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL); |
| 139 | udelay(200); |
Andreas Huber | 55449a0 | 2011-11-10 15:52:43 +0100 | [diff] [blame] | 140 | setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); |
Heiko Schocher | de04436 | 2008-11-20 09:57:47 +0100 | [diff] [blame] | 141 | |
Heiko Schocher | 118cbe3 | 2009-02-24 11:30:40 +0100 | [diff] [blame] | 142 | msize = CONFIG_SYS_DDR_SIZE << 20; |
Heiko Schocher | b11f53f | 2011-03-15 16:52:29 +0100 | [diff] [blame] | 143 | disable_addr_trans(); |
Mario Six | 8a81bfd | 2019-01-21 09:18:15 +0100 | [diff] [blame] | 144 | msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, msize); |
Heiko Schocher | b11f53f | 2011-03-15 16:52:29 +0100 | [diff] [blame] | 145 | enable_addr_trans(); |
Heiko Schocher | 118cbe3 | 2009-02-24 11:30:40 +0100 | [diff] [blame] | 146 | msize /= (1024 * 1024); |
| 147 | if (CONFIG_SYS_DDR_SIZE != msize) { |
| 148 | for (ddr_size = msize << 20, ddr_size_log2 = 0; |
Heiko Schocher | b11f53f | 2011-03-15 16:52:29 +0100 | [diff] [blame] | 149 | (ddr_size > 1); |
| 150 | ddr_size = ddr_size >> 1, ddr_size_log2++) |
Heiko Schocher | 118cbe3 | 2009-02-24 11:30:40 +0100 | [diff] [blame] | 151 | if (ddr_size & 1) |
| 152 | return -1; |
Heiko Schocher | b11f53f | 2011-03-15 16:52:29 +0100 | [diff] [blame] | 153 | out_be32(&im->sysconf.ddrlaw[0].ar, |
| 154 | (LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE))); |
| 155 | out_be32(&im->ddr.csbnds[0].csbnds, |
| 156 | (((msize / 16) - 1) & 0xff)); |
Heiko Schocher | 118cbe3 | 2009-02-24 11:30:40 +0100 | [diff] [blame] | 157 | } |
| 158 | |
Heiko Schocher | de04436 | 2008-11-20 09:57:47 +0100 | [diff] [blame] | 159 | return msize; |
| 160 | } |
| 161 | |
Simon Glass | f1683aa | 2017-04-06 12:47:05 -0600 | [diff] [blame] | 162 | int dram_init(void) |
Heiko Schocher | de04436 | 2008-11-20 09:57:47 +0100 | [diff] [blame] | 163 | { |
Heiko Schocher | b11f53f | 2011-03-15 16:52:29 +0100 | [diff] [blame] | 164 | immap_t *im = (immap_t *)CONFIG_SYS_IMMR; |
Heiko Schocher | de04436 | 2008-11-20 09:57:47 +0100 | [diff] [blame] | 165 | u32 msize = 0; |
| 166 | |
Heiko Schocher | b11f53f | 2011-03-15 16:52:29 +0100 | [diff] [blame] | 167 | if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im) |
Simon Glass | 088454c | 2017-03-31 08:40:25 -0600 | [diff] [blame] | 168 | return -ENXIO; |
Heiko Schocher | de04436 | 2008-11-20 09:57:47 +0100 | [diff] [blame] | 169 | |
Heiko Schocher | b11f53f | 2011-03-15 16:52:29 +0100 | [diff] [blame] | 170 | out_be32(&im->sysconf.ddrlaw[0].bar, |
Mario Six | 8a81bfd | 2019-01-21 09:18:15 +0100 | [diff] [blame] | 171 | CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR); |
Heiko Schocher | b11f53f | 2011-03-15 16:52:29 +0100 | [diff] [blame] | 172 | msize = fixed_sdram(); |
Heiko Schocher | de04436 | 2008-11-20 09:57:47 +0100 | [diff] [blame] | 173 | |
Peter Tyser | 9adda54 | 2009-06-30 17:15:50 -0500 | [diff] [blame] | 174 | #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) |
Heiko Schocher | de04436 | 2008-11-20 09:57:47 +0100 | [diff] [blame] | 175 | /* |
| 176 | * Initialize DDR ECC byte |
| 177 | */ |
Heiko Schocher | b11f53f | 2011-03-15 16:52:29 +0100 | [diff] [blame] | 178 | ddr_enable_ecc(msize * 1024 * 1024); |
Heiko Schocher | de04436 | 2008-11-20 09:57:47 +0100 | [diff] [blame] | 179 | #endif |
| 180 | |
| 181 | /* return total bus SDRAM size(bytes) -- DDR */ |
Simon Glass | 088454c | 2017-03-31 08:40:25 -0600 | [diff] [blame] | 182 | gd->ram_size = msize * 1024 * 1024; |
| 183 | |
| 184 | return 0; |
Heiko Schocher | de04436 | 2008-11-20 09:57:47 +0100 | [diff] [blame] | 185 | } |
| 186 | |
Heiko Schocher | b11f53f | 2011-03-15 16:52:29 +0100 | [diff] [blame] | 187 | int checkboard(void) |
Heiko Schocher | de04436 | 2008-11-20 09:57:47 +0100 | [diff] [blame] | 188 | { |
Holger Brunck | 5d57dfa | 2020-10-08 12:27:22 +0200 | [diff] [blame] | 189 | puts("Board: Hitachi " CONFIG_SYS_CONFIG_NAME); |
Heiko Schocher | 62ddcf0 | 2010-02-18 08:08:25 +0100 | [diff] [blame] | 190 | |
Karlheinz Jerg | 1eb95eb | 2013-01-21 03:55:16 +0000 | [diff] [blame] | 191 | if (piggy_present()) |
Heiko Schocher | b11f53f | 2011-03-15 16:52:29 +0100 | [diff] [blame] | 192 | puts(" with PIGGY."); |
| 193 | puts("\n"); |
Heiko Schocher | de04436 | 2008-11-20 09:57:47 +0100 | [diff] [blame] | 194 | return 0; |
| 195 | } |
| 196 | |
Masahiro Yamada | b75d8dc | 2020-06-26 15:13:33 +0900 | [diff] [blame] | 197 | int ft_board_setup(void *blob, struct bd_info *bd) |
Heiko Schocher | de04436 | 2008-11-20 09:57:47 +0100 | [diff] [blame] | 198 | { |
Heiko Schocher | 62ddcf0 | 2010-02-18 08:08:25 +0100 | [diff] [blame] | 199 | ft_cpu_setup(blob, bd); |
Simon Glass | e895a4b | 2014-10-23 18:58:47 -0600 | [diff] [blame] | 200 | |
| 201 | return 0; |
Heiko Schocher | de04436 | 2008-11-20 09:57:47 +0100 | [diff] [blame] | 202 | } |
Heiko Schocher | 19f0e93 | 2009-02-24 11:30:34 +0100 | [diff] [blame] | 203 | |
| 204 | #if defined(CONFIG_HUSH_INIT_VAR) |
Heiko Schocher | b11f53f | 2011-03-15 16:52:29 +0100 | [diff] [blame] | 205 | int hush_init_var(void) |
Heiko Schocher | 19f0e93 | 2009-02-24 11:30:34 +0100 | [diff] [blame] | 206 | { |
Valentin Longchamp | f32b3d3 | 2015-02-10 17:10:16 +0100 | [diff] [blame] | 207 | ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN); |
Heiko Schocher | 19f0e93 | 2009-02-24 11:30:34 +0100 | [diff] [blame] | 208 | return 0; |
| 209 | } |
| 210 | #endif |
Thomas Herzmann | 95209b6 | 2012-05-04 10:55:56 +0200 | [diff] [blame] | 211 | |
| 212 | #if defined(CONFIG_POST) |
| 213 | int post_hotkeys_pressed(void) |
| 214 | { |
| 215 | int testpin = 0; |
| 216 | struct km_bec_fpga *base = |
| 217 | (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE; |
| 218 | int testpin_reg = in_8(&base->CONFIG_TESTPIN_REG); |
| 219 | testpin = (testpin_reg & CONFIG_TESTPIN_MASK) != 0; |
| 220 | debug("post_hotkeys_pressed: %d\n", !testpin); |
| 221 | return testpin; |
| 222 | } |
| 223 | |
| 224 | ulong post_word_load(void) |
| 225 | { |
| 226 | void* addr = (ulong *) (CPM_POST_WORD_ADDR); |
| 227 | debug("post_word_load 0x%08lX: 0x%08X\n", (ulong)addr, in_le32(addr)); |
| 228 | return in_le32(addr); |
| 229 | |
| 230 | } |
| 231 | void post_word_store(ulong value) |
| 232 | { |
| 233 | void* addr = (ulong *) (CPM_POST_WORD_ADDR); |
| 234 | debug("post_word_store 0x%08lX: 0x%08lX\n", (ulong)addr, value); |
| 235 | out_le32(addr, value); |
| 236 | } |
| 237 | |
| 238 | int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset) |
| 239 | { |
Holger Brunck | c904a0b | 2020-10-29 13:54:54 +0100 | [diff] [blame] | 240 | *vstart = CONFIG_SYS_MEMTEST_START; |
| 241 | *size = CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START; |
Thomas Herzmann | 95209b6 | 2012-05-04 10:55:56 +0200 | [diff] [blame] | 242 | debug("arch_memory_test_prepare 0x%08X 0x%08X\n", *vstart, *size); |
| 243 | |
| 244 | return 0; |
| 245 | } |
| 246 | #endif |