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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 444ab3569bae32daed9c05fb10f87d907cc180ff / . / drivers / clk / sunxi / clk_h3.c
blob: 08a830bd1889c039d366c36b76d059cd74b4c357 [file] [log] [blame]
Jagan Tekie9458162018-08-02 15:43:02 +0530[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2018 Amarula Solutions.
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
5 */
6
7#include <common.h>
8#include <clk-uclass.h>
9#include <dm.h>
10#include <errno.h>
Samuel Holland21d314a2021-09-12 11:48:43 -0500[diff] [blame]11#include <clk/sunxi.h>
Jagan Tekie9458162018-08-02 15:43:02 +0530[diff] [blame]12#include <dt-bindings/clock/sun8i-h3-ccu.h>
13#include <dt-bindings/reset/sun8i-h3-ccu.h>
Simon Glasscd93d622020-05-10 11:40:13 -0600[diff] [blame]14#include <linux/bitops.h>
Jagan Tekie9458162018-08-02 15:43:02 +0530[diff] [blame]15
16static struct ccu_clk_gate h3_gates[] = {
Andre Przywara444ab352022-05-04 22:10:28 +0100[diff] [blame^]17 [CLK_PLL_PERIPH0] = GATE(0x028, BIT(31)),
18
Andre Przywarabb3e5aa2019-01-29 15:54:09 +0000[diff] [blame]19 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
20 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
21 [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
Jagan Teki68620c92019-02-28 00:26:57 +0530[diff] [blame]22 [CLK_BUS_EMAC] = GATE(0x060, BIT(17)),
Jagan Teki82111462019-02-27 20:02:06 +0530[diff] [blame]23 [CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
24 [CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
Jagan Tekie9458162018-08-02 15:43:02 +0530[diff] [blame]25 [CLK_BUS_OTG] = GATE(0x060, BIT(23)),
26 [CLK_BUS_EHCI0] = GATE(0x060, BIT(24)),
27 [CLK_BUS_EHCI1] = GATE(0x060, BIT(25)),
28 [CLK_BUS_EHCI2] = GATE(0x060, BIT(26)),
29 [CLK_BUS_EHCI3] = GATE(0x060, BIT(27)),
30 [CLK_BUS_OHCI0] = GATE(0x060, BIT(28)),
31 [CLK_BUS_OHCI1] = GATE(0x060, BIT(29)),
32 [CLK_BUS_OHCI2] = GATE(0x060, BIT(30)),
33 [CLK_BUS_OHCI3] = GATE(0x060, BIT(31)),
34
Andre Przywara444ab352022-05-04 22:10:28 +0100[diff] [blame^]35 [CLK_BUS_PIO] = GATE(0x068, BIT(5)),
36
Samuel Hollandc61897b2021-09-12 09:47:24 -0500[diff] [blame]37 [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
38 [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)),
39 [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)),
Jagan Teki4acc7112018-12-30 21:29:24 +0530[diff] [blame]40 [CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
41 [CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
42 [CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
43 [CLK_BUS_UART3] = GATE(0x06c, BIT(19)),
44
Jagan Tekiaefc0b72019-02-28 00:26:59 +0530[diff] [blame]45 [CLK_BUS_EPHY] = GATE(0x070, BIT(0)),
46
Jagan Teki82111462019-02-27 20:02:06 +0530[diff] [blame]47 [CLK_SPI0] = GATE(0x0a0, BIT(31)),
48 [CLK_SPI1] = GATE(0x0a4, BIT(31)),
49
Jagan Tekie9458162018-08-02 15:43:02 +0530[diff] [blame]50 [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)),
51 [CLK_USB_PHY1] = GATE(0x0cc, BIT(9)),
52 [CLK_USB_PHY2] = GATE(0x0cc, BIT(10)),
53 [CLK_USB_PHY3] = GATE(0x0cc, BIT(11)),
54 [CLK_USB_OHCI0] = GATE(0x0cc, BIT(16)),
55 [CLK_USB_OHCI1] = GATE(0x0cc, BIT(17)),
56 [CLK_USB_OHCI2] = GATE(0x0cc, BIT(18)),
57 [CLK_USB_OHCI3] = GATE(0x0cc, BIT(19)),
58};
59
60static struct ccu_reset h3_resets[] = {
61 [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
62 [RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
63 [RST_USB_PHY2] = RESET(0x0cc, BIT(2)),
64 [RST_USB_PHY3] = RESET(0x0cc, BIT(3)),
65
Andre Przywarabb3e5aa2019-01-29 15:54:09 +0000[diff] [blame]66 [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
67 [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
68 [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
Jagan Teki68620c92019-02-28 00:26:57 +0530[diff] [blame]69 [RST_BUS_EMAC] = RESET(0x2c0, BIT(17)),
Jagan Teki82111462019-02-27 20:02:06 +0530[diff] [blame]70 [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
71 [RST_BUS_SPI1] = RESET(0x2c0, BIT(21)),
Jagan Tekie9458162018-08-02 15:43:02 +0530[diff] [blame]72 [RST_BUS_OTG] = RESET(0x2c0, BIT(23)),
73 [RST_BUS_EHCI0] = RESET(0x2c0, BIT(24)),
74 [RST_BUS_EHCI1] = RESET(0x2c0, BIT(25)),
75 [RST_BUS_EHCI2] = RESET(0x2c0, BIT(26)),
76 [RST_BUS_EHCI3] = RESET(0x2c0, BIT(27)),
77 [RST_BUS_OHCI0] = RESET(0x2c0, BIT(28)),
78 [RST_BUS_OHCI1] = RESET(0x2c0, BIT(29)),
79 [RST_BUS_OHCI2] = RESET(0x2c0, BIT(30)),
80 [RST_BUS_OHCI3] = RESET(0x2c0, BIT(31)),
Jagan Teki8606f962018-12-30 21:37:31 +0530[diff] [blame]81
Jagan Tekiaefc0b72019-02-28 00:26:59 +0530[diff] [blame]82 [RST_BUS_EPHY] = RESET(0x2c8, BIT(2)),
83
Samuel Hollandc61897b2021-09-12 09:47:24 -0500[diff] [blame]84 [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)),
85 [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)),
86 [RST_BUS_I2C2] = RESET(0x2d8, BIT(2)),
Jagan Teki8606f962018-12-30 21:37:31 +0530[diff] [blame]87 [RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
88 [RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
89 [RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
90 [RST_BUS_UART3] = RESET(0x2d8, BIT(19)),
Jagan Tekie9458162018-08-02 15:43:02 +0530[diff] [blame]91};
92
93static const struct ccu_desc h3_ccu_desc = {
94 .gates = h3_gates,
95 .resets = h3_resets,
96};
97
98static int h3_clk_bind(struct udevice *dev)
99{
100 return sunxi_reset_bind(dev, ARRAY_SIZE(h3_resets));
101}
102
103static const struct udevice_id h3_ccu_ids[] = {
104 { .compatible = "allwinner,sun8i-h3-ccu",
105 .data = (ulong)&h3_ccu_desc },
106 { .compatible = "allwinner,sun50i-h5-ccu",
107 .data = (ulong)&h3_ccu_desc },
108 { }
109};
110
111U_BOOT_DRIVER(clk_sun8i_h3) = {
112 .name = "sun8i_h3_ccu",
113 .id = UCLASS_CLK,
114 .of_match = h3_ccu_ids,
Simon Glass41575d82020-12-03 16:55:17 -0700[diff] [blame]115 .priv_auto = sizeof(struct ccu_priv),
Jagan Tekie9458162018-08-02 15:43:02 +0530[diff] [blame]116 .ops = &sunxi_clk_ops,
117 .probe = sunxi_clk_probe,
118 .bind = h3_clk_bind,
119};