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Sergei Poselenov5d108ac2008-04-30 11:42:50 +02001/*
2 * (C) Copyright 2008
3 * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
4 *
5 * Wolfgang Denk <wd@denx.de>
6 * Copyright 2004 Freescale Semiconductor.
7 * (C) Copyright 2002,2003 Motorola,Inc.
8 * Xianghua Xiao <X.Xiao@motorola.com>
9 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28
29/*
30 * Socrates
31 */
32
33#ifndef __CONFIG_H
34#define __CONFIG_H
35
u-boot@bugs.denx.dee99b6072008-09-11 15:40:01 +020036/* new uImage format support */
37#define CONFIG_FIT 1
38#define CONFIG_OF_LIBFDT 1
39#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
40
Sergei Poselenov5d108ac2008-04-30 11:42:50 +020041/* High Level Configuration Options */
42#define CONFIG_BOOKE 1 /* BOOKE */
43#define CONFIG_E500 1 /* BOOKE e500 family */
44#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */
45#define CONFIG_MPC8544 1
46#define CONFIG_SOCRATES 1
47
48#define CONFIG_PCI
49
50#define CONFIG_TSEC_ENET /* tsec ethernet support */
51
52#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
Detlev Zundel3e79b582008-08-15 15:42:12 +020053#define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +020054
55#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
56
57/*
58 * Only possible on E500 Version 2 or newer cores.
59 */
60#define CONFIG_ENABLE_36BIT_PHYS 1
61
62/*
63 * sysclk for MPC85xx
64 *
65 * Two valid values are:
66 * 33000000
67 * 66000000
68 *
69 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
70 * is likely the desired value here, so that is now the default.
71 * The board, however, can run at 66MHz. In any event, this value
72 * must match the settings of some switches. Details can be found
73 * in the README.mpc85xxads.
74 */
75
76#ifndef CONFIG_SYS_CLK_FREQ
77#define CONFIG_SYS_CLK_FREQ 66666666
78#endif
79
80/*
81 * These can be toggled for performance analysis, otherwise use default.
82 */
83#define CONFIG_L2_CACHE /* toggle L2 cache */
84#define CONFIG_BTB /* toggle branch predition */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +020085
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020086#define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +020087
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020088#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
89#define CONFIG_SYS_MEMTEST_START 0x00400000
90#define CONFIG_SYS_MEMTEST_END 0x00C00000
Sergei Poselenov5d108ac2008-04-30 11:42:50 +020091
92/*
93 * Base addresses -- Note these are effective addresses where the
94 * actual resources get mapped (not physical addresses)
95 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020096#define CONFIG_SYS_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */
97#define CONFIG_SYS_CCSRBAR 0xE0000000 /* relocated CCSRBAR */
98#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
99#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200100
Kumar Galabe0bd822008-08-26 22:56:56 -0500101/* DDR Setup */
102#define CONFIG_FSL_DDR2
103#undef CONFIG_FSL_DDR_INTERACTIVE
104#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
105#define CONFIG_DDR_SPD
106
107#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
108#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
109
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
111#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Kumar Galabe0bd822008-08-26 22:56:56 -0500112#define CONFIG_VERY_BIG_RAM
113
114#define CONFIG_NUM_DDR_CONTROLLERS 1
115#define CONFIG_DIMM_SLOTS_PER_CTLR 1
116#define CONFIG_CHIP_SELECTS_PER_CTRL 2
117
118/* I2C addresses of SPD EEPROMs */
Anatolij Gustschin562788b2008-09-17 11:45:51 +0200119#define SPD_EEPROM_ADDRESS 0x50 /* CTLR 0 DIMM 0 */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200120
121#define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */
122
123/* Hardcoded values, to use instead of SPD */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
125#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102
126#define CONFIG_SYS_DDR_TIMING_0 0x00260802
127#define CONFIG_SYS_DDR_TIMING_1 0x3935D322
128#define CONFIG_SYS_DDR_TIMING_2 0x14904CC8
129#define CONFIG_SYS_DDR_MODE 0x00480432
130#define CONFIG_SYS_DDR_INTERVAL 0x030C0100
131#define CONFIG_SYS_DDR_CONFIG_2 0x04400000
132#define CONFIG_SYS_DDR_CONFIG 0xC3008000
133#define CONFIG_SYS_DDR_CLK_CONTROL 0x03800000
134#define CONFIG_SYS_SDRAM_SIZE 256 /* in Megs */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200135
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200136/*
137 * Flash on the LocalBus
138 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139#define CONFIG_SYS_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200140
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#define CONFIG_SYS_FLASH0 0xFE000000
142#define CONFIG_SYS_FLASH1 0xFC000000
143#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200144
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200145#define CONFIG_SYS_LBC_FLASH_BASE CONFIG_SYS_FLASH1 /* Localbus flash start */
146#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_LBC_FLASH_BASE /* start of FLASH */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200147
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_BR0_PRELIM 0xfe001001 /* port size 16bit */
149#define CONFIG_SYS_OR0_PRELIM 0xfe000030 /* 32MB Flash */
150#define CONFIG_SYS_BR1_PRELIM 0xfc001001 /* port size 16bit */
151#define CONFIG_SYS_OR1_PRELIM 0xfe000030 /* 32MB Flash */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200152
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153#define CONFIG_SYS_FLASH_CFI /* flash is CFI compat. */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200154#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver*/
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200155
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
157#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */
158#undef CONFIG_SYS_FLASH_CHECKSUM
159#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
160#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200161
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200163
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
165#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
166#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
167#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200168
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169#define CONFIG_SYS_INIT_RAM_LOCK 1
170#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
171#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End used area in RAM */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200172
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data*/
174#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
175#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200176
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200177#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256kB for Mon */
178#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 4 MB for malloc */
Detlev Zundel3e79b582008-08-15 15:42:12 +0200179
180/* FPGA and NAND */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181#define CONFIG_SYS_FPGA_BASE 0xc0000000
182#define CONFIG_SYS_FPGA_SIZE 0x00100000 /* 1 MB */
183#define CONFIG_SYS_HMI_BASE 0xc0010000
184#define CONFIG_SYS_BR3_PRELIM 0xc0001881 /* UPMA, 32-bit */
185#define CONFIG_SYS_OR3_PRELIM 0xfff00000 /* 1 MB */
Detlev Zundel3e79b582008-08-15 15:42:12 +0200186
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_FPGA_BASE + 0x70)
188#define CONFIG_SYS_MAX_NAND_DEVICE 1
Detlev Zundel3e79b582008-08-15 15:42:12 +0200189#define CONFIG_CMD_NAND
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200190
Anatolij Gustschine64987a2008-08-15 15:42:13 +0200191/* LIME GDC */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192#define CONFIG_SYS_LIME_BASE 0xc8000000
193#define CONFIG_SYS_LIME_SIZE 0x04000000 /* 64 MB */
194#define CONFIG_SYS_BR2_PRELIM 0xc80018a1 /* UPMB, 32-bit */
195#define CONFIG_SYS_OR2_PRELIM 0xfc000000 /* 64 MB */
Anatolij Gustschine64987a2008-08-15 15:42:13 +0200196
197#define CONFIG_VIDEO
198#define CONFIG_VIDEO_MB862xx
Anatolij Gustschin5d16ca82009-10-23 12:03:14 +0200199#define CONFIG_VIDEO_MB862xx_ACCEL
Anatolij Gustschine64987a2008-08-15 15:42:13 +0200200#define CONFIG_CFB_CONSOLE
201#define CONFIG_VIDEO_LOGO
202#define CONFIG_VIDEO_BMP_LOGO
203#define CONFIG_CONSOLE_EXTRA_INFO
204#define VIDEO_FB_16BPP_PIXEL_SWAP
Wolfgang Grandegger229b6dc2009-10-23 12:03:15 +0200205#define VIDEO_FB_16BPP_WORD_SWAP
Anatolij Gustschine64987a2008-08-15 15:42:13 +0200206#define CONFIG_VGA_AS_SINGLE_DEVICE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207#define CONFIG_SYS_CONSOLE_IS_IN_ENV
Anatolij Gustschine64987a2008-08-15 15:42:13 +0200208#define CONFIG_VIDEO_SW_CURSOR
209#define CONFIG_SPLASH_SCREEN
210#define CONFIG_VIDEO_BMP_GZIP
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200211#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */
Anatolij Gustschine64987a2008-08-15 15:42:13 +0200212
Wolfgang Grandeggerc28d3bb2009-10-23 12:03:13 +0200213/* SDRAM Clock frequency, 100MHz (0x0000) or 133MHz (0x10000) */
214#define CONFIG_SYS_MB862xx_CCF 0x10000
215/* SDRAM parameter */
216#define CONFIG_SYS_MB862xx_MMR 0x4157BA63
217
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200218/* Serial Port */
219
220#define CONFIG_CONS_INDEX 1
221#undef CONFIG_SERIAL_SOFTWARE_FIFO
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222#define CONFIG_SYS_NS16550
223#define CONFIG_SYS_NS16550_SERIAL
224#define CONFIG_SYS_NS16550_REG_SIZE 1
225#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200226
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
228#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200229
230#define CONFIG_BAUDRATE 115200
231
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232#define CONFIG_SYS_BAUDRATE_TABLE \
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200233 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
234
235#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200236#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
237#ifdef CONFIG_SYS_HUSH_PARSER
238#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200239#endif
240
241
242/*
243 * I2C
244 */
245#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
246#define CONFIG_HARD_I2C /* I2C with hardware support */
247#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248#define CONFIG_SYS_I2C_SPEED 102124 /* I2C speed and slave address */
249#define CONFIG_SYS_I2C_SLAVE 0x7F
250#define CONFIG_SYS_I2C_OFFSET 0x3000
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200251
Detlev Zundel3e79b582008-08-15 15:42:12 +0200252#define CONFIG_I2C_MULTI_BUS
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200253#define CONFIG_SYS_I2C2_OFFSET 0x3100
Detlev Zundel3e79b582008-08-15 15:42:12 +0200254
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200255/* I2C RTC */
Sergei Poselenove18575d2008-05-07 15:10:49 +0200256#define CONFIG_RTC_RX8025 /* Use Epson rx8025 rtc via i2c */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200257#define CONFIG_SYS_I2C_RTC_ADDR 0x32 /* at address 0x32 */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200258
Anatolij Gustschine64987a2008-08-15 15:42:13 +0200259/* I2C W83782G HW-Monitoring IC */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200260#define CONFIG_SYS_I2C_W83782G_ADDR 0x28 /* W83782G address */
Anatolij Gustschine64987a2008-08-15 15:42:13 +0200261
Sergei Poselenov2f7468a2008-05-27 10:36:07 +0200262/* I2C temp sensor */
263/* Socrates uses Maxim's DS75, which is compatible with LM75 */
264#define CONFIG_DTT_LM75 1
265#define CONFIG_DTT_SENSORS {4} /* Sensor addresses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200266#define CONFIG_SYS_DTT_MAX_TEMP 125
267#define CONFIG_SYS_DTT_LOW_TEMP -55
268#define CONFIG_SYS_DTT_HYSTERESIS 3
269#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
Sergei Poselenov2f7468a2008-05-27 10:36:07 +0200270
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200271/*
272 * General PCI
273 * Memory space is mapped 1-1.
274 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200275#define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200276
Sergei Poselenov5e1882d2008-05-27 13:47:00 +0200277/* PCI is clocked by the external source at 33 MHz */
278#define CONFIG_PCI_CLK_FREQ 33000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
280#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
281#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
282#define CONFIG_SYS_PCI1_IO_BASE 0xE2000000
283#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
284#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200285
286#if defined(CONFIG_PCI)
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200287#define CONFIG_PCI_PNP /* do pci plug-and-play */
Sergei Poselenovd39e6852008-06-06 15:42:39 +0200288#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200289#endif /* CONFIG_PCI */
290
291
292#define CONFIG_NET_MULTI 1
293#define CONFIG_MII 1 /* MII PHY management */
294#define CONFIG_TSEC1 1
295#define CONFIG_TSEC1_NAME "TSEC0"
Sergei Poselenov2f845dc2008-05-08 17:46:23 +0200296#define CONFIG_TSEC3 1
297#define CONFIG_TSEC3_NAME "TSEC1"
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200298#undef CONFIG_MPC85XX_FEC
299
300#define TSEC1_PHY_ADDR 0
Sergei Poselenov2f845dc2008-05-08 17:46:23 +0200301#define TSEC3_PHY_ADDR 1
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200302
303#define TSEC1_PHYIDX 0
Sergei Poselenov2f845dc2008-05-08 17:46:23 +0200304#define TSEC3_PHYIDX 0
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200305#define TSEC1_FLAGS TSEC_GIGABIT
Sergei Poselenov2f845dc2008-05-08 17:46:23 +0200306#define TSEC3_FLAGS TSEC_GIGABIT
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200307
Sergei Poselenov2f845dc2008-05-08 17:46:23 +0200308/* Options are: TSEC[0,1] */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200309#define CONFIG_ETHPRIME "TSEC0"
310#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
311
Sergei Poselenove18575d2008-05-07 15:10:49 +0200312#define CONFIG_HAS_ETH0
313#define CONFIG_HAS_ETH1
314
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200315/*
316 * Environment
317 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200318#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200319#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200320#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200321#define CONFIG_ENV_SIZE 0x4000
322#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
323#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200324
325#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200326#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200327
328#define CONFIG_TIMESTAMP /* Print image info with ts */
329
330
331/*
332 * BOOTP options
333 */
334#define CONFIG_BOOTP_BOOTFILESIZE
335#define CONFIG_BOOTP_BOOTPATH
336#define CONFIG_BOOTP_GATEWAY
337#define CONFIG_BOOTP_HOSTNAME
338
339
340/*
341 * Command line configuration.
342 */
343#include <config_cmd_default.h>
344
345#define CONFIG_CMD_DATE
346#define CONFIG_CMD_DHCP
Sergei Poselenov2f7468a2008-05-27 10:36:07 +0200347#define CONFIG_CMD_DTT
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200348#undef CONFIG_CMD_EEPROM
349#define CONFIG_CMD_I2C
Detlev Zundel3e79b582008-08-15 15:42:12 +0200350#define CONFIG_CMD_SDRAM
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200351#define CONFIG_CMD_MII
352#define CONFIG_CMD_NFS
353#define CONFIG_CMD_PING
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200354#define CONFIG_CMD_SNTP
Sergei Poselenov791e1db2008-05-27 11:49:13 +0200355#define CONFIG_CMD_USB
Detlev Zundel3e79b582008-08-15 15:42:12 +0200356#define CONFIG_CMD_EXT2 /* EXT2 Support */
Anatolij Gustschine64987a2008-08-15 15:42:13 +0200357#define CONFIG_CMD_BMP
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200358
359#if defined(CONFIG_PCI)
360 #define CONFIG_CMD_PCI
361#endif
362
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200363#undef CONFIG_WATCHDOG /* watchdog disabled */
364
365/*
366 * Miscellaneous configurable options
367 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200368#define CONFIG_SYS_LONGHELP /* undef to save memory */
369#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
370#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200371
372#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200373 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200374#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200375 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200376#endif
377
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200378#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buf Size */
379#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
380#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
381#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200382
383/*
384 * For booting Linux, the board info and command line data
385 * have to be in the first 8 MB of memory, since this is
386 * the maximum mapped by the Linux kernel during initialization.
387 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200388#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200389
390/*
391 * Internal Definitions
392 *
393 * Boot Flags
394 */
395#define BOOTFLAG_COLD 0x01 /* Power-On: Boot from FLASH */
396#define BOOTFLAG_WARM 0x02 /* Software reboot */
397
398#if defined(CONFIG_CMD_KGDB)
399#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/
400#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
401#endif
402
403
404#define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/
405
Detlev Zundel3e79b582008-08-15 15:42:12 +0200406#define CONFIG_BOOTDELAY 1 /* -1 disables auto-boot */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200407
408#define CONFIG_PREBOOT "echo;" \
Detlev Zundel3e79b582008-08-15 15:42:12 +0200409 "echo Welcome on the ABB Socrates Board;" \
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200410 "echo"
411
412#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
413
414#define CONFIG_EXTRA_ENV_SETTINGS \
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200415 "netdev=eth0\0" \
416 "consdev=ttyS0\0" \
Detlev Zundel3e79b582008-08-15 15:42:12 +0200417 "uboot_file=/home/tftp/syscon3/u-boot.bin\0" \
418 "bootfile=/home/tftp/syscon3/uImage\0" \
419 "fdt_file=/home/tftp/syscon3/socrates.dtb\0" \
420 "initrd_file=/home/tftp/syscon3/uinitrd.gz\0" \
421 "uboot_addr=FFFA0000\0" \
422 "kernel_addr=FE000000\0" \
423 "fdt_addr=FE1E0000\0" \
424 "ramdisk_addr=FE200000\0" \
425 "fdt_addr_r=B00000\0" \
426 "kernel_addr_r=200000\0" \
427 "ramdisk_addr_r=400000\0" \
428 "rootpath=/opt/eldk/ppc_85xxDP\0" \
429 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200430 "nfsargs=setenv bootargs root=/dev/nfs rw " \
431 "nfsroot=$serverip:$rootpath\0" \
Detlev Zundel3e79b582008-08-15 15:42:12 +0200432 "addcons=setenv bootargs $bootargs " \
433 "console=$consdev,$baudrate\0" \
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200434 "addip=setenv bootargs $bootargs " \
435 "ip=$ipaddr:$serverip:$gatewayip:$netmask" \
436 ":$hostname:$netdev:off panic=1\0" \
Detlev Zundel3e79b582008-08-15 15:42:12 +0200437 "boot_nor=run ramargs addcons;" \
Sergei Poselenove18575d2008-05-07 15:10:49 +0200438 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
Sergei Poselenove18575d2008-05-07 15:10:49 +0200439 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
440 "tftp ${fdt_addr_r} ${fdt_file}; " \
441 "run nfsargs addip addcons;" \
442 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
Detlev Zundel3e79b582008-08-15 15:42:12 +0200443 "update_uboot=tftp 100000 ${uboot_file};" \
444 "protect off fffa0000 ffffffff;" \
445 "era fffa0000 ffffffff;" \
446 "cp.b 100000 fffa0000 ${filesize};" \
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200447 "setenv filesize;saveenv\0" \
Detlev Zundel3e79b582008-08-15 15:42:12 +0200448 "update_kernel=tftp 100000 ${bootfile};" \
449 "era fe000000 fe1dffff;" \
450 "cp.b 100000 fe000000 ${filesize};" \
451 "setenv filesize;saveenv\0" \
452 "update_fdt=tftp 100000 ${fdt_file};" \
453 "era fe1e0000 fe1fffff;" \
454 "cp.b 100000 fe1e0000 ${filesize};" \
455 "setenv filesize;saveenv\0" \
456 "update_initrd=tftp 100000 ${initrd_file};" \
457 "era fe200000 fe9fffff;" \
458 "cp.b 100000 fe200000 ${filesize};" \
459 "setenv filesize;saveenv\0" \
460 "clean_data=era fea00000 fff5ffff\0" \
461 "usbargs=setenv bootargs root=/dev/sda1 rw\0" \
462 "load_usb=usb start;" \
463 "ext2load usb 0:1 ${kernel_addr_r} /boot/uImage\0" \
464 "boot_usb=run load_usb usbargs addcons;" \
465 "bootm ${kernel_addr_r} - ${fdt_addr};" \
466 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200467 ""
Detlev Zundel3e79b582008-08-15 15:42:12 +0200468#define CONFIG_BOOTCOMMAND "run boot_nor"
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200469
Sergei Poselenove18575d2008-05-07 15:10:49 +0200470/* pass open firmware flat tree */
471#define CONFIG_OF_LIBFDT 1
472#define CONFIG_OF_BOARD_SETUP 1
473
Sergei Poselenov791e1db2008-05-27 11:49:13 +0200474/* USB support */
475#define CONFIG_USB_OHCI_NEW 1
476#define CONFIG_PCI_OHCI 1
477#define CONFIG_PCI_OHCI_DEVNO 3 /* Number in PCI list */
Yuri Tikhonove90fb6a2008-09-04 11:19:05 +0200478#define CONFIG_PCI_EHCI_DEVNO (CONFIG_PCI_OHCI_DEVNO / 2)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200479#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
480#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci"
481#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
Sergei Poselenov791e1db2008-05-27 11:49:13 +0200482#define CONFIG_DOS_PARTITION 1
483#define CONFIG_USB_STORAGE 1
484
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200485#endif /* __CONFIG_H */