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wdenkbf9e3b32004-02-12 00:47:09 +00001/*
2 * (C) Copyright 2003
3 * Josef Baumgartner <josef.baumgartner@telex.de>
4 *
Heiko Schocher9acb6262006-04-20 08:42:42 +02005 * MCF5282 additionals
6 * (C) Copyright 2005
7 * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
8 *
TsiChungLiewa1436a82007-08-16 13:20:50 -05009 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
10 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
11 * Hayden Fraser (Hayden.Fraser@freescale.com)
12 *
Matthew Fettkef71d9d92008-02-04 15:38:20 -060013 * MCF5275 additions
14 * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
15 *
wdenkbf9e3b32004-02-12 00:47:09 +000016 * See file CREDITS for list of people who contributed to this
17 * project.
18 *
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License as
21 * published by the Free Software Foundation; either version 2 of
22 * the License, or (at your option) any later version.
23 *
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
Wolfgang Denk977b50f2006-05-10 17:43:20 +020026 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
wdenkbf9e3b32004-02-12 00:47:09 +000027 * GNU General Public License for more details.
28 *
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 * MA 02111-1307 USA
33 */
34
35#include <common.h>
36#include <watchdog.h>
TsiChungLiew83ec20b2007-08-15 19:21:21 -050037#include <asm/immap.h>
stroese8c725b92004-12-16 18:09:49 +000038
TsiChungLiewa1436a82007-08-16 13:20:50 -050039#if defined(CONFIG_M5253)
40/*
41 * Breath some life into the CPU...
42 *
43 * Set up the memory map,
44 * initialize a bunch of registers,
45 * initialize the UPM's
46 */
47void cpu_init_f(void)
48{
49 mbar_writeByte(MCFSIM_MPARK, 0x40); /* 5249 Internal Core takes priority over DMA */
50 mbar_writeByte(MCFSIM_SYPCR, 0x00);
51 mbar_writeByte(MCFSIM_SWIVR, 0x0f);
52 mbar_writeByte(MCFSIM_SWSR, 0x00);
53 mbar_writeByte(MCFSIM_SWDICR, 0x00);
54 mbar_writeByte(MCFSIM_TIMER1ICR, 0x00);
55 mbar_writeByte(MCFSIM_TIMER2ICR, 0x88);
56 mbar_writeByte(MCFSIM_I2CICR, 0x00);
57 mbar_writeByte(MCFSIM_UART1ICR, 0x00);
58 mbar_writeByte(MCFSIM_UART2ICR, 0x00);
59 mbar_writeByte(MCFSIM_ICR6, 0x00);
60 mbar_writeByte(MCFSIM_ICR7, 0x00);
61 mbar_writeByte(MCFSIM_ICR8, 0x00);
62 mbar_writeByte(MCFSIM_ICR9, 0x00);
63 mbar_writeByte(MCFSIM_QSPIICR, 0x00);
64
65 mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080);
66 mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */
67 mbar2_writeByte(MCFSIM_SPURVEC, 0x00);
68
Stefan Roese8280f6a2007-08-18 14:33:02 +020069 /*mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); */ /* Enable a 1 cycle pre-drive cycle on CS1 */
TsiChungLiewa1436a82007-08-16 13:20:50 -050070
71 /*
72 * Setup chip selects...
73 */
74
75 mbar_writeShort(MCFSIM_CSAR1, CFG_CSAR1);
76 mbar_writeShort(MCFSIM_CSCR1, CFG_CSCR1);
77 mbar_writeLong(MCFSIM_CSMR1, CFG_CSMR1);
78
79 mbar_writeShort(MCFSIM_CSAR0, CFG_CSAR0);
80 mbar_writeShort(MCFSIM_CSCR0, CFG_CSCR0);
81 mbar_writeLong(MCFSIM_CSMR0, CFG_CSMR0);
82
83 /* enable instruction cache now */
84 icache_enable();
85}
86
87/*initialize higher level parts of CPU like timers */
88int cpu_init_r(void)
89{
90 return (0);
91}
92
93void uart_port_conf(void)
94{
95 /* Setup Ports: */
96 switch (CFG_UART_PORT) {
97 case 0:
98 break;
99 case 1:
100 break;
101 case 2:
102 break;
103 }
104}
105#endif /* #if defined(CONFIG_M5253) */
106
Zachary P. Landaueacbd312006-01-26 17:35:56 -0500107#if defined(CONFIG_M5271)
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500108void cpu_init_f(void)
Zachary P. Landaueacbd312006-01-26 17:35:56 -0500109{
110#ifndef CONFIG_WATCHDOG
111 /* Disable the watchdog if we aren't using it */
112 mbar_writeShort(MCF_WTM_WCR, 0);
113#endif
114
115 /* Set clockspeed to 100MHz */
116 mbar_writeShort(MCF_FMPLL_SYNCR,
117 MCF_FMPLL_SYNCR_MFD(0) | MCF_FMPLL_SYNCR_RFD(0));
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500118 while (!mbar_readByte(MCF_FMPLL_SYNSR) & MCF_FMPLL_SYNSR_LOCK) ;
Zachary P. Landaueacbd312006-01-26 17:35:56 -0500119}
120
121/*
122 * initialize higher level parts of CPU like timers
123 */
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500124int cpu_init_r(void)
Zachary P. Landaueacbd312006-01-26 17:35:56 -0500125{
126 return (0);
127}
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500128
129void uart_port_conf(void)
130{
131 /* Setup Ports: */
132 switch (CFG_UART_PORT) {
133 case 0:
134 mbar_writeShort(MCF_GPIO_PAR_UART, MCF_GPIO_PAR_UART_U0TXD |
135 MCF_GPIO_PAR_UART_U0RXD);
136 break;
137 case 1:
138 mbar_writeShort(MCF_GPIO_PAR_UART,
139 MCF_GPIO_PAR_UART_U1RXD_UART1 |
140 MCF_GPIO_PAR_UART_U1TXD_UART1);
141 break;
142 case 2:
143 mbar_writeShort(MCF_GPIO_PAR_UART, 0x3000);
144 break;
145 }
146}
Zachary P. Landaueacbd312006-01-26 17:35:56 -0500147#endif
148
stroese8c725b92004-12-16 18:09:49 +0000149#if defined(CONFIG_M5272)
wdenkbf9e3b32004-02-12 00:47:09 +0000150/*
151 * Breath some life into the CPU...
152 *
153 * Set up the memory map,
154 * initialize a bunch of registers,
155 * initialize the UPM's
156 */
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500157void cpu_init_f(void)
wdenkbf9e3b32004-02-12 00:47:09 +0000158{
159 /* if we come from RAM we assume the CPU is
160 * already initialized.
161 */
162#ifndef CONFIG_MONITOR_IS_IN_RAM
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500163 volatile sysctrl_t *sysctrl = (sysctrl_t *) (CFG_MBAR);
164 volatile gpio_t *gpio = (gpio_t *) (MMAP_GPIO);
165 volatile csctrl_t *csctrl = (csctrl_t *) (MMAP_FBCS);
wdenkbf9e3b32004-02-12 00:47:09 +0000166
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500167 sysctrl->sc_scr = CFG_SCR;
168 sysctrl->sc_spr = CFG_SPR;
wdenkbf9e3b32004-02-12 00:47:09 +0000169
Wolfgang Denk977b50f2006-05-10 17:43:20 +0200170 /* Setup Ports: */
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500171 gpio->gpio_pacnt = CFG_PACNT;
172 gpio->gpio_paddr = CFG_PADDR;
173 gpio->gpio_padat = CFG_PADAT;
174 gpio->gpio_pbcnt = CFG_PBCNT;
175 gpio->gpio_pbddr = CFG_PBDDR;
176 gpio->gpio_pbdat = CFG_PBDAT;
177 gpio->gpio_pdcnt = CFG_PDCNT;
wdenkbf9e3b32004-02-12 00:47:09 +0000178
179 /* Memory Controller: */
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500180 csctrl->cs_br0 = CFG_BR0_PRELIM;
181 csctrl->cs_or0 = CFG_OR0_PRELIM;
wdenkbf9e3b32004-02-12 00:47:09 +0000182
183#if (defined(CFG_OR1_PRELIM) && defined(CFG_BR1_PRELIM))
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500184 csctrl->cs_br1 = CFG_BR1_PRELIM;
185 csctrl->cs_or1 = CFG_OR1_PRELIM;
wdenkbf9e3b32004-02-12 00:47:09 +0000186#endif
187
188#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500189 csctrl->cs_br2 = CFG_BR2_PRELIM;
190 csctrl->cs_or2 = CFG_OR2_PRELIM;
wdenkbf9e3b32004-02-12 00:47:09 +0000191#endif
192
193#if defined(CFG_OR3_PRELIM) && defined(CFG_BR3_PRELIM)
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500194 csctrl->cs_br3 = CFG_BR3_PRELIM;
195 csctrl->cs_or3 = CFG_OR3_PRELIM;
wdenkbf9e3b32004-02-12 00:47:09 +0000196#endif
197
198#if defined(CFG_OR4_PRELIM) && defined(CFG_BR4_PRELIM)
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500199 csctrl->cs_br4 = CFG_BR4_PRELIM;
200 csctrl->cs_or4 = CFG_OR4_PRELIM;
wdenkbf9e3b32004-02-12 00:47:09 +0000201#endif
202
203#if defined(CFG_OR5_PRELIM) && defined(CFG_BR5_PRELIM)
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500204 csctrl->cs_br5 = CFG_BR5_PRELIM;
205 csctrl->cs_or5 = CFG_OR5_PRELIM;
wdenkbf9e3b32004-02-12 00:47:09 +0000206#endif
207
208#if defined(CFG_OR6_PRELIM) && defined(CFG_BR6_PRELIM)
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500209 csctrl->cs_br6 = CFG_BR6_PRELIM;
210 csctrl->cs_or6 = CFG_OR6_PRELIM;
wdenkbf9e3b32004-02-12 00:47:09 +0000211#endif
212
213#if defined(CFG_OR7_PRELIM) && defined(CFG_BR7_PRELIM)
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500214 csctrl->cs_br7 = CFG_BR7_PRELIM;
215 csctrl->cs_or7 = CFG_OR7_PRELIM;
wdenkbf9e3b32004-02-12 00:47:09 +0000216#endif
217
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500218#endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
wdenkbf9e3b32004-02-12 00:47:09 +0000219
Wolfgang Denk977b50f2006-05-10 17:43:20 +0200220 /* enable instruction cache now */
221 icache_enable();
wdenkbf9e3b32004-02-12 00:47:09 +0000222
223}
224
225/*
226 * initialize higher level parts of CPU like timers
227 */
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500228int cpu_init_r(void)
wdenkbf9e3b32004-02-12 00:47:09 +0000229{
230 return (0);
231}
wdenkbf9e3b32004-02-12 00:47:09 +0000232
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500233void uart_port_conf(void)
234{
235 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
wdenkbf9e3b32004-02-12 00:47:09 +0000236
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500237 /* Setup Ports: */
238 switch (CFG_UART_PORT) {
239 case 0:
240 gpio->gpio_pbcnt &= ~(GPIO_PBCNT_PB0MSK | GPIO_PBCNT_PB1MSK);
241 gpio->gpio_pbcnt |= (GPIO_PBCNT_URT0_TXD | GPIO_PBCNT_URT0_RXD);
242 break;
243 case 1:
244 gpio->gpio_pdcnt &= ~(GPIO_PDCNT_PD1MSK | GPIO_PDCNT_PD4MSK);
245 gpio->gpio_pdcnt |= (GPIO_PDCNT_URT1_RXD | GPIO_PDCNT_URT1_TXD);
246 break;
247 }
248}
249#endif /* #if defined(CONFIG_M5272) */
250
Matthew Fettkef71d9d92008-02-04 15:38:20 -0600251#if defined(CONFIG_M5275)
252
253/*
254 * Breathe some life into the CPU...
255 *
256 * Set up the memory map,
257 * initialize a bunch of registers,
258 * initialize the UPM's
259 */
260void cpu_init_f(void)
261{
262 /* if we come from RAM we assume the CPU is
263 * already initialized.
264 */
265
266#ifndef CONFIG_MONITOR_IS_IN_RAM
267 volatile wdog_t *wdog_reg = (wdog_t *)(MMAP_WDOG);
268 volatile gpio_t *gpio_reg = (gpio_t *)(MMAP_GPIO);
269 volatile csctrl_t *csctrl_reg = (csctrl_t *)(MMAP_FBCS);
270
271 /* Kill watchdog so we can initialize the PLL */
272 wdog_reg->wcr = 0;
273
274 /* Memory Controller: */
275 /* Flash */
276 csctrl_reg->ar0 = CFG_AR0_PRELIM;
277 csctrl_reg->cr0 = CFG_CR0_PRELIM;
278 csctrl_reg->mr0 = CFG_MR0_PRELIM;
279
280#if (defined(CFG_AR1_PRELIM) && defined(CFG_CR1_PRELIM) && defined(CFG_MR1_PRELIM))
281 csctrl_reg->ar1 = CFG_AR1_PRELIM;
282 csctrl_reg->cr1 = CFG_CR1_PRELIM;
283 csctrl_reg->mr1 = CFG_MR1_PRELIM;
284#endif
285
286#if (defined(CFG_AR2_PRELIM) && defined(CFG_CR2_PRELIM) && defined(CFG_MR2_PRELIM))
287 csctrl_reg->ar2 = CFG_AR2_PRELIM;
288 csctrl_reg->cr2 = CFG_CR2_PRELIM;
289 csctrl_reg->mr2 = CFG_MR2_PRELIM;
290#endif
291
292#if (defined(CFG_AR3_PRELIM) && defined(CFG_CR3_PRELIM) && defined(CFG_MR3_PRELIM))
293 csctrl_reg->ar3 = CFG_AR3_PRELIM;
294 csctrl_reg->cr3 = CFG_CR3_PRELIM;
295 csctrl_reg->mr3 = CFG_MR3_PRELIM;
296#endif
297
298#if (defined(CFG_AR4_PRELIM) && defined(CFG_CR4_PRELIM) && defined(CFG_MR4_PRELIM))
299 csctrl_reg->ar4 = CFG_AR4_PRELIM;
300 csctrl_reg->cr4 = CFG_CR4_PRELIM;
301 csctrl_reg->mr4 = CFG_MR4_PRELIM;
302#endif
303
304#if (defined(CFG_AR5_PRELIM) && defined(CFG_CR5_PRELIM) && defined(CFG_MR5_PRELIM))
305 csctrl_reg->ar5 = CFG_AR5_PRELIM;
306 csctrl_reg->cr5 = CFG_CR5_PRELIM;
307 csctrl_reg->mr5 = CFG_MR5_PRELIM;
308#endif
309
310#if (defined(CFG_AR6_PRELIM) && defined(CFG_CR6_PRELIM) && defined(CFG_MR6_PRELIM))
311 csctrl_reg->ar6 = CFG_AR6_PRELIM;
312 csctrl_reg->cr6 = CFG_CR6_PRELIM;
313 csctrl_reg->mr6 = CFG_MR6_PRELIM;
314#endif
315
316#if (defined(CFG_AR7_PRELIM) && defined(CFG_CR7_PRELIM) && defined(CFG_MR7_PRELIM))
317 csctrl_reg->ar7 = CFG_AR7_PRELIM;
318 csctrl_reg->cr7 = CFG_CR7_PRELIM;
319 csctrl_reg->mr7 = CFG_MR7_PRELIM;
320#endif
321
322#endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
323
324#ifdef CONFIG_FSL_I2C
325 gpio_reg->par_feci2c = 0x000F;
326#endif
327
328 /* enable instruction cache now */
329 icache_enable();
330}
331
332/*
333 * initialize higher level parts of CPU like timers
334 */
335int cpu_init_r(void)
336{
337 return (0);
338}
339
340void uart_port_conf(void)
341{
342 volatile gpio_t *gpio = (gpio_t *)MMAP_GPIO;
343
344 /* Setup Ports: */
345 switch (CFG_UART_PORT) {
346 case 0:
347 gpio->par_uart |= UART0_ENABLE_MASK;
348 break;
349 case 1:
350 gpio->par_uart |= UART1_ENABLE_MASK;
351 break;
352 case 2:
353 gpio->par_uart |= UART2_ENABLE_MASK;
354 break;
355 }
356}
357#endif /* #if defined(CONFIG_M5275) */
358
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500359#if defined(CONFIG_M5282)
wdenkbf9e3b32004-02-12 00:47:09 +0000360/*
361 * Breath some life into the CPU...
362 *
363 * Set up the memory map,
364 * initialize a bunch of registers,
365 * initialize the UPM's
366 */
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500367void cpu_init_f(void)
wdenkbf9e3b32004-02-12 00:47:09 +0000368{
Heiko Schocher9acb6262006-04-20 08:42:42 +0200369#ifndef CONFIG_WATCHDOG
370 /* disable watchdog if we aren't using it */
371 MCFWTM_WCR = 0;
372#endif
wdenkbf9e3b32004-02-12 00:47:09 +0000373
Heiko Schocher9acb6262006-04-20 08:42:42 +0200374#ifndef CONFIG_MONITOR_IS_IN_RAM
375 /* Set speed /PLL */
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500376 MCFCLOCK_SYNCR =
377 MCFCLOCK_SYNCR_MFD(CFG_MFD) | MCFCLOCK_SYNCR_RFD(CFG_RFD);
378 while (!(MCFCLOCK_SYNSR & MCFCLOCK_SYNSR_LOCK)) ;
379
380 MCFGPIO_PBCDPAR = 0xc0;
Heiko Schocher9acb6262006-04-20 08:42:42 +0200381
382 /* Set up the GPIO ports */
383#ifdef CFG_PEPAR
384 MCFGPIO_PEPAR = CFG_PEPAR;
385#endif
386#ifdef CFG_PFPAR
387 MCFGPIO_PFPAR = CFG_PFPAR;
388#endif
389#ifdef CFG_PJPAR
390 MCFGPIO_PJPAR = CFG_PJPAR;
391#endif
392#ifdef CFG_PSDPAR
393 MCFGPIO_PSDPAR = CFG_PSDPAR;
394#endif
395#ifdef CFG_PASPAR
396 MCFGPIO_PASPAR = CFG_PASPAR;
397#endif
398#ifdef CFG_PEHLPAR
399 MCFGPIO_PEHLPAR = CFG_PEHLPAR;
400#endif
401#ifdef CFG_PQSPAR
402 MCFGPIO_PQSPAR = CFG_PQSPAR;
403#endif
404#ifdef CFG_PTCPAR
405 MCFGPIO_PTCPAR = CFG_PTCPAR;
406#endif
407#ifdef CFG_PTDPAR
408 MCFGPIO_PTDPAR = CFG_PTDPAR;
409#endif
410#ifdef CFG_PUAPAR
411 MCFGPIO_PUAPAR = CFG_PUAPAR;
412#endif
413
414#ifdef CFG_DDRUA
415 MCFGPIO_DDRUA = CFG_DDRUA;
416#endif
417
418 /* This is probably a bad place to setup chip selects, but everyone
419 else is doing it! */
420
421#if defined(CFG_CS0_BASE) & defined(CFG_CS0_SIZE) & \
TsiChung Liew47bf9c72008-07-09 16:20:23 -0500422 defined(CFG_CS0_WIDTH) & defined(CFG_CS0_WS)
Heiko Schocher9acb6262006-04-20 08:42:42 +0200423
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500424 MCFCSM_CSAR0 = (CFG_CS0_BASE >> 16) & 0xFFFF;
Heiko Schocher9acb6262006-04-20 08:42:42 +0200425
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500426#if (CFG_CS0_WIDTH == 8)
427#define CFG_CS0_PS MCFCSM_CSCR_PS_8
428#elif (CFG_CS0_WIDTH == 16)
429#define CFG_CS0_PS MCFCSM_CSCR_PS_16
430#elif (CFG_CS0_WIDTH == 32)
431#define CFG_CS0_PS MCFCSM_CSCR_PS_32
Heiko Schocher9acb6262006-04-20 08:42:42 +0200432#else
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500433#error "CFG_CS0_WIDTH: Fault - wrong bus with for CS0"
434#endif
435 MCFCSM_CSCR0 = MCFCSM_CSCR_WS(CFG_CS0_WS)
436 | CFG_CS0_PS | MCFCSM_CSCR_AA;
437
438#if (CFG_CS0_RO != 0)
439 MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CFG_CS0_SIZE - 1)
440 | MCFCSM_CSMR_WP | MCFCSM_CSMR_V;
441#else
442 MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CFG_CS0_SIZE - 1) | MCFCSM_CSMR_V;
443#endif
444#else
445#waring "Chip Select 0 are not initialized/used"
Heiko Schocher9acb6262006-04-20 08:42:42 +0200446#endif
447
448#if defined(CFG_CS1_BASE) & defined(CFG_CS1_SIZE) & \
TsiChung Liew47bf9c72008-07-09 16:20:23 -0500449 defined(CFG_CS1_WIDTH) & defined(CFG_CS1_WS)
Heiko Schocher9acb6262006-04-20 08:42:42 +0200450
451 MCFCSM_CSAR1 = (CFG_CS1_BASE >> 16) & 0xFFFF;
452
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500453#if (CFG_CS1_WIDTH == 8)
454#define CFG_CS1_PS MCFCSM_CSCR_PS_8
455#elif (CFG_CS1_WIDTH == 16)
456#define CFG_CS1_PS MCFCSM_CSCR_PS_16
457#elif (CFG_CS1_WIDTH == 32)
458#define CFG_CS1_PS MCFCSM_CSCR_PS_32
Heiko Schocher9acb6262006-04-20 08:42:42 +0200459#else
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500460#error "CFG_CS1_WIDTH: Fault - wrong bus with for CS1"
461#endif
462 MCFCSM_CSCR1 = MCFCSM_CSCR_WS(CFG_CS1_WS)
463 | CFG_CS1_PS | MCFCSM_CSCR_AA;
464
465#if (CFG_CS1_RO != 0)
466 MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CFG_CS1_SIZE - 1)
467 | MCFCSM_CSMR_WP | MCFCSM_CSMR_V;
468#else
469 MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CFG_CS1_SIZE - 1)
470 | MCFCSM_CSMR_V;
471#endif
472#else
473#warning "Chip Select 1 are not initialized/used"
Heiko Schocher9acb6262006-04-20 08:42:42 +0200474#endif
475
476#if defined(CFG_CS2_BASE) & defined(CFG_CS2_SIZE) & \
TsiChung Liew47bf9c72008-07-09 16:20:23 -0500477 defined(CFG_CS2_WIDTH) & defined(CFG_CS2_WS)
Heiko Schocher9acb6262006-04-20 08:42:42 +0200478
479 MCFCSM_CSAR2 = (CFG_CS2_BASE >> 16) & 0xFFFF;
480
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500481#if (CFG_CS2_WIDTH == 8)
482#define CFG_CS2_PS MCFCSM_CSCR_PS_8
483#elif (CFG_CS2_WIDTH == 16)
484#define CFG_CS2_PS MCFCSM_CSCR_PS_16
485#elif (CFG_CS2_WIDTH == 32)
486#define CFG_CS2_PS MCFCSM_CSCR_PS_32
Heiko Schocher9acb6262006-04-20 08:42:42 +0200487#else
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500488#error "CFG_CS2_WIDTH: Fault - wrong bus with for CS2"
489#endif
490 MCFCSM_CSCR2 = MCFCSM_CSCR_WS(CFG_CS2_WS)
491 | CFG_CS2_PS | MCFCSM_CSCR_AA;
492
493#if (CFG_CS2_RO != 0)
494 MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CFG_CS2_SIZE - 1)
495 | MCFCSM_CSMR_WP | MCFCSM_CSMR_V;
496#else
497 MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CFG_CS2_SIZE - 1)
498 | MCFCSM_CSMR_V;
499#endif
500#else
501#warning "Chip Select 2 are not initialized/used"
Heiko Schocher9acb6262006-04-20 08:42:42 +0200502#endif
503
504#if defined(CFG_CS3_BASE) & defined(CFG_CS3_SIZE) & \
TsiChung Liew47bf9c72008-07-09 16:20:23 -0500505 defined(CFG_CS3_WIDTH) & defined(CFG_CS3_WS)
Heiko Schocher9acb6262006-04-20 08:42:42 +0200506
507 MCFCSM_CSAR3 = (CFG_CS3_BASE >> 16) & 0xFFFF;
508
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500509#if (CFG_CS3_WIDTH == 8)
510#define CFG_CS3_PS MCFCSM_CSCR_PS_8
511#elif (CFG_CS3_WIDTH == 16)
512#define CFG_CS3_PS MCFCSM_CSCR_PS_16
513#elif (CFG_CS3_WIDTH == 32)
514#define CFG_CS3_PS MCFCSM_CSCR_PS_32
Heiko Schocher9acb6262006-04-20 08:42:42 +0200515#else
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500516#error "CFG_CS3_WIDTH: Fault - wrong bus with for CS1"
517#endif
518 MCFCSM_CSCR3 = MCFCSM_CSCR_WS(CFG_CS3_WS)
519 | CFG_CS3_PS | MCFCSM_CSCR_AA;
520
521#if (CFG_CS3_RO != 0)
522 MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CFG_CS3_SIZE - 1)
523 | MCFCSM_CSMR_WP | MCFCSM_CSMR_V;
524#else
525 MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CFG_CS3_SIZE - 1)
526 | MCFCSM_CSMR_V;
527#endif
528#else
529#warning "Chip Select 3 are not initialized/used"
Heiko Schocher9acb6262006-04-20 08:42:42 +0200530#endif
531
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500532#endif /* CONFIG_MONITOR_IS_IN_RAM */
Heiko Schocher9acb6262006-04-20 08:42:42 +0200533
534 /* defer enabling cache until boot (see do_go) */
535 /* icache_enable(); */
wdenkbf9e3b32004-02-12 00:47:09 +0000536}
537
538/*
539 * initialize higher level parts of CPU like timers
540 */
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500541int cpu_init_r(void)
wdenkbf9e3b32004-02-12 00:47:09 +0000542{
543 return (0);
544}
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500545
546void uart_port_conf(void)
547{
548 /* Setup Ports: */
549 switch (CFG_UART_PORT) {
550 case 0:
551 MCFGPIO_PUAPAR &= 0xFc;
552 MCFGPIO_PUAPAR |= 0x03;
553 break;
554 case 1:
555 MCFGPIO_PUAPAR &= 0xF3;
556 MCFGPIO_PUAPAR |= 0x0C;
557 break;
558 case 2:
559 MCFGPIO_PASPAR &= 0xFF0F;
560 MCFGPIO_PASPAR |= 0x00A0;
561 break;
562 }
563}
wdenkbf9e3b32004-02-12 00:47:09 +0000564#endif
stroese8c725b92004-12-16 18:09:49 +0000565
566#if defined(CONFIG_M5249)
567/*
568 * Breath some life into the CPU...
569 *
570 * Set up the memory map,
571 * initialize a bunch of registers,
572 * initialize the UPM's
573 */
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500574void cpu_init_f(void)
stroese8c725b92004-12-16 18:09:49 +0000575{
stroese8c725b92004-12-16 18:09:49 +0000576 /*
577 * NOTE: by setting the GPIO_FUNCTION registers, we ensure that the UART pins
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500578 * (UART0: gpio 30,27, UART1: gpio 31, 28) will be used as UART pins
579 * which is their primary function.
580 * ~Jeremy
stroese8c725b92004-12-16 18:09:49 +0000581 */
582 mbar2_writeLong(MCFSIM_GPIO_FUNC, CFG_GPIO_FUNC);
583 mbar2_writeLong(MCFSIM_GPIO1_FUNC, CFG_GPIO1_FUNC);
584 mbar2_writeLong(MCFSIM_GPIO_EN, CFG_GPIO_EN);
585 mbar2_writeLong(MCFSIM_GPIO1_EN, CFG_GPIO1_EN);
586 mbar2_writeLong(MCFSIM_GPIO_OUT, CFG_GPIO_OUT);
587 mbar2_writeLong(MCFSIM_GPIO1_OUT, CFG_GPIO1_OUT);
588
589 /*
590 * dBug Compliance:
591 * You can verify these values by using dBug's 'ird'
592 * (Internal Register Display) command
593 * ~Jeremy
594 *
Wolfgang Denk977b50f2006-05-10 17:43:20 +0200595 */
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500596 mbar_writeByte(MCFSIM_MPARK, 0x30); /* 5249 Internal Core takes priority over DMA */
stroese8c725b92004-12-16 18:09:49 +0000597 mbar_writeByte(MCFSIM_SYPCR, 0x00);
598 mbar_writeByte(MCFSIM_SWIVR, 0x0f);
599 mbar_writeByte(MCFSIM_SWSR, 0x00);
600 mbar_writeLong(MCFSIM_IMR, 0xfffffbff);
601 mbar_writeByte(MCFSIM_SWDICR, 0x00);
602 mbar_writeByte(MCFSIM_TIMER1ICR, 0x00);
603 mbar_writeByte(MCFSIM_TIMER2ICR, 0x88);
604 mbar_writeByte(MCFSIM_I2CICR, 0x00);
605 mbar_writeByte(MCFSIM_UART1ICR, 0x00);
606 mbar_writeByte(MCFSIM_UART2ICR, 0x00);
607 mbar_writeByte(MCFSIM_ICR6, 0x00);
608 mbar_writeByte(MCFSIM_ICR7, 0x00);
609 mbar_writeByte(MCFSIM_ICR8, 0x00);
610 mbar_writeByte(MCFSIM_ICR9, 0x00);
611 mbar_writeByte(MCFSIM_QSPIICR, 0x00);
612
613 mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080);
Wolfgang Denk977b50f2006-05-10 17:43:20 +0200614 mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */
stroese8c725b92004-12-16 18:09:49 +0000615 mbar2_writeByte(MCFSIM_SPURVEC, 0x00);
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500616 mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); /* Enable a 1 cycle pre-drive cycle on CS1 */
stroese8c725b92004-12-16 18:09:49 +0000617
618 /* Setup interrupt priorities for gpio7 */
619 /* mbar2_writeLong(MCFSIM_INTLEV5, 0x70000000); */
620
621 /* IDE Config registers */
622 mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020);
623 mbar2_writeLong(MCFSIM_IDECONFIG2, 0x00000000);
624
625 /*
626 * Setup chip selects...
627 */
628
629 mbar_writeShort(MCFSIM_CSAR1, CFG_CSAR1);
630 mbar_writeShort(MCFSIM_CSCR1, CFG_CSCR1);
631 mbar_writeLong(MCFSIM_CSMR1, CFG_CSMR1);
632
633 mbar_writeShort(MCFSIM_CSAR0, CFG_CSAR0);
634 mbar_writeShort(MCFSIM_CSCR0, CFG_CSCR0);
635 mbar_writeLong(MCFSIM_CSMR0, CFG_CSMR0);
636
637 /* enable instruction cache now */
638 icache_enable();
639}
640
641/*
642 * initialize higher level parts of CPU like timers
643 */
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500644int cpu_init_r(void)
stroese8c725b92004-12-16 18:09:49 +0000645{
646 return (0);
647}
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500648
649void uart_port_conf(void)
650{
651 /* Setup Ports: */
652 switch (CFG_UART_PORT) {
653 case 0:
654 break;
655 case 1:
656 break;
657 }
658}
659#endif /* #if defined(CONFIG_M5249) */