blob: ec883a40447f9b55e2c25fce6c495ee087401ab0 [file] [log] [blame]
Heiko Schocher381e4e62008-01-11 01:12:06 +01001/*
2 * (C) Copyright 2007
3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
Heiko Schocher381e4e62008-01-11 01:12:06 +010023#include <common.h>
24#include <mpc8xx.h>
Heiko Schocher210c8c02008-11-21 08:29:40 +010025#include <net.h>
Heiko Schocher9e299192008-10-17 12:15:55 +020026#include <asm/io.h>
Heiko Schocher381e4e62008-01-11 01:12:06 +010027
28#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
29#include <libfdt.h>
30#endif
31
Heiko Schocher210c8c02008-11-21 08:29:40 +010032#include "../common/common.h"
Heiko Schocher8f64da72008-10-15 09:41:00 +020033
Heiko Schocher381e4e62008-01-11 01:12:06 +010034DECLARE_GLOBAL_DATA_PTR;
35
36const uint sdram_table[] =
37{
38 0x0f07fc04, 0x0ffffc04, 0x00bdfc04, 0x0ff77c00,
39 0x1ffffc05, 0xfffffc04, 0xfffffc04, 0xfffffc04,
40 /* 0x08 Burst Read */
41 0x0f07fc04, 0x0ffffc04, 0x00bdfc04, 0x00fffc00,
42 0x00fffc00, 0x00fffc00, 0x0ff77c00, 0x1ffffc05,
43 /* 0x10 Load mode register */
44 0x0ffffc34, 0x0ff57c04, 0x0ffffc04, 0x1ffffc05,
45 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
46 /* 0x18 Single Write */
47 0x0f07fc04, 0x0ffffc00, 0x00bd7c04, 0x0ffffc04,
48 0x0ff77c04, 0x1ffffc05, 0xfffffc04, 0xfffffc04,
49 /* 0x20 Burst Write */
50 0x0f07fc04, 0x0ffffc00, 0x00bd7c00, 0x00fffc00,
51 0x00fffc00, 0x00fffc04, 0x0ffffc04, 0x0ff77c04,
52 0x1ffffc05, 0xfffffc04, 0xfffffc04, 0xfffffc04,
53 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
54 /* 0x30 Precharge all and Refresh */
55 0x0ff77c04, 0x0ffffc04, 0x0ff5fc84, 0x0ffffc04,
56 0x0ffffc04, 0x0ffffc84, 0x1ffffc05, 0xfffffc04,
57 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
58 /* 0x3C Exception */
59 0x7ffffc04, 0xfffffc07, 0xfffffc04, 0xfffffc04,
60};
61
62int checkboard (void)
63{
Heiko Schocher1b6275d2009-03-12 07:37:34 +010064 puts ("Board: Keymile ");
65#if defined(CONFIG_KMSUPX4)
66 puts ("kmsupx4");
67#else
68 puts ("mgsuvd");
69#endif
Heiko Schocher210c8c02008-11-21 08:29:40 +010070 if (ethernet_present ())
71 puts (" with PIGGY.");
72 puts ("\n");
Heiko Schocher381e4e62008-01-11 01:12:06 +010073 return (0);
74}
75
Becky Bruce9973e3c2008-06-09 16:03:40 -050076phys_size_t initdram (int board_type)
Heiko Schocher381e4e62008-01-11 01:12:06 +010077{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020078 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
Heiko Schocher381e4e62008-01-11 01:12:06 +010079 volatile memctl8xx_t *memctl = &immap->im_memctl;
80 long int size;
81
82 upmconfig (UPMB, (uint *) sdram_table,
83 sizeof (sdram_table) / sizeof (uint));
84
85 /*
86 * Preliminary prescaler for refresh (depends on number of
87 * banks): This value is selected for four cycles every 62.4 us
88 * with two SDRAM banks or four cycles every 31.2 us with one
89 * bank. It will be adjusted after memory sizing.
90 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020091 memctl->memc_mptpr = CONFIG_SYS_MPTPR;
Heiko Schocher381e4e62008-01-11 01:12:06 +010092
93 /*
94 * The following value is used as an address (i.e. opcode) for
95 * the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If
96 * the port size is 32bit the SDRAM does NOT "see" the lower two
97 * address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for
98 * MICRON SDRAMs:
99 * -> 0 00 010 0 010
100 * | | | | +- Burst Length = 4
101 * | | | +----- Burst Type = Sequential
102 * | | +------- CAS Latency = 2
103 * | +----------- Operating Mode = Standard
104 * +-------------- Write Burst Mode = Programmed Burst Length
105 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200106 memctl->memc_mar = CONFIG_SYS_MAR;
Heiko Schocher381e4e62008-01-11 01:12:06 +0100107
108 /*
109 * Map controller banks 1 to the SDRAM banks 1 at
110 * preliminary addresses - these have to be modified after the
111 * SDRAM size has been determined.
112 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113 memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
114 memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
Heiko Schocher381e4e62008-01-11 01:12:06 +0100115
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116 memctl->memc_mbmr = CONFIG_SYS_MBMR & (~(MBMR_PTBE)); /* no refresh yet */
Heiko Schocher381e4e62008-01-11 01:12:06 +0100117
118 udelay (200);
119
120 /* perform SDRAM initializsation sequence */
121
122 memctl->memc_mcr = 0x80802830; /* SDRAM bank 0 */
123 udelay (1);
124 memctl->memc_mcr = 0x80802110; /* SDRAM bank 0 - execute twice */
125 udelay (1);
126
127 memctl->memc_mbmr |= MBMR_PTBE; /* enable refresh */
128
129 udelay (1000);
130
131 /*
132 * Check Bank 0 Memory Size for re-configuration
133 *
134 */
135 size = get_ram_size(SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
136
137 udelay (1000);
138
139 debug ("SDRAM Bank 0: %ld MB\n", size >> 20);
140
141 return (size);
142}
143
Heiko Schocher82afabf2008-03-07 08:15:28 +0100144/*
145 * Early board initalization.
146 */
147int board_early_init_r(void)
148{
149 /* setup the UPIOx */
Heiko Schocher9e299192008-10-17 12:15:55 +0200150 out_8((u8 *)(CONFIG_SYS_PIGGY_BASE + 0x02), 0xc0);
151 out_8((u8 *)(CONFIG_SYS_PIGGY_BASE + 0x03), 0x35);
Heiko Schocher82afabf2008-03-07 08:15:28 +0100152 return 0;
153}
154
Heiko Schocher8f64da72008-10-15 09:41:00 +0200155int hush_init_var (void)
156{
157 ivm_read_eeprom ();
158 return 0;
159}
160
Heiko Schocher381e4e62008-01-11 01:12:06 +0100161#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
162/*
163 * update "memory" property in the blob
164 */
Heiko Schochercac9cf72008-10-17 12:15:05 +0200165void ft_blob_update (void *blob, bd_t *bd)
Heiko Schocher381e4e62008-01-11 01:12:06 +0100166{
Heiko Schocher381e4e62008-01-11 01:12:06 +0100167 ulong brg_data[1] = {0};
168 ulong memory_data[2] = {0};
Heiko Schocherdc71b242009-07-09 12:04:18 +0200169 ulong *flash_data = NULL;
Heiko Schocherdf909552009-02-19 17:24:01 +0100170 ulong flash_reg[3] = {0};
Heiko Schocherdc71b242009-07-09 12:04:18 +0200171 flash_info_t *info;
172 int len;
173 int i = 0;
Heiko Schocher381e4e62008-01-11 01:12:06 +0100174
Heiko Schochercac9cf72008-10-17 12:15:05 +0200175 memory_data[0] = cpu_to_be32 (bd->bi_memstart);
176 memory_data[1] = cpu_to_be32 (bd->bi_memsize);
Heiko Schocher6250f0f2008-10-17 16:11:52 +0200177 fdt_set_node_and_value (blob, "/memory", "reg", memory_data,
178 sizeof (memory_data));
Heiko Schocher381e4e62008-01-11 01:12:06 +0100179
Heiko Schocherdc71b242009-07-09 12:04:18 +0200180 len = fdt_get_node_and_value (blob, "/localbus", "ranges",
181 (void *)&flash_data);
182
183 if (flash_data == NULL) {
184 printf ("%s: error /localbus/ranges entry\n", __FUNCTION__);
185 return;
186 }
187
188 /* update Flash addr, size */
189 while ( i < (len / 4)) {
190 switch (flash_data[i]) {
191 case 0:
192 info = flash_get_info(CONFIG_SYS_FLASH_BASE);
193 flash_data[i + 1] = 0;
194 flash_data[i + 2] = cpu_to_be32 (CONFIG_SYS_FLASH_BASE);
195 flash_data[i + 3] = cpu_to_be32 (info->size);
196 break;
197 default:
198 break;
199 }
200 i += 4;
201 }
Heiko Schocher6250f0f2008-10-17 16:11:52 +0200202 fdt_set_node_and_value (blob, "/localbus", "ranges", flash_data,
Heiko Schocherdc71b242009-07-09 12:04:18 +0200203 len);
Heiko Schocher6250f0f2008-10-17 16:11:52 +0200204
Heiko Schocherdf909552009-02-19 17:24:01 +0100205 flash_reg[2] = cpu_to_be32 (bd->bi_flashsize);
206 fdt_set_node_and_value (blob, "/localbus/flash@0,0", "reg", flash_reg,
207 sizeof (flash_reg));
Heiko Schocher381e4e62008-01-11 01:12:06 +0100208 /* BRG */
Heiko Schochercac9cf72008-10-17 12:15:05 +0200209 brg_data[0] = cpu_to_be32 (bd->bi_busfreq);
Heiko Schocher6250f0f2008-10-17 16:11:52 +0200210 fdt_set_node_and_value (blob, "/soc/cpm", "brg-frequency", brg_data,
211 sizeof (brg_data));
212
213 /* MAC adr */
214 fdt_set_node_and_value (blob, "/soc/cpm/ethernet", "mac-address",
Heiko Schocherdc71b242009-07-09 12:04:18 +0200215 bd->bi_enetaddr, sizeof (u8) * 6);
Heiko Schocher381e4e62008-01-11 01:12:06 +0100216}
217
218void ft_board_setup(void *blob, bd_t *bd)
219{
Heiko Schochercac9cf72008-10-17 12:15:05 +0200220 ft_cpu_setup (blob, bd);
221 ft_blob_update (blob, bd);
Heiko Schocher381e4e62008-01-11 01:12:06 +0100222}
223#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
Heiko Schocher9661bf92008-10-15 09:36:03 +0200224
225int i2c_soft_read_pin (void)
226{
227 int val;
228
229 *(unsigned short *)(I2C_BASE_DIR) &= ~SDA_CONF;
230 udelay(1);
231 val = *(unsigned char *)(I2C_BASE_PORT);
232
233 return ((val & SDA_BIT) == SDA_BIT);
234}