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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Stefan Roeseb0f80b92015-01-19 11:33:42 +01002/*
Stefan Roesea5f88872016-01-07 14:09:09 +01003 * Copyright (C) 2014-2016 Stefan Roese <sr@denx.de>
Stefan Roeseb0f80b92015-01-19 11:33:42 +01004 */
5
6#include <common.h>
Stefan Roese64512232015-11-25 07:37:00 +01007#include <dm.h>
8#include <debug_uart.h>
9#include <fdtdec.h>
Simon Glassdb41d652019-12-28 10:45:07 -070010#include <hang.h>
Simon Glass691d7192020-05-10 11:40:02 -060011#include <init.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060012#include <log.h>
Stefan Roeseb0f80b92015-01-19 11:33:42 +010013#include <spl.h>
Simon Glass401d1c42020-10-30 21:38:53 -060014#include <asm/global_data.h>
Stefan Roeseb0f80b92015-01-19 11:33:42 +010015#include <asm/io.h>
16#include <asm/arch/cpu.h>
17#include <asm/arch/soc.h>
18
Stefan Roesea5f88872016-01-07 14:09:09 +010019static u32 get_boot_device(void)
20{
21 u32 val;
22 u32 boot_device;
23
Stefan Roesef4db6c92016-01-07 14:12:04 +010024 /*
25 * First check, if UART boot-mode is active. This can only
26 * be done, via the bootrom error register. Here the
27 * MSB marks if the UART mode is active.
28 */
29 val = readl(CONFIG_BOOTROM_ERR_REG);
30 boot_device = (val & BOOTROM_ERR_MODE_MASK) >> BOOTROM_ERR_MODE_OFFS;
31 debug("BOOTROM_REG=0x%08x boot_device=0x%x\n", val, boot_device);
32 if (boot_device == BOOTROM_ERR_MODE_UART)
33 return BOOT_DEVICE_UART;
34
Chris Packham2fd42842018-08-17 20:47:42 +120035#ifdef CONFIG_ARMADA_38X
36 /*
37 * If the bootrom error code contains any other than zeros it's an
38 * error condition and the bootROM has fallen back to UART boot
39 */
40 boot_device = (val & BOOTROM_ERR_CODE_MASK) >> BOOTROM_ERR_CODE_OFFS;
41 if (boot_device)
42 return BOOT_DEVICE_UART;
43#endif
44
Stefan Roesef4db6c92016-01-07 14:12:04 +010045 /*
46 * Now check the SAR register for the strapped boot-device
47 */
Stefan Roesea5f88872016-01-07 14:09:09 +010048 val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */
49 boot_device = (val & BOOT_DEV_SEL_MASK) >> BOOT_DEV_SEL_OFFS;
Stefan Roesef4db6c92016-01-07 14:12:04 +010050 debug("SAR_REG=0x%08x boot_device=0x%x\n", val, boot_device);
Stefan Roesea5f88872016-01-07 14:09:09 +010051 switch (boot_device) {
Sean Nyekjaer926c8b22017-11-24 14:01:47 +010052#if defined(CONFIG_ARMADA_38X)
53 case BOOT_FROM_NAND:
54 return BOOT_DEVICE_NAND;
55#endif
Stefan Roesea5f88872016-01-07 14:09:09 +010056#ifdef CONFIG_SPL_MMC_SUPPORT
57 case BOOT_FROM_MMC:
58 case BOOT_FROM_MMC_ALT:
59 return BOOT_DEVICE_MMC1;
60#endif
61 case BOOT_FROM_UART:
Baruch Siachf3a88e22017-09-24 15:50:17 +030062#ifdef BOOT_FROM_UART_ALT
63 case BOOT_FROM_UART_ALT:
64#endif
Stefan Roesea5f88872016-01-07 14:09:09 +010065 return BOOT_DEVICE_UART;
Baruch Siach22c65452019-05-16 13:03:58 +030066#ifdef BOOT_FROM_SATA
67 case BOOT_FROM_SATA:
68 case BOOT_FROM_SATA_ALT:
69 return BOOT_DEVICE_SATA;
70#endif
Stefan Roesea5f88872016-01-07 14:09:09 +010071 case BOOT_FROM_SPI:
72 default:
73 return BOOT_DEVICE_SPI;
74 };
75}
76
Stefan Roeseb0f80b92015-01-19 11:33:42 +010077u32 spl_boot_device(void)
78{
Stefan Roesea5f88872016-01-07 14:09:09 +010079 return get_boot_device();
Stefan Roeseb0f80b92015-01-19 11:33:42 +010080}
81
82void board_init_f(ulong dummy)
83{
Stefan Roese64512232015-11-25 07:37:00 +010084 int ret;
85
Stefan Roesee3cccf92015-04-17 18:13:06 +020086 /*
87 * Pin muxing needs to be done before UART output, since
88 * on A38x the UART pins need some re-muxing for output
89 * to work.
90 */
91 board_early_init_f();
92
Stefan Roese64512232015-11-25 07:37:00 +010093 /* Example code showing how to enable the debug UART on MVEBU */
94#ifdef EARLY_UART
95 /*
96 * Debug UART can be used from here if required:
97 *
98 * debug_uart_init();
99 * printch('a');
100 * printhex8(0x1234);
101 * printascii("string");
102 */
103#endif
104
Stefan Roesef2100f62019-04-12 16:42:28 +0200105 /*
106 * Use special translation offset for SPL. This needs to be
107 * configured *before* spl_init() is called as this function
108 * calls dm_init() which calls the bind functions of the
109 * device drivers. Here the base address needs to be configured
110 * (translated) correctly.
111 */
112 gd->translation_offset = 0xd0000000 - 0xf1000000;
113
Stefan Roese64512232015-11-25 07:37:00 +0100114 ret = spl_init();
115 if (ret) {
116 debug("spl_init() failed: %d\n", ret);
117 hang();
118 }
119
Stefan Roeseb0f80b92015-01-19 11:33:42 +0100120 preloader_console_init();
121
Stefan Roeseade741b2015-07-15 15:36:52 +0200122 timer_init();
123
Stefan Roese09e89ab2016-02-10 07:23:00 +0100124 /* Armada 375 does not support SerDes and DDR3 init yet */
125#if !defined(CONFIG_ARMADA_375)
Stefan Roeseb0f80b92015-01-19 11:33:42 +0100126 /* First init the serdes PHY's */
127 serdes_phy_config();
128
129 /* Setup DDR */
130 ddr3_init();
Stefan Roese09e89ab2016-02-10 07:23:00 +0100131#endif
Stefan Roeseb0f80b92015-01-19 11:33:42 +0100132
Baruch Siachcc66ebd2019-07-10 18:23:04 +0300133 /* Initialize Auto Voltage Scaling */
134 mv_avs_init();
135
Chris Packhamad91fdf2020-02-26 19:53:50 +1300136 /* Update read timing control for PCIe */
137 mv_rtc_config();
138
Stefan Roese944c7a32015-08-25 13:49:41 +0200139 /*
140 * Return to the BootROM to continue the Marvell xmodem
141 * UART boot protocol. As initiated by the kwboot tool.
142 *
143 * This can only be done by the BootROM and not by the
144 * U-Boot SPL infrastructure, since the beginning of the
145 * image is already read and interpreted by the BootROM.
146 * SPL has no chance to receive this information. So we
147 * need to return to the BootROM to enable this xmodem
148 * UART download.
Sean Nyekjaer926c8b22017-11-24 14:01:47 +0100149 *
150 * If booting from NAND lets let the BootROM load the
151 * rest of the bootloader.
Stefan Roese944c7a32015-08-25 13:49:41 +0200152 */
Sean Nyekjaer926c8b22017-11-24 14:01:47 +0100153 switch (get_boot_device()) {
154 case BOOT_DEVICE_UART:
155#if defined(CONFIG_ARMADA_38X)
156 case BOOT_DEVICE_NAND:
157#endif
158 return_to_bootrom();
159 }
Stefan Roeseb0f80b92015-01-19 11:33:42 +0100160}