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wdenk3bac3512003-03-12 10:41:04 +00001/*
2 * (C) Copyright 2001-2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <mpc824x.h>
26#include <asm/processor.h>
27
28#if defined(CFG_ENV_IS_IN_FLASH)
29# ifndef CFG_ENV_ADDR
30# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET)
31# endif
32# ifndef CFG_ENV_SIZE
33# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE
34# endif
35# ifndef CFG_ENV_SECT_SIZE
36# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE
37# endif
38#endif
39
40#define FLASH_BANK_SIZE 0x800000
41#define MAIN_SECT_SIZE 0x40000
42#define PARAM_SECT_SIZE 0x8000
43
44flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
45
46static int write_data (flash_info_t *info, ulong dest, ulong *data);
47static void write_via_fpu(vu_long *addr, ulong *data);
48static __inline__ unsigned long get_msr(void);
49static __inline__ void set_msr(unsigned long msr);
50
51/*---------------------------------------------------------------------*/
52#undef DEBUG_FLASH
53
54/*---------------------------------------------------------------------*/
55#ifdef DEBUG_FLASH
56#define DEBUGF(fmt,args...) printf(fmt ,##args)
57#else
58#define DEBUGF(fmt,args...)
59#endif
60/*---------------------------------------------------------------------*/
61
62/*-----------------------------------------------------------------------
63 */
64
65unsigned long flash_init(void)
66{
67 int i, j;
68 ulong size = 0;
69 uchar tempChar;
70
71 /* Enable flash writes on CPC45 */
72
73 tempChar = BOARD_CTRL;
74
75 tempChar |= (B_CTRL_FWPT_1 | B_CTRL_FWRE_1);
76
77 tempChar &= ~(B_CTRL_FWPT_0 | B_CTRL_FWRE_0);
78
79 BOARD_CTRL = tempChar;
80
81
82 for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
wdenk8bde7f72003-06-27 21:31:46 +000083 vu_long *addr = (vu_long *)(CFG_FLASH_BASE + i * FLASH_BANK_SIZE);
wdenk3bac3512003-03-12 10:41:04 +000084
85 addr[0] = 0x00900090;
86
87 DEBUGF ("Flash bank # %d:\n"
88 "\tManuf. ID @ 0x%08lX: 0x%08lX\n"
89 "\tDevice ID @ 0x%08lX: 0x%08lX\n",
90 i,
91 (ulong)(&addr[0]), addr[0],
92 (ulong)(&addr[2]), addr[2]);
93
94
95 if ((addr[0] == addr[1]) && (addr[0] == INTEL_MANUFACT) &&
96 (addr[2] == addr[3]) && (addr[2] == INTEL_ID_28F160F3T))
97 {
98
99 flash_info[i].flash_id = (FLASH_MAN_INTEL & FLASH_VENDMASK) |
wdenk8bde7f72003-06-27 21:31:46 +0000100 (INTEL_ID_28F160F3T & FLASH_TYPEMASK);
wdenk3bac3512003-03-12 10:41:04 +0000101
102 } else {
103 flash_info[i].flash_id = FLASH_UNKNOWN;
104 addr[0] = 0xFFFFFFFF;
105 goto Done;
106 }
107
108 DEBUGF ("flash_id = 0x%08lX\n", flash_info[i].flash_id);
109
110 addr[0] = 0xFFFFFFFF;
111
112 flash_info[i].size = FLASH_BANK_SIZE;
113 flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
114 memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
115 for (j = 0; j < flash_info[i].sector_count; j++) {
116 if (j > 30) {
117 flash_info[i].start[j] = CFG_FLASH_BASE +
wdenk8bde7f72003-06-27 21:31:46 +0000118 i * FLASH_BANK_SIZE +
119 (MAIN_SECT_SIZE * 31) + (j - 31) * PARAM_SECT_SIZE;
wdenk3bac3512003-03-12 10:41:04 +0000120 } else {
121 flash_info[i].start[j] = CFG_FLASH_BASE +
wdenk8bde7f72003-06-27 21:31:46 +0000122 i * FLASH_BANK_SIZE +
123 j * MAIN_SECT_SIZE;
wdenk3bac3512003-03-12 10:41:04 +0000124 }
125 }
126 size += flash_info[i].size;
127 }
128
129 /* Protect monitor and environment sectors
130 */
131#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
132#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + FLASH_BANK_SIZE
133 flash_protect(FLAG_PROTECT_SET,
wdenk8bde7f72003-06-27 21:31:46 +0000134 CFG_MONITOR_BASE,
135 CFG_MONITOR_BASE + monitor_flash_len - 1,
136 &flash_info[1]);
wdenk3bac3512003-03-12 10:41:04 +0000137#else
138 flash_protect(FLAG_PROTECT_SET,
wdenk8bde7f72003-06-27 21:31:46 +0000139 CFG_MONITOR_BASE,
140 CFG_MONITOR_BASE + monitor_flash_len - 1,
141 &flash_info[0]);
wdenk3bac3512003-03-12 10:41:04 +0000142#endif
143#endif
144
145#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR)
146#if CFG_ENV_ADDR >= CFG_FLASH_BASE + FLASH_BANK_SIZE
147 flash_protect(FLAG_PROTECT_SET,
wdenk8bde7f72003-06-27 21:31:46 +0000148 CFG_ENV_ADDR,
149 CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
150 &flash_info[1]);
wdenk3bac3512003-03-12 10:41:04 +0000151#else
152 flash_protect(FLAG_PROTECT_SET,
wdenk8bde7f72003-06-27 21:31:46 +0000153 CFG_ENV_ADDR,
154 CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
155 &flash_info[0]);
wdenk3bac3512003-03-12 10:41:04 +0000156#endif
157#endif
158
159Done:
160 return size;
161}
162
163/*-----------------------------------------------------------------------
164 */
165void flash_print_info (flash_info_t * info)
166{
167 int i;
168
169 switch ((i = info->flash_id & FLASH_VENDMASK)) {
170 case (FLASH_MAN_INTEL & FLASH_VENDMASK):
171 printf ("Intel: ");
172 break;
173 default:
174 printf ("Unknown Vendor 0x%04x ", i);
175 break;
176 }
177
178 switch ((i = info->flash_id & FLASH_TYPEMASK)) {
179 case (INTEL_ID_28F160F3T & FLASH_TYPEMASK):
180 printf ("28F160F3T (16Mbit)\n");
181 break;
182 default:
183 printf ("Unknown Chip Type 0x%04x\n", i);
184 goto Done;
185 break;
186 }
187
188 printf (" Size: %ld MB in %d Sectors\n",
189 info->size >> 20, info->sector_count);
190
191 printf (" Sector Start Addresses:");
192 for (i = 0; i < info->sector_count; i++) {
193 if ((i % 5) == 0) {
194 printf ("\n ");
195 }
196 printf (" %08lX%s", info->start[i],
197 info->protect[i] ? " (RO)" : " ");
198 }
199 printf ("\n");
200
201Done:
202 return;
203}
204
205/*-----------------------------------------------------------------------
206 */
207
208int flash_erase (flash_info_t *info, int s_first, int s_last)
209{
210 int flag, prot, sect;
211 ulong start, now, last;
212
213 DEBUGF ("Erase flash bank %d sect %d ... %d\n",
214 info - &flash_info[0], s_first, s_last);
215
216 if ((s_first < 0) || (s_first > s_last)) {
217 if (info->flash_id == FLASH_UNKNOWN) {
218 printf ("- missing\n");
219 } else {
220 printf ("- no sectors to erase\n");
221 }
222 return 1;
223 }
224
225 if ((info->flash_id & FLASH_VENDMASK) !=
226 (FLASH_MAN_INTEL & FLASH_VENDMASK)) {
227 printf ("Can erase only Intel flash types - aborted\n");
228 return 1;
229 }
230
231 prot = 0;
232 for (sect=s_first; sect<=s_last; ++sect) {
233 if (info->protect[sect]) {
234 prot++;
235 }
236 }
237
238 if (prot) {
239 printf ("- Warning: %d protected sectors will not be erased!\n",
240 prot);
241 } else {
242 printf ("\n");
243 }
244
245 start = get_timer (0);
246 last = start;
247 /* Start erase on unprotected sectors */
248 for (sect = s_first; sect<=s_last; sect++) {
249 if (info->protect[sect] == 0) { /* not protected */
250 vu_long *addr = (vu_long *)(info->start[sect]);
251
252 DEBUGF ("Erase sect %d @ 0x%08lX\n",
253 sect, (ulong)addr);
254
255 /* Disable interrupts which might cause a timeout
256 * here.
257 */
258 flag = disable_interrupts();
259
260 addr[0] = 0x00500050; /* clear status register */
261 addr[0] = 0x00200020; /* erase setup */
262 addr[0] = 0x00D000D0; /* erase confirm */
263
264 addr[1] = 0x00500050; /* clear status register */
265 addr[1] = 0x00200020; /* erase setup */
266 addr[1] = 0x00D000D0; /* erase confirm */
267
268 /* re-enable interrupts if necessary */
269 if (flag)
270 enable_interrupts();
271
272 /* wait at least 80us - let's wait 1 ms */
273 udelay (1000);
274
275 while (((addr[0] & 0x00800080) != 0x00800080) ||
276 ((addr[1] & 0x00800080) != 0x00800080) ) {
277 if ((now=get_timer(start)) >
wdenk8bde7f72003-06-27 21:31:46 +0000278 CFG_FLASH_ERASE_TOUT) {
wdenk3bac3512003-03-12 10:41:04 +0000279 printf ("Timeout\n");
280 addr[0] = 0x00B000B0; /* suspend erase */
281 addr[0] = 0x00FF00FF; /* to read mode */
282 return 1;
283 }
284
285 /* show that we're waiting */
286 if ((now - last) > 1000) { /* every second */
287 putc ('.');
288 last = now;
289 }
290 }
291
292 addr[0] = 0x00FF00FF;
293 }
294 }
295 printf (" done\n");
296 return 0;
297}
298
299/*-----------------------------------------------------------------------
300 * Copy memory to flash, returns:
301 * 0 - OK
302 * 1 - write timeout
303 * 2 - Flash not erased
304 * 4 - Flash not identified
305 */
306
307#define FLASH_WIDTH 8 /* flash bus width in bytes */
308
309int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
310{
311 ulong wp, cp, msr;
312 int l, rc, i;
313 ulong data[2];
314 ulong *datah = &data[0];
315 ulong *datal = &data[1];
316
317 DEBUGF ("Flash write_buff: @ 0x%08lx, src 0x%08lx len %ld\n",
318 addr, (ulong)src, cnt);
319
320 if (info->flash_id == FLASH_UNKNOWN) {
321 return 4;
322 }
323
324 msr = get_msr();
325 set_msr(msr | MSR_FP);
326
327 wp = (addr & ~(FLASH_WIDTH-1)); /* get lower aligned address */
328
329 /*
330 * handle unaligned start bytes
331 */
332 if ((l = addr - wp) != 0) {
333 *datah = *datal = 0;
334
335 for (i = 0, cp = wp; i < l; i++, cp++) {
336 if (i >= 4) {
337 *datah = (*datah << 8) |
wdenk8bde7f72003-06-27 21:31:46 +0000338 ((*datal & 0xFF000000) >> 24);
wdenk3bac3512003-03-12 10:41:04 +0000339 }
340
341 *datal = (*datal << 8) | (*(uchar *)cp);
342 }
343 for (; i < FLASH_WIDTH && cnt > 0; ++i) {
344 char tmp;
345
346 tmp = *src;
347
348 src++;
349
350 if (i >= 4) {
351 *datah = (*datah << 8) |
wdenk8bde7f72003-06-27 21:31:46 +0000352 ((*datal & 0xFF000000) >> 24);
wdenk3bac3512003-03-12 10:41:04 +0000353 }
354
355 *datal = (*datal << 8) | tmp;
356
357 --cnt; ++cp;
358 }
359
360 for (; cnt == 0 && i < FLASH_WIDTH; ++i, ++cp) {
361 if (i >= 4) {
362 *datah = (*datah << 8) |
wdenk8bde7f72003-06-27 21:31:46 +0000363 ((*datal & 0xFF000000) >> 24);
wdenk3bac3512003-03-12 10:41:04 +0000364 }
365
366 *datal = (*datah << 8) | (*(uchar *)cp);
367 }
368
369 if ((rc = write_data(info, wp, data)) != 0) {
370 set_msr(msr);
371 return (rc);
372 }
373
374 wp += FLASH_WIDTH;
375 }
376
377 /*
378 * handle FLASH_WIDTH aligned part
379 */
380 while (cnt >= FLASH_WIDTH) {
381 *datah = *(ulong *)src;
382 *datal = *(ulong *)(src + 4);
383 if ((rc = write_data(info, wp, data)) != 0) {
384 set_msr(msr);
385 return (rc);
386 }
387 wp += FLASH_WIDTH;
388 cnt -= FLASH_WIDTH;
389 src += FLASH_WIDTH;
390 }
391
392 if (cnt == 0) {
393 set_msr(msr);
394 return (0);
395 }
396
397 /*
398 * handle unaligned tail bytes
399 */
400 *datah = *datal = 0;
401 for (i = 0, cp = wp; i < FLASH_WIDTH && cnt > 0; ++i, ++cp) {
402 char tmp;
403
wdenk8bde7f72003-06-27 21:31:46 +0000404 tmp = *src;
wdenk3bac3512003-03-12 10:41:04 +0000405
406 src++;
407
408 if (i >= 4) {
409 *datah = (*datah << 8) | ((*datal & 0xFF000000) >> 24);
410 }
411
412 *datal = (*datal << 8) | tmp;
413
414 --cnt;
415 }
416
417 for (; i < FLASH_WIDTH; ++i, ++cp) {
418 if (i >= 4) {
419 *datah = (*datah << 8) | ((*datal & 0xFF000000) >> 24);
420 }
421
422 *datal = (*datal << 8) | (*(uchar *)cp);
423 }
424
425 rc = write_data(info, wp, data);
426 set_msr(msr);
427
428 return (rc);
429}
430
431/*-----------------------------------------------------------------------
432 * Write a word to Flash, returns:
433 * 0 - OK
434 * 1 - write timeout
435 * 2 - Flash not erased
436 */
437static int write_data (flash_info_t *info, ulong dest, ulong *data)
438{
439 vu_long *addr = (vu_long *)dest;
440 ulong start;
441 int flag;
442
443 /* Check if Flash is (sufficiently) erased */
444 if (((addr[0] & data[0]) != data[0]) ||
445 ((addr[1] & data[1]) != data[1]) ) {
446 return (2);
447 }
448 /* Disable interrupts which might cause a timeout here */
449 flag = disable_interrupts();
450
451 addr[0] = 0x00400040; /* write setup */
452 write_via_fpu(addr, data);
453
454 /* re-enable interrupts if necessary */
455 if (flag)
456 enable_interrupts();
457
458 start = get_timer (0);
459
460 while (((addr[0] & 0x00800080) != 0x00800080) ||
461 ((addr[1] & 0x00800080) != 0x00800080) ) {
462 if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
463 addr[0] = 0x00FF00FF; /* restore read mode */
464 return (1);
465 }
466 }
467
468 addr[0] = 0x00FF00FF; /* restore read mode */
469
470 return (0);
471}
472
473/*-----------------------------------------------------------------------
474 */
475static void write_via_fpu(vu_long *addr, ulong *data)
476{
477 __asm__ __volatile__ ("lfd 1, 0(%0)" : : "r" (data));
478 __asm__ __volatile__ ("stfd 1, 0(%0)" : : "r" (addr));
479}
480/*-----------------------------------------------------------------------
481 */
482static __inline__ unsigned long get_msr(void)
483{
484 unsigned long msr;
485
486 __asm__ __volatile__ ("mfmsr %0" : "=r" (msr) :);
487 return msr;
488}
489
490static __inline__ void set_msr(unsigned long msr)
491{
492 __asm__ __volatile__ ("mtmsr %0" : : "r" (msr));
493}