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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Chin Liang Seeddfeb0a2014-03-04 22:13:53 -06002/*
Ley Foon Tande778112017-04-26 02:44:33 +08003 * Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
Chin Liang Seeddfeb0a2014-03-04 22:13:53 -06004 */
5
6#include <common.h>
Ley Foon Tande778112017-04-26 02:44:33 +08007#include <wait_bit.h>
Chin Liang Seeddfeb0a2014-03-04 22:13:53 -06008#include <asm/io.h>
9#include <asm/arch/clock_manager.h>
10
Pavel Macheka832ddb2014-09-08 14:08:45 +020011DECLARE_GLOBAL_DATA_PTR;
12
Chin Liang Seeddfeb0a2014-03-04 22:13:53 -060013static const struct socfpga_clock_manager *clock_manager_base =
Pavel Macheka832ddb2014-09-08 14:08:45 +020014 (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
Chin Liang Seeddfeb0a2014-03-04 22:13:53 -060015
Ley Foon Tande778112017-04-26 02:44:33 +080016void cm_wait_for_lock(u32 mask)
Chin Liang Seeddfeb0a2014-03-04 22:13:53 -060017{
Ley Foon Tande778112017-04-26 02:44:33 +080018 u32 inter_val;
19 u32 retry = 0;
Chin Liang Seeddfeb0a2014-03-04 22:13:53 -060020 do {
Ley Foon Tan177ba1f2017-04-26 02:44:39 +080021#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
Chin Liang Seeddfeb0a2014-03-04 22:13:53 -060022 inter_val = readl(&clock_manager_base->inter) & mask;
Ley Foon Tan508791a2018-05-18 22:05:22 +080023#else
Ley Foon Tan177ba1f2017-04-26 02:44:39 +080024 inter_val = readl(&clock_manager_base->stat) & mask;
25#endif
26 /* Wait for stable lock */
Marek Vasut036ba542014-09-16 19:54:32 +020027 if (inter_val == mask)
28 retry++;
29 else
30 retry = 0;
31 if (retry >= 10)
32 break;
33 } while (1);
Chin Liang Seeddfeb0a2014-03-04 22:13:53 -060034}
35
36/* function to poll in the fsm busy bit */
Ley Foon Tande778112017-04-26 02:44:33 +080037int cm_wait_for_fsm(void)
Chin Liang Seeddfeb0a2014-03-04 22:13:53 -060038{
Álvaro Fernández Rojas48263502018-01-23 17:14:55 +010039 return wait_for_bit_le32(&clock_manager_base->stat,
40 CLKMGR_STAT_BUSY, false, 20000, false);
Pavel Macheka832ddb2014-09-08 14:08:45 +020041}
42
43int set_cpu_clk_info(void)
44{
45 /* Calculate the clock frequencies required for drivers */
46 cm_get_l4_sp_clk_hz();
47 cm_get_mmc_controller_clk_hz();
48
49 gd->bd->bi_arm_freq = cm_get_mpu_clk_hz() / 1000000;
50 gd->bd->bi_dsp_freq = 0;
Ley Foon Tan177ba1f2017-04-26 02:44:39 +080051
52#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
Pavel Macheka832ddb2014-09-08 14:08:45 +020053 gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 1000000;
Ley Foon Tan508791a2018-05-18 22:05:22 +080054#else
Ley Foon Tan177ba1f2017-04-26 02:44:39 +080055 gd->bd->bi_ddr_freq = 0;
56#endif
Pavel Macheka832ddb2014-09-08 14:08:45 +020057
58 return 0;
59}
60
Tom Rinib4b98142017-12-22 12:19:22 -050061#ifndef CONFIG_SPL_BUILD
62static int do_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
Pavel Macheka832ddb2014-09-08 14:08:45 +020063{
64 cm_print_clock_quick_summary();
65 return 0;
66}
67
68U_BOOT_CMD(
69 clocks, CONFIG_SYS_MAXARGS, 1, do_showclocks,
70 "display clocks",
71 ""
72);
Tom Rinib4b98142017-12-22 12:19:22 -050073#endif