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wdenk4a9cbbe2002-08-27 09:48:53 +00001/*
2 * (C) Copyright 2000
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <watchdog.h>
26#include <405gp_enet.h>
27#include <asm/processor.h>
28#include <ppc4xx.h>
29
30
31#define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data)
32
33
34/*
35 * Breath some life into the CPU...
36 *
37 * Set up the memory map,
38 * initialize a bunch of registers
39 */
40void
41cpu_init_f (void)
42{
43 /*
44 * External Bus Controller (EBC) Setup
45 */
46#if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
47 /*
48 * Move the next instructions into icache, since these modify the flash
49 * we are running from!
50 */
51 asm volatile(" bl 0f" ::: "lr");
52 asm volatile("0: mflr 3" ::: "r3");
53 asm volatile(" addi 4, 0, 14" ::: "r4");
54 asm volatile(" mtctr 4" ::: "ctr");
55 asm volatile("1: icbt 0, 3");
56 asm volatile(" addi 3, 3, 32" ::: "r3");
57 asm volatile(" bdnz 1b" ::: "ctr", "cr0");
58 asm volatile(" addis 3, 0, 0x0" ::: "r3");
59 asm volatile(" ori 3, 3, 0xA000" ::: "r3");
60 asm volatile(" mtctr 3" ::: "ctr");
61 asm volatile("2: bdnz 2b" ::: "ctr", "cr0");
62
63 mtebc(pb0ap, CFG_EBC_PB0AP);
64 mtebc(pb0cr, CFG_EBC_PB0CR);
65#endif
66
67#if (defined(CFG_EBC_PB1AP) && defined(CFG_EBC_PB1CR))
68 mtebc(pb1ap, CFG_EBC_PB1AP);
69 mtebc(pb1cr, CFG_EBC_PB1CR);
70#endif
71
72#if (defined(CFG_EBC_PB2AP) && defined(CFG_EBC_PB2CR))
73 mtebc(pb2ap, CFG_EBC_PB2AP);
74 mtebc(pb2cr, CFG_EBC_PB2CR);
75#endif
76
77#if (defined(CFG_EBC_PB3AP) && defined(CFG_EBC_PB3CR))
78 mtebc(pb3ap, CFG_EBC_PB3AP);
79 mtebc(pb3cr, CFG_EBC_PB3CR);
80#endif
81
82#if (defined(CFG_EBC_PB4AP) && defined(CFG_EBC_PB4CR))
83 mtebc(pb4ap, CFG_EBC_PB4AP);
84 mtebc(pb4cr, CFG_EBC_PB4CR);
85#endif
86
87#if (defined(CFG_EBC_PB5AP) && defined(CFG_EBC_PB5CR))
88 mtebc(pb5ap, CFG_EBC_PB5AP);
89 mtebc(pb5cr, CFG_EBC_PB5CR);
90#endif
91
92#if (defined(CFG_EBC_PB6AP) && defined(CFG_EBC_PB6CR))
93 mtebc(pb6ap, CFG_EBC_PB6AP);
94 mtebc(pb6cr, CFG_EBC_PB6CR);
95#endif
96
97#if (defined(CFG_EBC_PB7AP) && defined(CFG_EBC_PB7CR))
98 mtebc(pb7ap, CFG_EBC_PB7AP);
99 mtebc(pb7cr, CFG_EBC_PB7CR);
100#endif
101
102#if defined(CONFIG_WATCHDOG)
103 unsigned long val;
104
105 val = mfspr(tcr);
106 val |= 0xf0000000; /* generate system reset after 2.684 seconds */
107 mtspr(tcr, val);
108
109 val = mfspr(tsr);
110 val |= 0x80000000; /* enable watchdog timer */
111 mtspr(tsr, val);
112
113 reset_4xx_watchdog();
114#endif /* CONFIG_WATCHDOG */
115}
116
117/*
118 * initialize higher level parts of CPU like time base and timers
119 */
120int cpu_init_r (void)
121{
122#ifdef CONFIG_405GP
123 DECLARE_GLOBAL_DATA_PTR;
124
125 bd_t *bd = gd->bd;
126 unsigned long reg;
127
128 /*
129 * Write Ethernetaddress into on-chip register
130 */
131 reg = 0x00000000;
132 reg |= bd->bi_enetaddr[0]; /* set high address */
133 reg = reg << 8;
134 reg |= bd->bi_enetaddr[1];
135 out32 (EMAC_IAH, reg);
136
137 reg = 0x00000000;
138 reg |= bd->bi_enetaddr[2]; /* set low address */
139 reg = reg << 8;
140 reg |= bd->bi_enetaddr[3];
141 reg = reg << 8;
142 reg |= bd->bi_enetaddr[4];
143 reg = reg << 8;
144 reg |= bd->bi_enetaddr[5];
145 out32 (EMAC_IAL, reg);
146#endif /* CONFIG_405GP */
147 return (0);
148}