blob: b18127c4d18c596bfc103379a383ebe5eb6c5c7a [file] [log] [blame]
Michael Walle4ceb5c62020-10-15 23:08:57 +02001// SPDX-License-Identifier: GPL-2.0+
2
3#include <common.h>
4#include <malloc.h>
5#include <errno.h>
6#include <fsl_ddr.h>
7#include <fdt_support.h>
8#include <linux/libfdt.h>
9#include <env_internal.h>
10#include <asm/arch-fsl-layerscape/soc.h>
11#include <asm/arch-fsl-layerscape/fsl_icid.h>
12#include <i2c.h>
13#include <asm/arch/soc.h>
14#include <fsl_immap.h>
15#include <netdev.h>
16
17#include <fdtdec.h>
18#include <miiphy.h>
19
20DECLARE_GLOBAL_DATA_PTR;
21
22int board_init(void)
23{
24 if (CONFIG_IS_ENABLED(FSL_CAAM))
25 sec_init();
26
27 return 0;
28}
29
30int board_eth_init(struct bd_info *bis)
31{
32 return pci_eth_init(bis);
33}
34
35int checkboard(void)
36{
37 printf("EL: %d\n", current_el());
38 return 0;
39}
40
41void detail_board_ddr_info(void)
42{
43 puts("\nDDR ");
44 print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
45 print_ddr_info(0);
46}
47
48int ft_board_setup(void *blob, struct bd_info *bd)
49{
50 u64 base[CONFIG_NR_DRAM_BANKS];
51 u64 size[CONFIG_NR_DRAM_BANKS];
52 int nbanks = CONFIG_NR_DRAM_BANKS;
53 int i;
54
55 ft_cpu_setup(blob, bd);
56
57 /* fixup DT for the two GPP DDR banks */
58 for (i = 0; i < nbanks; i++) {
59 base[i] = gd->bd->bi_dram[i].start;
60 size[i] = gd->bd->bi_dram[i].size;
61 }
62
63 fdt_fixup_memory_banks(blob, base, size, nbanks);
64
65 fdt_fixup_icid(blob);
66
67 return 0;
68}