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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Heiko Schocher4e43b2e2010-07-07 12:26:34 +02002/*
3 * Copyright (C) Freescale Semiconductor, Inc. 2006-2007
4 *
5 * Author: Scott Wood <scottwood@freescale.com>
6 *
7 * (C) Copyright 2010
8 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
Heiko Schocher4e43b2e2010-07-07 12:26:34 +02009 */
10
11#include <common.h>
Simon Glass2cf431c2019-11-14 12:57:47 -070012#include <init.h>
Masahiro Yamadab08c8c42018-03-05 01:20:11 +090013#include <linux/libfdt.h>
Heiko Schocher4e43b2e2010-07-07 12:26:34 +020014#include <pci.h>
15#include <mpc83xx.h>
16#include <ns16550.h>
17#include <nand.h>
18
19#include <asm/bitops.h>
20#include <asm/io.h>
21
22DECLARE_GLOBAL_DATA_PTR;
23
24extern void disable_addr_trans (void);
25extern void enable_addr_trans (void);
26
27int checkboard(void)
28{
29 puts("Board: ve8313\n");
30 return 0;
31}
32
33static long fixed_sdram(void)
34{
35 u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
36
37#ifndef CONFIG_SYS_RAMBOOT
38 volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
39 u32 msize_log2 = __ilog2(msize);
40
41 out_be32(&im->sysconf.ddrlaw[0].bar,
Mario Six133ec602019-01-21 09:18:16 +010042 (CONFIG_SYS_SDRAM_BASE & 0xfffff000));
Heiko Schocher4e43b2e2010-07-07 12:26:34 +020043 out_be32(&im->sysconf.ddrlaw[0].ar, (LBLAWAR_EN | (msize_log2 - 1)));
44 out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
45
46 /*
47 * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
48 * or the DDR2 controller may fail to initialize correctly.
49 */
50 __udelay(50000);
51
Mario Six133ec602019-01-21 09:18:16 +010052#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
Joe Hershberger2e651b22011-10-11 23:57:31 -050053#warning Chip select bounds is only configurable in 16MB increments
54#endif
55 out_be32(&im->ddr.csbnds[0].csbnds,
Mario Six133ec602019-01-21 09:18:16 +010056 ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
57 (((CONFIG_SYS_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) &
Joe Hershberger2e651b22011-10-11 23:57:31 -050058 CSBNDS_EA));
59 out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
Heiko Schocher4e43b2e2010-07-07 12:26:34 +020060
61 /* Currently we use only one CS, so disable the other bank. */
62 out_be32(&im->ddr.cs_config[1], 0);
63
64 out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL);
65 out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
66 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
67 out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
68 out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
69
70 out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_SDRAM_CFG);
71
72 out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_SDRAM_CFG2);
73 out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
74 out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE_2);
75
76 out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
77 sync();
78
79 /* enable DDR controller */
80 setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
81
82 /* now check the real size */
83 disable_addr_trans ();
Mario Six8a81bfd2019-01-21 09:18:15 +010084 msize = get_ram_size (CONFIG_SYS_SDRAM_BASE, msize);
Heiko Schocher4e43b2e2010-07-07 12:26:34 +020085 enable_addr_trans ();
86#endif
87
88 return msize;
89}
90
Simon Glassf1683aa2017-04-06 12:47:05 -060091int dram_init(void)
Heiko Schocher4e43b2e2010-07-07 12:26:34 +020092{
93 volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
Kumar Galaa2243b82010-08-19 01:48:14 -050094 volatile fsl_lbc_t *lbc = &im->im_lbc;
Heiko Schocher4e43b2e2010-07-07 12:26:34 +020095 u32 msize;
96
97 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
98 return -1;
99
100 /* DDR SDRAM - Main SODIMM */
101 msize = fixed_sdram();
102
103 /* Local Bus setup lbcr and mrtpr */
Mario Six42c9a492019-01-21 09:18:17 +0100104 out_be32(&lbc->lbcr, 0x00040000);
105 out_be32(&lbc->mrtpr, 0x20000000);
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200106 sync();
107
108 /* return total bus SDRAM size(bytes) -- DDR */
Simon Glass088454c2017-03-31 08:40:25 -0600109 gd->ram_size = msize;
110
111 return 0;
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200112}
113
114#define VE8313_WDT_EN 0x00020000
115#define VE8313_WDT_TRIG 0x00040000
116
117int board_early_init_f (void)
118{
119 volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
120 volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)im->gpio;
121
122#if defined(CONFIG_HW_WATCHDOG)
123 /* enable WDT */
124 clrbits_be32(&gpio->dat, VE8313_WDT_EN | VE8313_WDT_TRIG);
125#else
126 /* disable WDT */
127 setbits_be32(&gpio->dat, VE8313_WDT_EN | VE8313_WDT_TRIG);
128#endif
129 /* set WDT pins as output */
130 setbits_be32(&gpio->dir, VE8313_WDT_EN | VE8313_WDT_TRIG);
131
132 return 0;
133}
134
135#if defined(CONFIG_HW_WATCHDOG)
136void hw_watchdog_reset(void)
137{
138 volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
139 volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)im->gpio;
140 unsigned long reg;
141
142 reg = in_be32(&gpio->dat);
143 if (reg & VE8313_WDT_TRIG)
144 clrbits_be32(&gpio->dat, VE8313_WDT_TRIG);
145 else
146 setbits_be32(&gpio->dat, VE8313_WDT_TRIG);
147}
148#endif
149
150
151#if defined(CONFIG_PCI)
152static struct pci_region pci_regions[] = {
153 {
154 bus_start: CONFIG_SYS_PCI1_MEM_BASE,
155 phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
156 size: CONFIG_SYS_PCI1_MEM_SIZE,
157 flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
158 },
159 {
160 bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
161 phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
162 size: CONFIG_SYS_PCI1_MMIO_SIZE,
163 flags: PCI_REGION_MEM
164 },
165 {
166 bus_start: CONFIG_SYS_PCI1_IO_BASE,
167 phys_start: CONFIG_SYS_PCI1_IO_PHYS,
168 size: CONFIG_SYS_PCI1_IO_SIZE,
169 flags: PCI_REGION_IO
170 }
171};
172
173void pci_init_board(void)
174{
175 volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
176 volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
177 volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
178 struct pci_region *reg[] = { pci_regions };
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200179
180 /* Enable all 3 PCI_CLK_OUTPUTs. */
181 setbits_be32(&clk->occr, 0xe0000000);
182
183 /*
184 * Configure PCI Local Access Windows
185 */
186 out_be32(&pci_law[0].bar, CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR);
187 out_be32(&pci_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
188
189 out_be32(&pci_law[1].bar, CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR);
190 out_be32(&pci_law[1].ar, LBLAWAR_EN | LBLAWAR_1MB);
191
Peter Tyser6aa3d3b2010-09-14 19:13:50 -0500192 mpc83xx_pci_init(1, reg);
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200193}
194#endif
195
196#if defined(CONFIG_OF_BOARD_SETUP)
Simon Glasse895a4b2014-10-23 18:58:47 -0600197int ft_board_setup(void *blob, bd_t *bd)
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200198{
199 ft_cpu_setup(blob, bd);
200#ifdef CONFIG_PCI
201 ft_pci_setup(blob, bd);
202#endif
Simon Glasse895a4b2014-10-23 18:58:47 -0600203
204 return 0;
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200205}
206#endif