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Michal Simek44303df2015-10-30 15:39:18 +01001/*
2 * dts file for Xilinx ZynqMP
3 *
4 * (C) Copyright 2014 - 2015, Xilinx, Inc.
5 *
6 * Michal Simek <michal.simek@xilinx.com>
7 *
8 * SPDX-License-Identifier: GPL-2.0+
9 */
Michal Simek91d11532016-12-16 13:12:48 +010010
Michal Simek44303df2015-10-30 15:39:18 +010011/ {
12 compatible = "xlnx,zynqmp";
13 #address-cells = <2>;
Michal Simek85d11422016-04-07 15:07:38 +020014 #size-cells = <2>;
Michal Simek44303df2015-10-30 15:39:18 +010015
16 cpus {
17 #address-cells = <1>;
18 #size-cells = <0>;
19
Michal Simek585ca872017-02-06 10:09:53 +010020 cpu0: cpu@0 {
Michal Simek44303df2015-10-30 15:39:18 +010021 compatible = "arm,cortex-a53", "arm,armv8";
22 device_type = "cpu";
23 enable-method = "psci";
Shubhrajyoti Datta941f61f2017-02-13 15:58:55 +053024 operating-points-v2 = <&cpu_opp_table>;
Michal Simek44303df2015-10-30 15:39:18 +010025 reg = <0x0>;
Stefan Krsmanovic2e15b072016-10-21 12:44:56 +020026 cpu-idle-states = <&CPU_SLEEP_0>;
Michal Simek44303df2015-10-30 15:39:18 +010027 };
28
Michal Simek585ca872017-02-06 10:09:53 +010029 cpu1: cpu@1 {
Michal Simek44303df2015-10-30 15:39:18 +010030 compatible = "arm,cortex-a53", "arm,armv8";
31 device_type = "cpu";
32 enable-method = "psci";
33 reg = <0x1>;
Shubhrajyoti Datta941f61f2017-02-13 15:58:55 +053034 operating-points-v2 = <&cpu_opp_table>;
Stefan Krsmanovic2e15b072016-10-21 12:44:56 +020035 cpu-idle-states = <&CPU_SLEEP_0>;
Michal Simek44303df2015-10-30 15:39:18 +010036 };
37
Michal Simek585ca872017-02-06 10:09:53 +010038 cpu2: cpu@2 {
Michal Simek44303df2015-10-30 15:39:18 +010039 compatible = "arm,cortex-a53", "arm,armv8";
40 device_type = "cpu";
41 enable-method = "psci";
42 reg = <0x2>;
Shubhrajyoti Datta941f61f2017-02-13 15:58:55 +053043 operating-points-v2 = <&cpu_opp_table>;
Stefan Krsmanovic2e15b072016-10-21 12:44:56 +020044 cpu-idle-states = <&CPU_SLEEP_0>;
Michal Simek44303df2015-10-30 15:39:18 +010045 };
46
Michal Simek585ca872017-02-06 10:09:53 +010047 cpu3: cpu@3 {
Michal Simek44303df2015-10-30 15:39:18 +010048 compatible = "arm,cortex-a53", "arm,armv8";
49 device_type = "cpu";
50 enable-method = "psci";
51 reg = <0x3>;
Shubhrajyoti Datta941f61f2017-02-13 15:58:55 +053052 operating-points-v2 = <&cpu_opp_table>;
Stefan Krsmanovic2e15b072016-10-21 12:44:56 +020053 cpu-idle-states = <&CPU_SLEEP_0>;
54 };
55
56 idle-states {
Jyotheeswar Reddyfec54732017-01-13 16:13:39 +053057 entry-method = "arm,psci";
Stefan Krsmanovic2e15b072016-10-21 12:44:56 +020058
59 CPU_SLEEP_0: cpu-sleep-0 {
60 compatible = "arm,idle-state";
61 arm,psci-suspend-param = <0x40000000>;
62 local-timer-stop;
63 entry-latency-us = <300>;
64 exit-latency-us = <600>;
Jolly Shah6a097b02017-06-14 15:03:52 -070065 min-residency-us = <10000>;
Stefan Krsmanovic2e15b072016-10-21 12:44:56 +020066 };
Michal Simek44303df2015-10-30 15:39:18 +010067 };
68 };
69
Shubhrajyoti Datta941f61f2017-02-13 15:58:55 +053070 cpu_opp_table: cpu_opp_table {
71 compatible = "operating-points-v2";
72 opp-shared;
73 opp00 {
74 opp-hz = /bits/ 64 <1199999988>;
75 opp-microvolt = <1000000>;
76 clock-latency-ns = <500000>;
77 };
78 opp01 {
79 opp-hz = /bits/ 64 <599999994>;
80 opp-microvolt = <1000000>;
81 clock-latency-ns = <500000>;
82 };
83 opp02 {
84 opp-hz = /bits/ 64 <399999996>;
85 opp-microvolt = <1000000>;
86 clock-latency-ns = <500000>;
87 };
88 opp03 {
89 opp-hz = /bits/ 64 <299999997>;
90 opp-microvolt = <1000000>;
91 clock-latency-ns = <500000>;
92 };
93 };
94
Michal Simek69d09dd2016-09-09 08:46:39 +020095 dcc: dcc {
96 compatible = "arm,dcc";
97 status = "disabled";
98 u-boot,dm-pre-reloc;
99 };
100
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800101 power-domains {
102 compatible = "xlnx,zynqmp-genpd";
103
104 pd_usb0: pd-usb0 {
105 #power-domain-cells = <0x0>;
106 pd-id = <0x16>;
107 };
108
109 pd_usb1: pd-usb1 {
110 #power-domain-cells = <0x0>;
111 pd-id = <0x17>;
112 };
113
114 pd_sata: pd-sata {
115 #power-domain-cells = <0x0>;
116 pd-id = <0x1c>;
117 };
118
119 pd_spi0: pd-spi0 {
120 #power-domain-cells = <0x0>;
121 pd-id = <0x23>;
122 };
123
124 pd_spi1: pd-spi1 {
125 #power-domain-cells = <0x0>;
126 pd-id = <0x24>;
127 };
128
129 pd_uart0: pd-uart0 {
130 #power-domain-cells = <0x0>;
131 pd-id = <0x21>;
132 };
133
134 pd_uart1: pd-uart1 {
135 #power-domain-cells = <0x0>;
136 pd-id = <0x22>;
137 };
138
139 pd_eth0: pd-eth0 {
140 #power-domain-cells = <0x0>;
141 pd-id = <0x1d>;
142 };
143
144 pd_eth1: pd-eth1 {
145 #power-domain-cells = <0x0>;
146 pd-id = <0x1e>;
147 };
148
149 pd_eth2: pd-eth2 {
150 #power-domain-cells = <0x0>;
151 pd-id = <0x1f>;
152 };
153
154 pd_eth3: pd-eth3 {
155 #power-domain-cells = <0x0>;
156 pd-id = <0x20>;
157 };
158
159 pd_i2c0: pd-i2c0 {
160 #power-domain-cells = <0x0>;
161 pd-id = <0x25>;
162 };
163
164 pd_i2c1: pd-i2c1 {
165 #power-domain-cells = <0x0>;
166 pd-id = <0x26>;
167 };
168
169 pd_dp: pd-dp {
170 /* fixme: what to attach to */
171 #power-domain-cells = <0x0>;
172 pd-id = <0x29>;
173 };
174
175 pd_gdma: pd-gdma {
176 #power-domain-cells = <0x0>;
177 pd-id = <0x2a>;
178 };
179
180 pd_adma: pd-adma {
181 #power-domain-cells = <0x0>;
182 pd-id = <0x2b>;
183 };
184
185 pd_ttc0: pd-ttc0 {
186 #power-domain-cells = <0x0>;
187 pd-id = <0x18>;
188 };
189
190 pd_ttc1: pd-ttc1 {
191 #power-domain-cells = <0x0>;
192 pd-id = <0x19>;
193 };
194
195 pd_ttc2: pd-ttc2 {
196 #power-domain-cells = <0x0>;
197 pd-id = <0x1a>;
198 };
199
200 pd_ttc3: pd-ttc3 {
201 #power-domain-cells = <0x0>;
202 pd-id = <0x1b>;
203 };
204
205 pd_sd0: pd-sd0 {
206 #power-domain-cells = <0x0>;
207 pd-id = <0x27>;
208 };
209
210 pd_sd1: pd-sd1 {
211 #power-domain-cells = <0x0>;
212 pd-id = <0x28>;
213 };
214
215 pd_nand: pd-nand {
216 #power-domain-cells = <0x0>;
217 pd-id = <0x2c>;
218 };
219
220 pd_qspi: pd-qspi {
221 #power-domain-cells = <0x0>;
222 pd-id = <0x2d>;
223 };
224
225 pd_gpio: pd-gpio {
226 #power-domain-cells = <0x0>;
227 pd-id = <0x2e>;
228 };
229
230 pd_can0: pd-can0 {
231 #power-domain-cells = <0x0>;
232 pd-id = <0x2f>;
233 };
234
235 pd_can1: pd-can1 {
236 #power-domain-cells = <0x0>;
237 pd-id = <0x30>;
238 };
Filip Drazic2af39322016-08-29 19:32:56 +0200239
240 pd_pcie: pd-pcie {
241 #power-domain-cells = <0x0>;
242 pd-id = <0x3b>;
243 };
244
245 pd_gpu: pd-gpu {
246 #power-domain-cells = <0x0>;
Filip Drazica4d7d562016-08-29 19:32:59 +0200247 pd-id = <0x3a 0x14 0x15>;
Filip Drazic2af39322016-08-29 19:32:56 +0200248 };
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800249 };
250
Michal Simek44303df2015-10-30 15:39:18 +0100251 pmu {
252 compatible = "arm,armv8-pmuv3";
Michal Simek14cd9ea2016-04-07 15:28:33 +0200253 interrupt-parent = <&gic>;
Michal Simek44303df2015-10-30 15:39:18 +0100254 interrupts = <0 143 4>,
255 <0 144 4>,
256 <0 145 4>,
257 <0 146 4>;
258 };
259
260 psci {
261 compatible = "arm,psci-0.2";
262 method = "smc";
263 };
264
265 firmware {
266 compatible = "xlnx,zynqmp-pm";
267 method = "smc";
Soren Brinkmann19ee4022016-11-21 16:12:05 -0800268 interrupt-parent = <&gic>;
269 interrupts = <0 35 4>;
Michal Simek44303df2015-10-30 15:39:18 +0100270 };
271
272 timer {
273 compatible = "arm,armv8-timer";
274 interrupt-parent = <&gic>;
Michal Simek6db82e02017-02-09 14:45:12 +0100275 interrupts = <1 13 0xf08>,
276 <1 14 0xf08>,
277 <1 11 0xf08>,
278 <1 10 0xf08>;
Michal Simek44303df2015-10-30 15:39:18 +0100279 };
280
Naga Sureshkumar Relliaaf232f2016-06-20 15:48:30 +0530281 edac {
282 compatible = "arm,cortex-a53-edac";
283 };
284
Nava kishore Manne7689dce2017-05-22 12:05:17 +0530285 fpga_full: fpga-full {
286 compatible = "fpga-region";
287 fpga-mgr = <&pcap>;
288 #address-cells = <2>;
289 #size-cells = <2>;
290 };
291
292 pcap: pcap {
Nava kishore Manned64e43f2016-08-21 00:17:52 +0530293 compatible = "xlnx,zynqmp-pcap-fpga";
294 };
295
Michal Simekc926e6f2016-11-11 13:21:04 +0100296 amba_apu: amba_apu@0 {
Michal Simek44303df2015-10-30 15:39:18 +0100297 compatible = "simple-bus";
298 #address-cells = <2>;
299 #size-cells = <1>;
Michal Simek85d11422016-04-07 15:07:38 +0200300 ranges = <0 0 0 0 0xffffffff>;
Michal Simek44303df2015-10-30 15:39:18 +0100301
302 gic: interrupt-controller@f9010000 {
303 compatible = "arm,gic-400", "arm,cortex-a15-gic";
304 #interrupt-cells = <3>;
305 reg = <0x0 0xf9010000 0x10000>,
Alexander Graf0a8c4f62016-05-12 13:44:01 +0200306 <0x0 0xf9020000 0x20000>,
Michal Simek44303df2015-10-30 15:39:18 +0100307 <0x0 0xf9040000 0x20000>,
Alexander Graf0a8c4f62016-05-12 13:44:01 +0200308 <0x0 0xf9060000 0x20000>;
Michal Simek44303df2015-10-30 15:39:18 +0100309 interrupt-controller;
310 interrupt-parent = <&gic>;
311 interrupts = <1 9 0xf04>;
312 };
313 };
314
Michal Simekb976fd62016-02-11 07:19:06 +0100315 amba: amba {
Michal Simek44303df2015-10-30 15:39:18 +0100316 compatible = "simple-bus";
Michal Simekc9811e12016-02-22 09:57:27 +0100317 u-boot,dm-pre-reloc;
Michal Simek44303df2015-10-30 15:39:18 +0100318 #address-cells = <2>;
Michal Simekb976fd62016-02-11 07:19:06 +0100319 #size-cells = <2>;
320 ranges;
Michal Simek44303df2015-10-30 15:39:18 +0100321
322 can0: can@ff060000 {
323 compatible = "xlnx,zynq-can-1.0";
324 status = "disabled";
325 clock-names = "can_clk", "pclk";
Michal Simekb976fd62016-02-11 07:19:06 +0100326 reg = <0x0 0xff060000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +0100327 interrupts = <0 23 4>;
328 interrupt-parent = <&gic>;
329 tx-fifo-depth = <0x40>;
330 rx-fifo-depth = <0x40>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800331 power-domains = <&pd_can0>;
Michal Simek44303df2015-10-30 15:39:18 +0100332 };
333
334 can1: can@ff070000 {
335 compatible = "xlnx,zynq-can-1.0";
336 status = "disabled";
337 clock-names = "can_clk", "pclk";
Michal Simekb976fd62016-02-11 07:19:06 +0100338 reg = <0x0 0xff070000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +0100339 interrupts = <0 24 4>;
340 interrupt-parent = <&gic>;
341 tx-fifo-depth = <0x40>;
342 rx-fifo-depth = <0x40>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800343 power-domains = <&pd_can1>;
Michal Simek44303df2015-10-30 15:39:18 +0100344 };
345
Michal Simekff50d212015-11-26 11:21:25 +0100346 cci: cci@fd6e0000 {
347 compatible = "arm,cci-400";
Michal Simekb976fd62016-02-11 07:19:06 +0100348 reg = <0x0 0xfd6e0000 0x0 0x9000>;
Michal Simekff50d212015-11-26 11:21:25 +0100349 ranges = <0x0 0x0 0xfd6e0000 0x10000>;
350 #address-cells = <1>;
351 #size-cells = <1>;
352
353 pmu@9000 {
354 compatible = "arm,cci-400-pmu,r1";
355 reg = <0x9000 0x5000>;
356 interrupt-parent = <&gic>;
357 interrupts = <0 123 4>,
358 <0 123 4>,
359 <0 123 4>,
360 <0 123 4>,
361 <0 123 4>;
362 };
363 };
364
Michal Simek44303df2015-10-30 15:39:18 +0100365 /* GDMA */
366 fpd_dma_chan1: dma@fd500000 {
367 status = "disabled";
368 compatible = "xlnx,zynqmp-dma-1.0";
Michal Simekb976fd62016-02-11 07:19:06 +0100369 reg = <0x0 0xfd500000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +0100370 interrupt-parent = <&gic>;
371 interrupts = <0 124 4>;
VNSL Durgab34d11d2016-03-24 22:45:12 +0530372 clock-names = "clk_main", "clk_apb";
Michal Simek44303df2015-10-30 15:39:18 +0100373 xlnx,bus-width = <128>;
Michal Simekba6ad312016-04-06 10:43:23 +0200374 #stream-id-cells = <1>;
375 iommus = <&smmu 0x14e8>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800376 power-domains = <&pd_gdma>;
Michal Simek44303df2015-10-30 15:39:18 +0100377 };
378
379 fpd_dma_chan2: dma@fd510000 {
380 status = "disabled";
381 compatible = "xlnx,zynqmp-dma-1.0";
Michal Simekb976fd62016-02-11 07:19:06 +0100382 reg = <0x0 0xfd510000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +0100383 interrupt-parent = <&gic>;
384 interrupts = <0 125 4>;
VNSL Durgab34d11d2016-03-24 22:45:12 +0530385 clock-names = "clk_main", "clk_apb";
Michal Simek44303df2015-10-30 15:39:18 +0100386 xlnx,bus-width = <128>;
Michal Simekba6ad312016-04-06 10:43:23 +0200387 #stream-id-cells = <1>;
388 iommus = <&smmu 0x14e9>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800389 power-domains = <&pd_gdma>;
Michal Simek44303df2015-10-30 15:39:18 +0100390 };
391
392 fpd_dma_chan3: dma@fd520000 {
393 status = "disabled";
394 compatible = "xlnx,zynqmp-dma-1.0";
Michal Simekb976fd62016-02-11 07:19:06 +0100395 reg = <0x0 0xfd520000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +0100396 interrupt-parent = <&gic>;
397 interrupts = <0 126 4>;
VNSL Durgab34d11d2016-03-24 22:45:12 +0530398 clock-names = "clk_main", "clk_apb";
Michal Simek44303df2015-10-30 15:39:18 +0100399 xlnx,bus-width = <128>;
Michal Simekba6ad312016-04-06 10:43:23 +0200400 #stream-id-cells = <1>;
401 iommus = <&smmu 0x14ea>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800402 power-domains = <&pd_gdma>;
Michal Simek44303df2015-10-30 15:39:18 +0100403 };
404
405 fpd_dma_chan4: dma@fd530000 {
406 status = "disabled";
407 compatible = "xlnx,zynqmp-dma-1.0";
Michal Simekb976fd62016-02-11 07:19:06 +0100408 reg = <0x0 0xfd530000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +0100409 interrupt-parent = <&gic>;
410 interrupts = <0 127 4>;
VNSL Durgab34d11d2016-03-24 22:45:12 +0530411 clock-names = "clk_main", "clk_apb";
Michal Simek44303df2015-10-30 15:39:18 +0100412 xlnx,bus-width = <128>;
Michal Simekba6ad312016-04-06 10:43:23 +0200413 #stream-id-cells = <1>;
414 iommus = <&smmu 0x14eb>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800415 power-domains = <&pd_gdma>;
Michal Simek44303df2015-10-30 15:39:18 +0100416 };
417
418 fpd_dma_chan5: dma@fd540000 {
419 status = "disabled";
420 compatible = "xlnx,zynqmp-dma-1.0";
Michal Simekb976fd62016-02-11 07:19:06 +0100421 reg = <0x0 0xfd540000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +0100422 interrupt-parent = <&gic>;
423 interrupts = <0 128 4>;
VNSL Durgab34d11d2016-03-24 22:45:12 +0530424 clock-names = "clk_main", "clk_apb";
Michal Simek44303df2015-10-30 15:39:18 +0100425 xlnx,bus-width = <128>;
Michal Simekba6ad312016-04-06 10:43:23 +0200426 #stream-id-cells = <1>;
427 iommus = <&smmu 0x14ec>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800428 power-domains = <&pd_gdma>;
Michal Simek44303df2015-10-30 15:39:18 +0100429 };
430
431 fpd_dma_chan6: dma@fd550000 {
432 status = "disabled";
433 compatible = "xlnx,zynqmp-dma-1.0";
Michal Simekb976fd62016-02-11 07:19:06 +0100434 reg = <0x0 0xfd550000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +0100435 interrupt-parent = <&gic>;
436 interrupts = <0 129 4>;
VNSL Durgab34d11d2016-03-24 22:45:12 +0530437 clock-names = "clk_main", "clk_apb";
Michal Simek44303df2015-10-30 15:39:18 +0100438 xlnx,bus-width = <128>;
Michal Simekba6ad312016-04-06 10:43:23 +0200439 #stream-id-cells = <1>;
440 iommus = <&smmu 0x14ed>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800441 power-domains = <&pd_gdma>;
Michal Simek44303df2015-10-30 15:39:18 +0100442 };
443
444 fpd_dma_chan7: dma@fd560000 {
445 status = "disabled";
446 compatible = "xlnx,zynqmp-dma-1.0";
Michal Simekb976fd62016-02-11 07:19:06 +0100447 reg = <0x0 0xfd560000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +0100448 interrupt-parent = <&gic>;
449 interrupts = <0 130 4>;
VNSL Durgab34d11d2016-03-24 22:45:12 +0530450 clock-names = "clk_main", "clk_apb";
Michal Simek44303df2015-10-30 15:39:18 +0100451 xlnx,bus-width = <128>;
Michal Simekba6ad312016-04-06 10:43:23 +0200452 #stream-id-cells = <1>;
453 iommus = <&smmu 0x14ee>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800454 power-domains = <&pd_gdma>;
Michal Simek44303df2015-10-30 15:39:18 +0100455 };
456
457 fpd_dma_chan8: dma@fd570000 {
458 status = "disabled";
459 compatible = "xlnx,zynqmp-dma-1.0";
Michal Simekb976fd62016-02-11 07:19:06 +0100460 reg = <0x0 0xfd570000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +0100461 interrupt-parent = <&gic>;
462 interrupts = <0 131 4>;
VNSL Durgab34d11d2016-03-24 22:45:12 +0530463 clock-names = "clk_main", "clk_apb";
Michal Simek44303df2015-10-30 15:39:18 +0100464 xlnx,bus-width = <128>;
Michal Simekba6ad312016-04-06 10:43:23 +0200465 #stream-id-cells = <1>;
466 iommus = <&smmu 0x14ef>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800467 power-domains = <&pd_gdma>;
Michal Simek44303df2015-10-30 15:39:18 +0100468 };
469
470 gpu: gpu@fd4b0000 {
471 status = "disabled";
472 compatible = "arm,mali-400", "arm,mali-utgard";
Hyun Kwon834ec8e2017-08-21 18:54:29 -0700473 reg = <0x0 0xfd4b0000 0x0 0x10000>;
Michal Simek44303df2015-10-30 15:39:18 +0100474 interrupt-parent = <&gic>;
475 interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>;
476 interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1";
Madhurkiran Harikrishnan59206dd2017-02-17 04:14:45 -0800477 clock-names = "gpu", "gpu_pp0", "gpu_pp1";
Filip Drazic2af39322016-08-29 19:32:56 +0200478 power-domains = <&pd_gpu>;
Michal Simek44303df2015-10-30 15:39:18 +0100479 };
480
Kedareswara rao Appana6af57732016-09-09 12:36:01 +0530481 /* LPDDMA default allows only secured access. inorder to enable
482 * These dma channels, Users should ensure that these dma
483 * Channels are allowed for non secure access.
484 */
Michal Simek44303df2015-10-30 15:39:18 +0100485 lpd_dma_chan1: dma@ffa80000 {
486 status = "disabled";
487 compatible = "xlnx,zynqmp-dma-1.0";
Kedareswara rao Appanad33046a2016-09-30 10:34:59 +0530488 clock-names = "clk_main", "clk_apb";
Michal Simekb976fd62016-02-11 07:19:06 +0100489 reg = <0x0 0xffa80000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +0100490 interrupt-parent = <&gic>;
491 interrupts = <0 77 4>;
Michal Simek44303df2015-10-30 15:39:18 +0100492 xlnx,bus-width = <64>;
Michal Simekba6ad312016-04-06 10:43:23 +0200493 #stream-id-cells = <1>;
494 iommus = <&smmu 0x868>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800495 power-domains = <&pd_adma>;
Michal Simek44303df2015-10-30 15:39:18 +0100496 };
497
498 lpd_dma_chan2: dma@ffa90000 {
499 status = "disabled";
500 compatible = "xlnx,zynqmp-dma-1.0";
Kedareswara rao Appanad33046a2016-09-30 10:34:59 +0530501 clock-names = "clk_main", "clk_apb";
Michal Simekb976fd62016-02-11 07:19:06 +0100502 reg = <0x0 0xffa90000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +0100503 interrupt-parent = <&gic>;
504 interrupts = <0 78 4>;
Michal Simek44303df2015-10-30 15:39:18 +0100505 xlnx,bus-width = <64>;
Michal Simekba6ad312016-04-06 10:43:23 +0200506 #stream-id-cells = <1>;
507 iommus = <&smmu 0x869>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800508 power-domains = <&pd_adma>;
Michal Simek44303df2015-10-30 15:39:18 +0100509 };
510
511 lpd_dma_chan3: dma@ffaa0000 {
512 status = "disabled";
513 compatible = "xlnx,zynqmp-dma-1.0";
Kedareswara rao Appanad33046a2016-09-30 10:34:59 +0530514 clock-names = "clk_main", "clk_apb";
Michal Simekb976fd62016-02-11 07:19:06 +0100515 reg = <0x0 0xffaa0000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +0100516 interrupt-parent = <&gic>;
517 interrupts = <0 79 4>;
Michal Simek44303df2015-10-30 15:39:18 +0100518 xlnx,bus-width = <64>;
Michal Simekba6ad312016-04-06 10:43:23 +0200519 #stream-id-cells = <1>;
520 iommus = <&smmu 0x86a>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800521 power-domains = <&pd_adma>;
Michal Simek44303df2015-10-30 15:39:18 +0100522 };
523
524 lpd_dma_chan4: dma@ffab0000 {
525 status = "disabled";
526 compatible = "xlnx,zynqmp-dma-1.0";
Kedareswara rao Appanad33046a2016-09-30 10:34:59 +0530527 clock-names = "clk_main", "clk_apb";
Michal Simekb976fd62016-02-11 07:19:06 +0100528 reg = <0x0 0xffab0000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +0100529 interrupt-parent = <&gic>;
530 interrupts = <0 80 4>;
Michal Simek44303df2015-10-30 15:39:18 +0100531 xlnx,bus-width = <64>;
Michal Simekba6ad312016-04-06 10:43:23 +0200532 #stream-id-cells = <1>;
533 iommus = <&smmu 0x86b>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800534 power-domains = <&pd_adma>;
Michal Simek44303df2015-10-30 15:39:18 +0100535 };
536
537 lpd_dma_chan5: dma@ffac0000 {
538 status = "disabled";
539 compatible = "xlnx,zynqmp-dma-1.0";
Kedareswara rao Appanad33046a2016-09-30 10:34:59 +0530540 clock-names = "clk_main", "clk_apb";
Michal Simekb976fd62016-02-11 07:19:06 +0100541 reg = <0x0 0xffac0000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +0100542 interrupt-parent = <&gic>;
543 interrupts = <0 81 4>;
Michal Simek44303df2015-10-30 15:39:18 +0100544 xlnx,bus-width = <64>;
Michal Simekba6ad312016-04-06 10:43:23 +0200545 #stream-id-cells = <1>;
546 iommus = <&smmu 0x86c>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800547 power-domains = <&pd_adma>;
Michal Simek44303df2015-10-30 15:39:18 +0100548 };
549
550 lpd_dma_chan6: dma@ffad0000 {
551 status = "disabled";
552 compatible = "xlnx,zynqmp-dma-1.0";
Kedareswara rao Appanad33046a2016-09-30 10:34:59 +0530553 clock-names = "clk_main", "clk_apb";
Michal Simekb976fd62016-02-11 07:19:06 +0100554 reg = <0x0 0xffad0000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +0100555 interrupt-parent = <&gic>;
556 interrupts = <0 82 4>;
Michal Simek44303df2015-10-30 15:39:18 +0100557 xlnx,bus-width = <64>;
Michal Simekba6ad312016-04-06 10:43:23 +0200558 #stream-id-cells = <1>;
559 iommus = <&smmu 0x86d>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800560 power-domains = <&pd_adma>;
Michal Simek44303df2015-10-30 15:39:18 +0100561 };
562
563 lpd_dma_chan7: dma@ffae0000 {
564 status = "disabled";
565 compatible = "xlnx,zynqmp-dma-1.0";
Kedareswara rao Appanad33046a2016-09-30 10:34:59 +0530566 clock-names = "clk_main", "clk_apb";
Michal Simekb976fd62016-02-11 07:19:06 +0100567 reg = <0x0 0xffae0000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +0100568 interrupt-parent = <&gic>;
569 interrupts = <0 83 4>;
Michal Simek44303df2015-10-30 15:39:18 +0100570 xlnx,bus-width = <64>;
Michal Simekba6ad312016-04-06 10:43:23 +0200571 #stream-id-cells = <1>;
572 iommus = <&smmu 0x86e>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800573 power-domains = <&pd_adma>;
Michal Simek44303df2015-10-30 15:39:18 +0100574 };
575
576 lpd_dma_chan8: dma@ffaf0000 {
577 status = "disabled";
578 compatible = "xlnx,zynqmp-dma-1.0";
Kedareswara rao Appanad33046a2016-09-30 10:34:59 +0530579 clock-names = "clk_main", "clk_apb";
Michal Simekb976fd62016-02-11 07:19:06 +0100580 reg = <0x0 0xffaf0000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +0100581 interrupt-parent = <&gic>;
582 interrupts = <0 84 4>;
Michal Simek44303df2015-10-30 15:39:18 +0100583 xlnx,bus-width = <64>;
Michal Simekba6ad312016-04-06 10:43:23 +0200584 #stream-id-cells = <1>;
585 iommus = <&smmu 0x86f>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800586 power-domains = <&pd_adma>;
Michal Simek44303df2015-10-30 15:39:18 +0100587 };
588
Naga Sureshkumar Relli90869002016-03-11 13:10:26 +0530589 mc: memory-controller@fd070000 {
590 compatible = "xlnx,zynqmp-ddrc-2.40a";
Michal Simekb976fd62016-02-11 07:19:06 +0100591 reg = <0x0 0xfd070000 0x0 0x30000>;
Naga Sureshkumar Relli90869002016-03-11 13:10:26 +0530592 interrupt-parent = <&gic>;
593 interrupts = <0 112 4>;
594 };
595
Michal Simek44303df2015-10-30 15:39:18 +0100596 nand0: nand@ff100000 {
597 compatible = "arasan,nfc-v3p10";
598 status = "disabled";
Michal Simekb976fd62016-02-11 07:19:06 +0100599 reg = <0x0 0xff100000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +0100600 clock-names = "clk_sys", "clk_flash";
601 interrupt-parent = <&gic>;
602 interrupts = <0 14 4>;
603 #address-cells = <2>;
604 #size-cells = <1>;
Michal Simekba6ad312016-04-06 10:43:23 +0200605 #stream-id-cells = <1>;
606 iommus = <&smmu 0x872>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800607 power-domains = <&pd_nand>;
Michal Simek44303df2015-10-30 15:39:18 +0100608 };
609
610 gem0: ethernet@ff0b0000 {
Michal Simekda2ad782016-02-11 15:26:46 +0100611 compatible = "cdns,zynqmp-gem";
Michal Simek44303df2015-10-30 15:39:18 +0100612 status = "disabled";
613 interrupt-parent = <&gic>;
614 interrupts = <0 57 4>, <0 57 4>;
Michal Simekb976fd62016-02-11 07:19:06 +0100615 reg = <0x0 0xff0b0000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +0100616 clock-names = "pclk", "hclk", "tx_clk";
617 #address-cells = <1>;
618 #size-cells = <0>;
Edgar E. Iglesias7f1d7d92015-11-26 14:12:20 +0100619 #stream-id-cells = <1>;
Michal Simekba6ad312016-04-06 10:43:23 +0200620 iommus = <&smmu 0x874>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800621 power-domains = <&pd_eth0>;
Michal Simek44303df2015-10-30 15:39:18 +0100622 };
623
624 gem1: ethernet@ff0c0000 {
Michal Simekda2ad782016-02-11 15:26:46 +0100625 compatible = "cdns,zynqmp-gem";
Michal Simek44303df2015-10-30 15:39:18 +0100626 status = "disabled";
627 interrupt-parent = <&gic>;
628 interrupts = <0 59 4>, <0 59 4>;
Michal Simekb976fd62016-02-11 07:19:06 +0100629 reg = <0x0 0xff0c0000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +0100630 clock-names = "pclk", "hclk", "tx_clk";
631 #address-cells = <1>;
632 #size-cells = <0>;
Edgar E. Iglesias7f1d7d92015-11-26 14:12:20 +0100633 #stream-id-cells = <1>;
Michal Simekba6ad312016-04-06 10:43:23 +0200634 iommus = <&smmu 0x875>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800635 power-domains = <&pd_eth1>;
Michal Simek44303df2015-10-30 15:39:18 +0100636 };
637
638 gem2: ethernet@ff0d0000 {
Michal Simekda2ad782016-02-11 15:26:46 +0100639 compatible = "cdns,zynqmp-gem";
Michal Simek44303df2015-10-30 15:39:18 +0100640 status = "disabled";
641 interrupt-parent = <&gic>;
642 interrupts = <0 61 4>, <0 61 4>;
Michal Simekb976fd62016-02-11 07:19:06 +0100643 reg = <0x0 0xff0d0000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +0100644 clock-names = "pclk", "hclk", "tx_clk";
645 #address-cells = <1>;
646 #size-cells = <0>;
Edgar E. Iglesias7f1d7d92015-11-26 14:12:20 +0100647 #stream-id-cells = <1>;
Michal Simekba6ad312016-04-06 10:43:23 +0200648 iommus = <&smmu 0x876>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800649 power-domains = <&pd_eth2>;
Michal Simek44303df2015-10-30 15:39:18 +0100650 };
651
652 gem3: ethernet@ff0e0000 {
Michal Simekda2ad782016-02-11 15:26:46 +0100653 compatible = "cdns,zynqmp-gem";
Michal Simek44303df2015-10-30 15:39:18 +0100654 status = "disabled";
655 interrupt-parent = <&gic>;
656 interrupts = <0 63 4>, <0 63 4>;
Michal Simekb976fd62016-02-11 07:19:06 +0100657 reg = <0x0 0xff0e0000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +0100658 clock-names = "pclk", "hclk", "tx_clk";
659 #address-cells = <1>;
660 #size-cells = <0>;
Edgar E. Iglesias7f1d7d92015-11-26 14:12:20 +0100661 #stream-id-cells = <1>;
Michal Simekba6ad312016-04-06 10:43:23 +0200662 iommus = <&smmu 0x877>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800663 power-domains = <&pd_eth3>;
Michal Simek44303df2015-10-30 15:39:18 +0100664 };
665
666 gpio: gpio@ff0a0000 {
667 compatible = "xlnx,zynqmp-gpio-1.0";
668 status = "disabled";
669 #gpio-cells = <0x2>;
670 interrupt-parent = <&gic>;
671 interrupts = <0 16 4>;
Michal Simek9e826b62016-10-20 10:26:13 +0200672 interrupt-controller;
673 #interrupt-cells = <2>;
Michal Simekb976fd62016-02-11 07:19:06 +0100674 reg = <0x0 0xff0a0000 0x0 0x1000>;
Michal Simek0b33e0b12017-08-30 08:06:11 +0200675 gpio-controller;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800676 power-domains = <&pd_gpio>;
Michal Simek44303df2015-10-30 15:39:18 +0100677 };
678
679 i2c0: i2c@ff020000 {
Moritz Fischerde4914b2016-12-22 09:36:11 -0800680 compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
Michal Simek44303df2015-10-30 15:39:18 +0100681 status = "disabled";
682 interrupt-parent = <&gic>;
683 interrupts = <0 17 4>;
Michal Simekb976fd62016-02-11 07:19:06 +0100684 reg = <0x0 0xff020000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +0100685 #address-cells = <1>;
686 #size-cells = <0>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800687 power-domains = <&pd_i2c0>;
Michal Simek44303df2015-10-30 15:39:18 +0100688 };
689
690 i2c1: i2c@ff030000 {
Moritz Fischerde4914b2016-12-22 09:36:11 -0800691 compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
Michal Simek44303df2015-10-30 15:39:18 +0100692 status = "disabled";
693 interrupt-parent = <&gic>;
694 interrupts = <0 18 4>;
Michal Simekb976fd62016-02-11 07:19:06 +0100695 reg = <0x0 0xff030000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +0100696 #address-cells = <1>;
697 #size-cells = <0>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800698 power-domains = <&pd_i2c1>;
Michal Simek44303df2015-10-30 15:39:18 +0100699 };
700
Naga Sureshkumar Relli55344802016-05-18 12:23:13 +0530701 ocm: memory-controller@ff960000 {
702 compatible = "xlnx,zynqmp-ocmc-1.0";
Michal Simekb976fd62016-02-11 07:19:06 +0100703 reg = <0x0 0xff960000 0x0 0x1000>;
Naga Sureshkumar Relli55344802016-05-18 12:23:13 +0530704 interrupt-parent = <&gic>;
705 interrupts = <0 10 4>;
706 };
707
Michal Simek44303df2015-10-30 15:39:18 +0100708 pcie: pcie@fd0e0000 {
709 compatible = "xlnx,nwl-pcie-2.11";
710 status = "disabled";
711 #address-cells = <3>;
712 #size-cells = <2>;
713 #interrupt-cells = <1>;
Bharat Kumar Gogada7d6ca732016-07-19 20:49:29 +0530714 msi-controller;
Michal Simek44303df2015-10-30 15:39:18 +0100715 device_type = "pci";
716 interrupt-parent = <&gic>;
Michal Simek91a8b0e2016-01-20 12:59:23 +0100717 interrupts = <0 118 4>,
Bharat Kumar Gogada7d6ca732016-07-19 20:49:29 +0530718 <0 117 4>,
Michal Simek91a8b0e2016-01-20 12:59:23 +0100719 <0 116 4>,
720 <0 115 4>, /* MSI_1 [63...32] */
721 <0 114 4>; /* MSI_0 [31...0] */
Bharat Kumar Gogada7d6ca732016-07-19 20:49:29 +0530722 interrupt-names = "misc","dummy","intx", "msi1", "msi0";
723 msi-parent = <&pcie>;
Michal Simekb976fd62016-02-11 07:19:06 +0100724 reg = <0x0 0xfd0e0000 0x0 0x1000>,
725 <0x0 0xfd480000 0x0 0x1000>,
Bharat Kumar Gogada688d1be2016-08-02 20:34:13 +0530726 <0x80 0x00000000 0x0 0x1000000>;
Michal Simek44303df2015-10-30 15:39:18 +0100727 reg-names = "breg", "pcireg", "cfg";
Bharat Kumar Gogada688d1be2016-08-02 20:34:13 +0530728 ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */
729 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
Rob Herringec2b2d42017-03-21 21:03:13 -0500730 bus-range = <0x00 0xff>;
Bharat Kumar Gogada33aec512016-02-15 21:18:58 +0530731 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
732 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
733 <0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
734 <0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
735 <0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
Filip Drazic2af39322016-08-29 19:32:56 +0200736 power-domains = <&pd_pcie>;
Bharat Kumar Gogada33aec512016-02-15 21:18:58 +0530737 pcie_intc: legacy-interrupt-controller {
738 interrupt-controller;
739 #address-cells = <0>;
740 #interrupt-cells = <1>;
741 };
Michal Simek44303df2015-10-30 15:39:18 +0100742 };
743
744 qspi: spi@ff0f0000 {
745 compatible = "xlnx,zynqmp-qspi-1.0";
746 status = "disabled";
747 clock-names = "ref_clk", "pclk";
748 interrupts = <0 15 4>;
749 interrupt-parent = <&gic>;
750 num-cs = <1>;
Michal Simekb976fd62016-02-11 07:19:06 +0100751 reg = <0x0 0xff0f0000 0x0 0x1000>,
752 <0x0 0xc0000000 0x0 0x8000000>;
Michal Simek44303df2015-10-30 15:39:18 +0100753 #address-cells = <1>;
754 #size-cells = <0>;
Michal Simekba6ad312016-04-06 10:43:23 +0200755 #stream-id-cells = <1>;
756 iommus = <&smmu 0x873>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800757 power-domains = <&pd_qspi>;
Michal Simek44303df2015-10-30 15:39:18 +0100758 };
759
760 rtc: rtc@ffa60000 {
761 compatible = "xlnx,zynqmp-rtc";
762 status = "disabled";
Michal Simekb976fd62016-02-11 07:19:06 +0100763 reg = <0x0 0xffa60000 0x0 0x100>;
Michal Simek44303df2015-10-30 15:39:18 +0100764 interrupt-parent = <&gic>;
765 interrupts = <0 26 4>, <0 27 4>;
766 interrupt-names = "alarm", "sec";
767 };
768
Anurag Kumar Vulishadb6c62e2016-05-17 16:49:01 +0530769 serdes: zynqmp_phy@fd400000 {
770 compatible = "xlnx,zynqmp-psgtr";
771 status = "disabled";
Michal Simekb976fd62016-02-11 07:19:06 +0100772 reg = <0x0 0xfd400000 0x0 0x40000>,
773 <0x0 0xfd3d0000 0x0 0x1000>,
774 <0x0 0xfd1a0000 0x0 0x1000>,
775 <0x0 0xff5e0000 0x0 0x1000>;
Anurag Kumar Vulishadb6c62e2016-05-17 16:49:01 +0530776 reg-names = "serdes", "siou", "fpd", "lpd";
777 xlnx,tx_termination_fix;
778 lane0: lane0 {
779 #phy-cells = <4>;
780 };
781 lane1: lane1 {
782 #phy-cells = <4>;
783 };
784 lane2: lane2 {
785 #phy-cells = <4>;
786 };
787 lane3: lane3 {
788 #phy-cells = <4>;
789 };
790 };
791
Michal Simek44303df2015-10-30 15:39:18 +0100792 sata: ahci@fd0c0000 {
793 compatible = "ceva,ahci-1v84";
794 status = "disabled";
Michal Simekb976fd62016-02-11 07:19:06 +0100795 reg = <0x0 0xfd0c0000 0x0 0x2000>;
Michal Simek44303df2015-10-30 15:39:18 +0100796 interrupt-parent = <&gic>;
797 interrupts = <0 133 4>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800798 power-domains = <&pd_sata>;
Anurag Kumar Vulisha110d06b2017-07-04 20:03:42 +0530799 #stream-id-cells = <4>;
800 iommus = <&smmu 0x4c0>, <&smmu 0x4c1>,
801 <&smmu 0x4c2>, <&smmu 0x4c3>;
802 /* dma-coherent; */
Michal Simek44303df2015-10-30 15:39:18 +0100803 };
804
805 sdhci0: sdhci@ff160000 {
Michal Simekc9811e12016-02-22 09:57:27 +0100806 u-boot,dm-pre-reloc;
Sai Krishna Potthuri0488a5e2016-08-16 14:41:35 +0530807 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
Michal Simek44303df2015-10-30 15:39:18 +0100808 status = "disabled";
809 interrupt-parent = <&gic>;
810 interrupts = <0 48 4>;
Michal Simekb976fd62016-02-11 07:19:06 +0100811 reg = <0x0 0xff160000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +0100812 clock-names = "clk_xin", "clk_ahb";
Sai Krishna Potthuri0488a5e2016-08-16 14:41:35 +0530813 xlnx,device_id = <0>;
Michal Simekba6ad312016-04-06 10:43:23 +0200814 #stream-id-cells = <1>;
815 iommus = <&smmu 0x870>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800816 power-domains = <&pd_sd0>;
Michal Simek44303df2015-10-30 15:39:18 +0100817 };
818
819 sdhci1: sdhci@ff170000 {
Michal Simekc9811e12016-02-22 09:57:27 +0100820 u-boot,dm-pre-reloc;
Sai Krishna Potthuri0488a5e2016-08-16 14:41:35 +0530821 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
Michal Simek44303df2015-10-30 15:39:18 +0100822 status = "disabled";
823 interrupt-parent = <&gic>;
824 interrupts = <0 49 4>;
Michal Simekb976fd62016-02-11 07:19:06 +0100825 reg = <0x0 0xff170000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +0100826 clock-names = "clk_xin", "clk_ahb";
Sai Krishna Potthuri0488a5e2016-08-16 14:41:35 +0530827 xlnx,device_id = <1>;
Michal Simekba6ad312016-04-06 10:43:23 +0200828 #stream-id-cells = <1>;
829 iommus = <&smmu 0x871>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800830 power-domains = <&pd_sd1>;
Michal Simek44303df2015-10-30 15:39:18 +0100831 };
832
833 smmu: smmu@fd800000 {
834 compatible = "arm,mmu-500";
Michal Simekb976fd62016-02-11 07:19:06 +0100835 reg = <0x0 0xfd800000 0x0 0x20000>;
Michal Simekba6ad312016-04-06 10:43:23 +0200836 #iommu-cells = <1>;
Michal Simek44303df2015-10-30 15:39:18 +0100837 #global-interrupts = <1>;
838 interrupt-parent = <&gic>;
Edgar E. Iglesias88a85aa2015-11-26 14:12:19 +0100839 interrupts = <0 155 4>,
840 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
841 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
842 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
843 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;
Edgar E. Iglesias7f1d7d92015-11-26 14:12:20 +0100844 mmu-masters = < &gem0 0x874
845 &gem1 0x875
846 &gem2 0x876
Michal Simekba6ad312016-04-06 10:43:23 +0200847 &gem3 0x877
848 &usb0 0x860
849 &usb1 0x861
850 &qspi 0x873
851 &lpd_dma_chan1 0x868
852 &lpd_dma_chan2 0x869
853 &lpd_dma_chan3 0x86a
854 &lpd_dma_chan4 0x86b
855 &lpd_dma_chan5 0x86c
856 &lpd_dma_chan6 0x86d
857 &lpd_dma_chan7 0x86e
858 &lpd_dma_chan8 0x86f
859 &fpd_dma_chan1 0x14e8
860 &fpd_dma_chan2 0x14e9
861 &fpd_dma_chan3 0x14ea
862 &fpd_dma_chan4 0x14eb
863 &fpd_dma_chan5 0x14ec
864 &fpd_dma_chan6 0x14ed
865 &fpd_dma_chan7 0x14ee
866 &fpd_dma_chan8 0x14ef
867 &sdhci0 0x870
868 &sdhci1 0x871
869 &nand0 0x872>;
Michal Simek44303df2015-10-30 15:39:18 +0100870 };
871
872 spi0: spi@ff040000 {
873 compatible = "cdns,spi-r1p6";
874 status = "disabled";
875 interrupt-parent = <&gic>;
876 interrupts = <0 19 4>;
Michal Simekb976fd62016-02-11 07:19:06 +0100877 reg = <0x0 0xff040000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +0100878 clock-names = "ref_clk", "pclk";
879 #address-cells = <1>;
880 #size-cells = <0>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800881 power-domains = <&pd_spi0>;
Michal Simek44303df2015-10-30 15:39:18 +0100882 };
883
884 spi1: spi@ff050000 {
885 compatible = "cdns,spi-r1p6";
886 status = "disabled";
887 interrupt-parent = <&gic>;
888 interrupts = <0 20 4>;
Michal Simekb976fd62016-02-11 07:19:06 +0100889 reg = <0x0 0xff050000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +0100890 clock-names = "ref_clk", "pclk";
891 #address-cells = <1>;
892 #size-cells = <0>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800893 power-domains = <&pd_spi1>;
Michal Simek44303df2015-10-30 15:39:18 +0100894 };
895
896 ttc0: timer@ff110000 {
897 compatible = "cdns,ttc";
898 status = "disabled";
899 interrupt-parent = <&gic>;
900 interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
Michal Simekb976fd62016-02-11 07:19:06 +0100901 reg = <0x0 0xff110000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +0100902 timer-width = <32>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800903 power-domains = <&pd_ttc0>;
Michal Simek44303df2015-10-30 15:39:18 +0100904 };
905
906 ttc1: timer@ff120000 {
907 compatible = "cdns,ttc";
908 status = "disabled";
909 interrupt-parent = <&gic>;
910 interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
Michal Simekb976fd62016-02-11 07:19:06 +0100911 reg = <0x0 0xff120000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +0100912 timer-width = <32>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800913 power-domains = <&pd_ttc1>;
Michal Simek44303df2015-10-30 15:39:18 +0100914 };
915
916 ttc2: timer@ff130000 {
917 compatible = "cdns,ttc";
918 status = "disabled";
919 interrupt-parent = <&gic>;
920 interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
Michal Simekb976fd62016-02-11 07:19:06 +0100921 reg = <0x0 0xff130000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +0100922 timer-width = <32>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800923 power-domains = <&pd_ttc2>;
Michal Simek44303df2015-10-30 15:39:18 +0100924 };
925
926 ttc3: timer@ff140000 {
927 compatible = "cdns,ttc";
928 status = "disabled";
929 interrupt-parent = <&gic>;
930 interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
Michal Simekb976fd62016-02-11 07:19:06 +0100931 reg = <0x0 0xff140000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +0100932 timer-width = <32>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800933 power-domains = <&pd_ttc3>;
Michal Simek44303df2015-10-30 15:39:18 +0100934 };
935
936 uart0: serial@ff000000 {
Michal Simekc9811e12016-02-22 09:57:27 +0100937 u-boot,dm-pre-reloc;
Michal Simekca2f5872015-11-27 13:22:58 +0100938 compatible = "cdns,uart-r1p12", "xlnx,xuartps";
Michal Simek44303df2015-10-30 15:39:18 +0100939 status = "disabled";
940 interrupt-parent = <&gic>;
941 interrupts = <0 21 4>;
Michal Simekb976fd62016-02-11 07:19:06 +0100942 reg = <0x0 0xff000000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +0100943 clock-names = "uart_clk", "pclk";
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800944 power-domains = <&pd_uart0>;
Michal Simek44303df2015-10-30 15:39:18 +0100945 };
946
947 uart1: serial@ff010000 {
Michal Simekc9811e12016-02-22 09:57:27 +0100948 u-boot,dm-pre-reloc;
Michal Simekca2f5872015-11-27 13:22:58 +0100949 compatible = "cdns,uart-r1p12", "xlnx,xuartps";
Michal Simek44303df2015-10-30 15:39:18 +0100950 status = "disabled";
951 interrupt-parent = <&gic>;
952 interrupts = <0 22 4>;
Michal Simekb976fd62016-02-11 07:19:06 +0100953 reg = <0x0 0xff010000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +0100954 clock-names = "uart_clk", "pclk";
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800955 power-domains = <&pd_uart1>;
Michal Simek44303df2015-10-30 15:39:18 +0100956 };
957
Michal Simekc926e6f2016-11-11 13:21:04 +0100958 usb0: usb0 {
Michal Simeka84de482016-04-07 15:06:07 +0200959 #address-cells = <2>;
Michal Simekb976fd62016-02-11 07:19:06 +0100960 #size-cells = <2>;
Michal Simek44303df2015-10-30 15:39:18 +0100961 status = "disabled";
Michal Simeka84de482016-04-07 15:06:07 +0200962 compatible = "xlnx,zynqmp-dwc3";
963 clock-names = "bus_clk", "ref_clk";
964 clocks = <&clk125>, <&clk125>;
Michal Simekba6ad312016-04-06 10:43:23 +0200965 #stream-id-cells = <1>;
966 iommus = <&smmu 0x860>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800967 power-domains = <&pd_usb0>;
Michal Simeka84de482016-04-07 15:06:07 +0200968 ranges;
969
970 dwc3_0: dwc3@fe200000 {
971 compatible = "snps,dwc3";
972 status = "disabled";
Michal Simekb976fd62016-02-11 07:19:06 +0100973 reg = <0x0 0xfe200000 0x0 0x40000>;
Michal Simeka84de482016-04-07 15:06:07 +0200974 interrupt-parent = <&gic>;
975 interrupts = <0 65 4>;
976 /* snps,quirk-frame-length-adjustment = <0x20>; */
977 snps,refclk_fladj;
978 };
Michal Simek44303df2015-10-30 15:39:18 +0100979 };
980
Michal Simekc926e6f2016-11-11 13:21:04 +0100981 usb1: usb1 {
Michal Simeka84de482016-04-07 15:06:07 +0200982 #address-cells = <2>;
Michal Simekb976fd62016-02-11 07:19:06 +0100983 #size-cells = <2>;
Michal Simek44303df2015-10-30 15:39:18 +0100984 status = "disabled";
Michal Simeka84de482016-04-07 15:06:07 +0200985 compatible = "xlnx,zynqmp-dwc3";
986 clock-names = "bus_clk", "ref_clk";
987 clocks = <&clk125>, <&clk125>;
Michal Simekba6ad312016-04-06 10:43:23 +0200988 #stream-id-cells = <1>;
989 iommus = <&smmu 0x861>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800990 power-domains = <&pd_usb1>;
Michal Simeka84de482016-04-07 15:06:07 +0200991 ranges;
992
993 dwc3_1: dwc3@fe300000 {
994 compatible = "snps,dwc3";
995 status = "disabled";
Michal Simekb976fd62016-02-11 07:19:06 +0100996 reg = <0x0 0xfe300000 0x0 0x40000>;
Michal Simeka84de482016-04-07 15:06:07 +0200997 interrupt-parent = <&gic>;
998 interrupts = <0 70 4>;
999 /* snps,quirk-frame-length-adjustment = <0x20>; */
1000 snps,refclk_fladj;
1001 };
Michal Simek44303df2015-10-30 15:39:18 +01001002 };
1003
1004 watchdog0: watchdog@fd4d0000 {
1005 compatible = "cdns,wdt-r1p2";
1006 status = "disabled";
1007 interrupt-parent = <&gic>;
Punnaiah Choudary Kallurid3fd4332015-11-04 12:34:17 +05301008 interrupts = <0 113 1>;
Michal Simekb976fd62016-02-11 07:19:06 +01001009 reg = <0x0 0xfd4d0000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +01001010 timeout-sec = <10>;
1011 };
1012
1013 xilinx_drm: xilinx_drm {
1014 compatible = "xlnx,drm";
1015 status = "disabled";
1016 xlnx,encoder-slave = <&xlnx_dp>;
1017 xlnx,connector-type = "DisplayPort";
1018 xlnx,dp-sub = <&xlnx_dp_sub>;
1019 planes {
1020 xlnx,pixel-format = "rgb565";
1021 plane0 {
1022 dmas = <&xlnx_dpdma 3>;
Hyun Kwonbfe27982016-07-14 17:42:44 -07001023 dma-names = "dma0";
Michal Simek44303df2015-10-30 15:39:18 +01001024 };
1025 plane1 {
Hyun Kwonbfe27982016-07-14 17:42:44 -07001026 dmas = <&xlnx_dpdma 0>,
1027 <&xlnx_dpdma 1>,
1028 <&xlnx_dpdma 2>;
1029 dma-names = "dma0", "dma1", "dma2";
Michal Simek44303df2015-10-30 15:39:18 +01001030 };
1031 };
1032 };
1033
Hyun Kwon695d75a2015-11-23 17:12:54 -08001034 xlnx_dp: dp@fd4a0000 {
Michal Simek44303df2015-10-30 15:39:18 +01001035 compatible = "xlnx,v-dp";
1036 status = "disabled";
Michal Simekb976fd62016-02-11 07:19:06 +01001037 reg = <0x0 0xfd4a0000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +01001038 interrupts = <0 119 4>;
1039 interrupt-parent = <&gic>;
1040 clock-names = "aclk", "aud_clk";
1041 xlnx,dp-version = "v1.2";
1042 xlnx,max-lanes = <2>;
1043 xlnx,max-link-rate = <540000>;
1044 xlnx,max-bpc = <16>;
1045 xlnx,enable-ycrcb;
1046 xlnx,colormetry = "rgb";
1047 xlnx,bpc = <8>;
1048 xlnx,audio-chan = <2>;
1049 xlnx,dp-sub = <&xlnx_dp_sub>;
Hyun Kwon939cfea2015-11-23 17:12:55 -08001050 xlnx,max-pclock-frequency = <300000>;
Michal Simek44303df2015-10-30 15:39:18 +01001051 };
1052
1053 xlnx_dp_snd_card: dp_snd_card {
1054 compatible = "xlnx,dp-snd-card";
1055 status = "disabled";
1056 xlnx,dp-snd-pcm = <&xlnx_dp_snd_pcm0>, <&xlnx_dp_snd_pcm1>;
1057 xlnx,dp-snd-codec = <&xlnx_dp_snd_codec0>;
1058 };
1059
1060 xlnx_dp_snd_codec0: dp_snd_codec0 {
1061 compatible = "xlnx,dp-snd-codec";
1062 status = "disabled";
1063 clock-names = "aud_clk";
1064 };
1065
1066 xlnx_dp_snd_pcm0: dp_snd_pcm0 {
1067 compatible = "xlnx,dp-snd-pcm";
1068 status = "disabled";
1069 dmas = <&xlnx_dpdma 4>;
1070 dma-names = "tx";
1071 };
1072
1073 xlnx_dp_snd_pcm1: dp_snd_pcm1 {
1074 compatible = "xlnx,dp-snd-pcm";
1075 status = "disabled";
1076 dmas = <&xlnx_dpdma 5>;
1077 dma-names = "tx";
1078 };
1079
Hyun Kwon695d75a2015-11-23 17:12:54 -08001080 xlnx_dp_sub: dp_sub@fd4aa000 {
Michal Simek44303df2015-10-30 15:39:18 +01001081 compatible = "xlnx,dp-sub";
1082 status = "disabled";
Michal Simekb976fd62016-02-11 07:19:06 +01001083 reg = <0x0 0xfd4aa000 0x0 0x1000>,
1084 <0x0 0xfd4ab000 0x0 0x1000>,
1085 <0x0 0xfd4ac000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +01001086 reg-names = "blend", "av_buf", "aud";
1087 xlnx,output-fmt = "rgb";
Hyun Kwon939cfea2015-11-23 17:12:55 -08001088 xlnx,vid-fmt = "yuyv";
1089 xlnx,gfx-fmt = "rgb565";
Michal Simek44303df2015-10-30 15:39:18 +01001090 };
1091
1092 xlnx_dpdma: dma@fd4c0000 {
1093 compatible = "xlnx,dpdma";
1094 status = "disabled";
Michal Simekb976fd62016-02-11 07:19:06 +01001095 reg = <0x0 0xfd4c0000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +01001096 interrupts = <0 122 4>;
1097 interrupt-parent = <&gic>;
1098 clock-names = "axi_clk";
1099 dma-channels = <6>;
1100 #dma-cells = <1>;
Michal Simekc926e6f2016-11-11 13:21:04 +01001101 dma-video0channel {
Michal Simek44303df2015-10-30 15:39:18 +01001102 compatible = "xlnx,video0";
1103 };
Michal Simekc926e6f2016-11-11 13:21:04 +01001104 dma-video1channel {
Michal Simek44303df2015-10-30 15:39:18 +01001105 compatible = "xlnx,video1";
1106 };
Michal Simekc926e6f2016-11-11 13:21:04 +01001107 dma-video2channel {
Michal Simek44303df2015-10-30 15:39:18 +01001108 compatible = "xlnx,video2";
1109 };
Michal Simekc926e6f2016-11-11 13:21:04 +01001110 dma-graphicschannel {
Michal Simek44303df2015-10-30 15:39:18 +01001111 compatible = "xlnx,graphics";
1112 };
Michal Simekc926e6f2016-11-11 13:21:04 +01001113 dma-audio0channel {
Michal Simek44303df2015-10-30 15:39:18 +01001114 compatible = "xlnx,audio0";
1115 };
Michal Simekc926e6f2016-11-11 13:21:04 +01001116 dma-audio1channel {
Michal Simek44303df2015-10-30 15:39:18 +01001117 compatible = "xlnx,audio1";
1118 };
1119 };
1120 };
1121};