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wdenk682011f2003-06-03 23:54:09 +00001/*
2 * (C) Copyright 2000, 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * Modified by Udi Finkelstein udif@udif.com
6 * For the RBC823 board.
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27/*
28 * board/config.h - configuration options, board specific
29 */
30
31#ifndef __CONFIG_H
32#define __CONFIG_H
33
34/*
35 * High Level Configuration Options
36 * (easy to change)
37 */
38
39#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
40#define CONFIG_RBC823 1 /* ...on a RBC823 module */
41
42
43#if 0
44#define DEBUG 1
45#define CONFIG_LAST_STAGE_INIT
46#endif
47#define CONFIG_KEYBOARD 1 /* This board has a custom keybpard */
48#define CONFIG_LCD 1 /* use LCD controller ... */
49#define CONFIG_HITACHI_SP19X001_Z1A /* The LCD type we use */
50
51#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
52#undef CONFIG_8xx_CONS_SMC1
53#undef CONFIG_8xx_CONS_NONE
54#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
55#if 1
56#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
57#else
58#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
59#endif
60
61#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
62#define CONFIG_8xx_GCLK_FREQ 48000000L
63
64#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
65
66#undef CONFIG_BOOTARGS
67#define CONFIG_BOOTCOMMAND \
68 "bootp; " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010069 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
70 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
wdenk682011f2003-06-03 23:54:09 +000071 "bootm"
72
73#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
74#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
75
76#undef CONFIG_WATCHDOG /* watchdog disabled */
77
78#define CONFIG_STATUS_LED 1 /* Status LED enabled */
79
80#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
81
Jon Loeliger18225e82007-07-09 21:31:24 -050082/*
83 * BOOTP options
84 */
85#define CONFIG_BOOTP_SUBNETMASK
86#define CONFIG_BOOTP_GATEWAY
87#define CONFIG_BOOTP_HOSTNAME
88#define CONFIG_BOOTP_BOOTPATH
89#define CONFIG_BOOTP_BOOTFILESIZE
90
wdenk682011f2003-06-03 23:54:09 +000091
92#undef CONFIG_MAC_PARTITION
93#define CONFIG_DOS_PARTITION
94
95#undef CONFIG_RTC_MPC8xx /* don't use internal RTC of MPC8xx (no battery) */
96
97#define CONFIG_HARD_I2C
98#define CFG_I2C_SPEED 40000
99#define CFG_I2C_SLAVE 0xfe
wdenkb79a11c2004-03-25 15:14:43 +0000100#define CFG_I2C_EEPROM_ADDR 0x50
101#define CFG_I2C_EEPROM_ADDR_LEN 1
102#define CFG_EEPROM_WRITE_BITS 4
103#define CFG_EEPROM_WRITE_DELAY_MS 10
wdenk682011f2003-06-03 23:54:09 +0000104
Jon Loeligere9a0f8f2007-07-08 15:12:40 -0500105/*
106 * Command line configuration.
107 */
108#include <config_cmd_all.h>
wdenk682011f2003-06-03 23:54:09 +0000109
Jon Loeligere9a0f8f2007-07-08 15:12:40 -0500110#undef CONFIG_CMD_BSP
111#undef CONFIG_CMD_DATE
112#undef CONFIG_CMD_DISPLAY
113#undef CONFIG_CMD_DTT
114#undef CONFIG_CMD_EXT2
115#undef CONFIG_CMD_FDC
116#undef CONFIG_CMD_FDOS
117#undef CONFIG_CMD_HWFLOW
118#undef CONFIG_CMD_IDE
119#undef CONFIG_CMD_IRQ
120#undef CONFIG_CMD_JFFS2
121#undef CONFIG_CMD_MII
Wolfgang Denkcdd917a2007-08-02 00:48:45 +0200122#undef CONFIG_CMD_MFSL
Jon Loeligere9a0f8f2007-07-08 15:12:40 -0500123#undef CONFIG_CMD_MMC
124#undef CONFIG_CMD_NAND
125#undef CONFIG_CMD_PCI
126#undef CONFIG_CMD_PCMCIA
127#undef CONFIG_CMD_REISER
128#undef CONFIG_CMD_SCSI
129#undef CONFIG_CMD_SETGETDCR
130#undef CONFIG_CMD_SNTP
131#undef CONFIG_CMD_SPI
132#undef CONFIG_CMD_UNIVERSE
133#undef CONFIG_CMD_USB
134#undef CONFIG_CMD_VFD
135#undef CONFIG_CMD_XIMG
136
wdenk682011f2003-06-03 23:54:09 +0000137
138/*
139 * Miscellaneous configurable options
140 */
141#define CFG_LONGHELP /* undef to save memory */
142#define CFG_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeligere9a0f8f2007-07-08 15:12:40 -0500143#if defined(CONFIG_CMD_KGDB)
wdenk682011f2003-06-03 23:54:09 +0000144#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
145#else
146#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
147#endif
148#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
149#define CFG_MAXARGS 16 /* max number of command args */
150#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
151
152#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
153#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
154
155#define CFG_LOAD_ADDR 0x0100000 /* default load address */
156
157#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
158
159#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
160
161/*
162 * Low Level Configuration Settings
163 * (address mappings, register initial values, etc.)
164 * You should know what you are doing if you make changes here.
165 */
166/*-----------------------------------------------------------------------
167 * Internal Memory Mapped Register
168 */
169#define CFG_IMMR 0xFF000000
170
171/*-----------------------------------------------------------------------
172 * Definitions for initial stack pointer and data area (in DPRAM)
173 */
174#define CFG_INIT_RAM_ADDR CFG_IMMR
175#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
176#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
177#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
178#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
179
180/*-----------------------------------------------------------------------
181 * Start addresses for the final memory configuration
182 * (Set up by the startup code)
183 * Please note that CFG_SDRAM_BASE _must_ start at 0
184 */
185#define CFG_SDRAM_BASE 0x00000000
186#define CFG_FLASH_BASE 0xFFF00000
187#if defined(DEBUG)
188#define CFG_MONITOR_LEN (384 << 10) /* Reserve 256 kB for Monitor */
189#else
190#define CFG_MONITOR_LEN (384 << 10) /* Reserve 192 kB for Monitor */
191#endif
192#define CFG_MONITOR_BASE CFG_FLASH_BASE
193#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
194
195/*
196 * For booting Linux, the board info and command line data
197 * have to be in the first 8 MB of memory, since this is
198 * the maximum mapped by the Linux kernel during initialization.
199 */
200#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
201
202/*-----------------------------------------------------------------------
203 * FLASH organization
204 */
205#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
206#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
207
208#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
209#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
210
211#define CFG_ENV_IS_IN_FLASH 1
212#define CFG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */
213#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
214
215/*-----------------------------------------------------------------------
216 * Cache Configuration
217 */
218#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeligere9a0f8f2007-07-08 15:12:40 -0500219#if defined(CONFIG_CMD_KGDB)
wdenk682011f2003-06-03 23:54:09 +0000220#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
221#endif
222
223/*-----------------------------------------------------------------------
224 * SYPCR - System Protection Control 11-9
225 * SYPCR can only be written once after reset!
226 *-----------------------------------------------------------------------
227 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
228 */
229#if defined(CONFIG_WATCHDOG)
230#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
231 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
232#else
233/*
234#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
235*/
236#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWRI | SYPCR_SWP)
237#endif
238
239/*-----------------------------------------------------------------------
240 * SIUMCR - SIU Module Configuration 11-6
241 *-----------------------------------------------------------------------
242 * PCMCIA config., multi-function pin tri-state
243 */
244#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC00 | SIUMCR_FRC)
245
246/*-----------------------------------------------------------------------
247 * TBSCR - Time Base Status and Control 11-26
248 *-----------------------------------------------------------------------
249 * Clear Reference Interrupt Status, Timebase freezing enabled
250 */
251#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
252
253/*-----------------------------------------------------------------------
254 * RTCSC - Real-Time Clock Status and Control Register 11-27
255 *-----------------------------------------------------------------------
256 */
257#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
258
259/*-----------------------------------------------------------------------
260 * PISCR - Periodic Interrupt Status and Control 11-31
261 *-----------------------------------------------------------------------
262 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
263 */
264#define CFG_PISCR (PISCR_PS | PISCR_PITF)
265
266/*-----------------------------------------------------------------------
267 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
268 *-----------------------------------------------------------------------
269 * Reset PLL lock status sticky bit, timer expired status bit and timer
270 * interrupt status bit
271 *
272 */
273
274/*
275 * for 48 MHz, we use a 4 MHz clock * 12
276 */
277#define CFG_PLPRCR \
278 ( (12-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_LOLRE )
279
280/*-----------------------------------------------------------------------
281 * SCCR - System Clock and reset Control Register 15-27
282 *-----------------------------------------------------------------------
283 * Set clock output, timebase and RTC source and divider,
284 * power management and some other internal clocks
285 */
286#define SCCR_MASK SCCR_EBDF11
287#define CFG_SCCR (SCCR_RTDIV | SCCR_RTSEL | SCCR_CRQEN | \
288 SCCR_PRQEN | SCCR_EBDF00 | \
289 SCCR_COM01 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
290 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD001 | \
291 SCCR_DFALCD00)
292
293#ifdef NOT_USED
294/*-----------------------------------------------------------------------
295 * PCMCIA stuff
296 *-----------------------------------------------------------------------
297 *
298 */
299#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
300#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
301#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
302#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
303#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
304#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
305#define CFG_PCMCIA_IO_ADDR (0xEC000000)
306#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
307
308/*-----------------------------------------------------------------------
309 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
310 *-----------------------------------------------------------------------
311 */
312
313#define CONFIG_IDE_PCCARD 1 /* Use IDE with PC Card Adapter */
314
315#undef CONFIG_IDE_PCMCIA /* Direct IDE not supported */
316#undef CONFIG_IDE_LED /* LED for ide not supported */
317#undef CONFIG_IDE_RESET /* reset for ide not supported */
318
319#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
320#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
321
322#define CFG_ATA_IDE0_OFFSET 0x0000
323
324#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
325
326/* Offset for data I/O */
327#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
328
329/* Offset for normal register accesses */
330#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
331
332/* Offset for alternate registers */
333#define CFG_ATA_ALT_OFFSET 0x0100
334
335#endif
336
337/************************************************************
338 * Disk-On-Chip configuration
339 ************************************************************/
340#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
341#define CFG_DOC_SHORT_TIMEOUT
342#define CFG_DOC_SUPPORT_2000
343#define CFG_DOC_SUPPORT_MILLENNIUM
344
345/*-----------------------------------------------------------------------
346 *
347 *-----------------------------------------------------------------------
348 *
349 */
350/*#define CFG_DER 0x2002000F*/
351#define CFG_DER 0
352
353/*
354 * Init Memory Controller:
355 *
356 * BR0/1 and OR0/1 (FLASH)
357 */
358
359#define FLASH_BASE0_PRELIM 0xFFF00000 /* FLASH bank #0 */
360#define FLASH_BASE1_PRELIM 0x04000000 /* D.O.C Millenium */
361
362/* used to re-map FLASH both when starting from SRAM or FLASH:
363 * restrict access enough to keep SRAM working (if any)
364 * but not too much to meddle with FLASH accesses
365 */
366#define CFG_PRELIM_OR_AM 0xFFF80000 /* OR addr mask */
367
368/* FLASH timing: ACS = 00, TRLX = 0, CSNT = 1, SCY = 7, EHTR = 1 */
369#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_BI | OR_SCY_7_CLK | OR_EHTR)
370
371#define CFG_OR_TIMING_MSYS (OR_ACS_DIV1 | OR_BI)
372
373#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
374#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V)
375
376#define CFG_OR1_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_MSYS)
377#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMB | \
378 BR_PS_8 | BR_V)
379
380/*
381 * BR4 and OR4 (SDRAM)
382 *
383 */
384#define SDRAM_BASE4_PRELIM 0x00000000 /* SDRAM bank #0 */
385#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
386
387/*
388 * SDRAM timing:
389 */
390#define CFG_OR_TIMING_SDRAM (OR_CSNT_SAM)
391
392#define CFG_OR4_PRELIM (~(SDRAM_MAX_SIZE-1) | CFG_OR_TIMING_SDRAM )
393#define CFG_BR4_PRELIM ((SDRAM_BASE4_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
394
395/*
396 * Memory Periodic Timer Prescaler
397 */
398
399/* periodic timer for refresh */
400#define CFG_MAMR_PTA 187 /* start with divider for 48 MHz */
401
402/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
403#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
404#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
405
406/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
407#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
408#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
409
410/*
411 * MAMR settings for SDRAM
412 */
413
414/* 8 column SDRAM */
415#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
416 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
417 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
418/* 9 column SDRAM */
419#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
420 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
421 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
422
423
424/*
425 * Internal Definitions
426 *
427 * Boot Flags
428 */
429#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
430#define BOOTFLAG_WARM 0x02 /* Software reboot */
431
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200432/*
433 * JFFS2 partitions
434 *
435 */
436/* No command line, one static partition, whole device */
437#undef CONFIG_JFFS2_CMDLINE
438#define CONFIG_JFFS2_DEV "nor0"
439#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
440#define CONFIG_JFFS2_PART_OFFSET 0x00000000
441
442/* mtdparts command line support */
443/* Note: fake mtd_id used, no linux mtd map file */
444/*
445#define CONFIG_JFFS2_CMDLINE
446#define MTDIDS_DEFAULT ""
447#define MTDPARTS_DEFAULT ""
448*/
449
wdenk682011f2003-06-03 23:54:09 +0000450#endif /* __CONFIG_H */