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wdenkedc48b62002-09-08 17:56:50 +00001/*
2 * (C) Copyright 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenkedc48b62002-09-08 17:56:50 +00006 */
7
8/* for now: just dummy functions to satisfy the linker */
9
wdenk8ed96042005-01-09 23:16:25 +000010#include <common.h>
Thierry Reding1dfdd9b2014-12-09 22:25:22 -070011#include <malloc.h>
wdenk8ed96042005-01-09 23:16:25 +000012
Wu, Josh633b6cc2015-07-27 11:40:17 +080013/*
14 * Flush range from all levels of d-cache/unified-cache.
15 * Affects the range [start, start + size - 1].
16 */
Jeroen Hofsteefcfddfd2014-06-23 22:07:04 +020017__weak void flush_cache(unsigned long start, unsigned long size)
wdenkedc48b62002-09-08 17:56:50 +000018{
Wu, Josh633b6cc2015-07-27 11:40:17 +080019 flush_dcache_range(start, start + size);
wdenkedc48b62002-09-08 17:56:50 +000020}
Aneesh Ve05f0072011-06-16 23:30:50 +000021
22/*
23 * Default implementation:
24 * do a range flush for the entire range
25 */
Jeroen Hofsteefcfddfd2014-06-23 22:07:04 +020026__weak void flush_dcache_all(void)
Aneesh Ve05f0072011-06-16 23:30:50 +000027{
28 flush_cache(0, ~0);
29}
Aneesh Vcba4b182011-08-16 04:33:05 +000030
31/*
32 * Default implementation of enable_caches()
33 * Real implementation should be in platform code
34 */
Jeroen Hofsteefcfddfd2014-06-23 22:07:04 +020035__weak void enable_caches(void)
Aneesh Vcba4b182011-08-16 04:33:05 +000036{
37 puts("WARNING: Caches not enabled\n");
38}
Thierry Reding1dfdd9b2014-12-09 22:25:22 -070039
Wu, Josh387871a2015-07-27 11:40:16 +080040__weak void invalidate_dcache_range(unsigned long start, unsigned long stop)
41{
42 /* An empty stub, real implementation should be in platform code */
43}
44__weak void flush_dcache_range(unsigned long start, unsigned long stop)
45{
46 /* An empty stub, real implementation should be in platform code */
47}
48
Simon Glass397b5692016-06-19 19:43:01 -060049int check_cache_range(unsigned long start, unsigned long stop)
50{
51 int ok = 1;
52
53 if (start & (CONFIG_SYS_CACHELINE_SIZE - 1))
54 ok = 0;
55
56 if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1))
57 ok = 0;
58
59 if (!ok) {
Simon Glassbcc53bf2016-06-19 19:43:05 -060060 warn_non_spl("CACHE: Misaligned operation at range [%08lx, %08lx]\n",
61 start, stop);
Simon Glass397b5692016-06-19 19:43:01 -060062 }
63
64 return ok;
65}
66
Thierry Reding1dfdd9b2014-12-09 22:25:22 -070067#ifdef CONFIG_SYS_NONCACHED_MEMORY
68/*
69 * Reserve one MMU section worth of address space below the malloc() area that
70 * will be mapped uncached.
71 */
72static unsigned long noncached_start;
73static unsigned long noncached_end;
74static unsigned long noncached_next;
75
76void noncached_init(void)
77{
78 phys_addr_t start, end;
79 size_t size;
80
81 end = ALIGN(mem_malloc_start, MMU_SECTION_SIZE) - MMU_SECTION_SIZE;
82 size = ALIGN(CONFIG_SYS_NONCACHED_MEMORY, MMU_SECTION_SIZE);
83 start = end - size;
84
85 debug("mapping memory %pa-%pa non-cached\n", &start, &end);
86
87 noncached_start = start;
88 noncached_end = end;
89 noncached_next = start;
90
91#ifndef CONFIG_SYS_DCACHE_OFF
92 mmu_set_region_dcache_behaviour(noncached_start, size, DCACHE_OFF);
93#endif
94}
95
96phys_addr_t noncached_alloc(size_t size, size_t align)
97{
98 phys_addr_t next = ALIGN(noncached_next, align);
99
100 if (next >= noncached_end || (noncached_end - next) < size)
101 return 0;
102
103 debug("allocated %zu bytes of uncached memory @%pa\n", size, &next);
104 noncached_next = next + size;
105
106 return next;
107}
108#endif /* CONFIG_SYS_NONCACHED_MEMORY */
Albert ARIBAUD62e92072015-10-23 18:06:40 +0200109
110#if defined(CONFIG_SYS_THUMB_BUILD)
111void invalidate_l2_cache(void)
112{
113 unsigned int val = 0;
114
115 asm volatile("mcr p15, 1, %0, c15, c11, 0 @ invl l2 cache"
116 : : "r" (val) : "cc");
117 isb();
118}
119#endif