blob: 16c30d09dc73e4105e4406b62a295f6f4cee7fa3 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Wang Huanc8a7d9d2014-09-05 13:52:45 +08002/*
3 * Copyright 2014 Freescale Semiconductor, Inc.
Biwen Li9ebde882019-12-31 15:33:44 +08004 * Copyright 2019 NXP
Wang Huanc8a7d9d2014-09-05 13:52:45 +08005 */
6
7#ifndef __CONFIG_H
8#define __CONFIG_H
9
Hongbo Zhangaeb901f2016-07-21 18:09:38 +080010#define CONFIG_ARMV7_PSCI_1_0
Wang Dongsheng340848b2015-06-04 12:01:09 +080011
Hongbo Zhang32886282016-07-21 18:09:39 +080012#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
13
Gong Qianyu18fb0e32015-10-26 19:47:42 +080014#define CONFIG_SYS_FSL_CLK
Wang Huanc8a7d9d2014-09-05 13:52:45 +080015
Wang Huanc8a7d9d2014-09-05 13:52:45 +080016#define CONFIG_SKIP_LOWLEVEL_INIT
Tang Yuantian99e1bd42015-05-14 17:20:28 +080017#define CONFIG_DEEP_SLEEP
Wang Huanc8a7d9d2014-09-05 13:52:45 +080018
19/*
20 * Size of malloc() pool
21 */
22#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
23
24#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
25#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
26
Wang Huanc8a7d9d2014-09-05 13:52:45 +080027#define CONFIG_SYS_CLK_FREQ 100000000
28#define CONFIG_DDR_CLK_FREQ 100000000
29
York Suna88cc3b2015-04-29 10:35:35 -070030#define DDR_SDRAM_CFG 0x470c0008
31#define DDR_CS0_BNDS 0x008000bf
32#define DDR_CS0_CONFIG 0x80014302
33#define DDR_TIMING_CFG_0 0x50550004
34#define DDR_TIMING_CFG_1 0xbcb38c56
35#define DDR_TIMING_CFG_2 0x0040d120
36#define DDR_TIMING_CFG_3 0x010e1000
37#define DDR_TIMING_CFG_4 0x00000001
38#define DDR_TIMING_CFG_5 0x03401400
39#define DDR_SDRAM_CFG_2 0x00401010
40#define DDR_SDRAM_MODE 0x00061c60
41#define DDR_SDRAM_MODE_2 0x00180000
42#define DDR_SDRAM_INTERVAL 0x18600618
43#define DDR_DDR_WRLVL_CNTL 0x8655f605
44#define DDR_DDR_WRLVL_CNTL_2 0x05060607
45#define DDR_DDR_WRLVL_CNTL_3 0x05050505
46#define DDR_DDR_CDR1 0x80040000
47#define DDR_DDR_CDR2 0x00000001
48#define DDR_SDRAM_CLK_CNTL 0x02000000
49#define DDR_DDR_ZQ_CNTL 0x89080600
50#define DDR_CS0_CONFIG_2 0
51#define DDR_SDRAM_CFG_MEM_EN 0x80000000
Tang Yuantian99e1bd42015-05-14 17:20:28 +080052#define SDRAM_CFG2_D_INIT 0x00000010
53#define DDR_CDR2_VREF_TRAIN_EN 0x00000080
54#define SDRAM_CFG2_FRC_SR 0x80000000
55#define SDRAM_CFG_BI 0x00000001
York Suna88cc3b2015-04-29 10:35:35 -070056
Alison Wang8415bb62014-12-03 15:00:48 +080057#ifdef CONFIG_RAMBOOT_PBL
58#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg
59#endif
60
61#ifdef CONFIG_SD_BOOT
Alison Wang947cee12015-10-15 17:54:40 +080062#ifdef CONFIG_SD_BOOT_QSPI
63#define CONFIG_SYS_FSL_PBL_RCW \
64 board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg
65#else
66#define CONFIG_SYS_FSL_PBL_RCW \
67 board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg
68#endif
Sumit Garge7e720c2016-06-14 13:52:40 -040069
Udit Agarwal5536c3c2019-11-07 16:11:32 +000070#ifdef CONFIG_NXP_ESBC
Sumit Garge7e720c2016-06-14 13:52:40 -040071/*
72 * HDR would be appended at end of image and copied to DDR along
73 * with U-Boot image.
74 */
Semen Protsenko693d4c92016-11-16 19:19:06 +020075#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
Udit Agarwal5536c3c2019-11-07 16:11:32 +000076#endif /* ifdef CONFIG_NXP_ESBC */
Alison Wang8415bb62014-12-03 15:00:48 +080077
Alison Wang8415bb62014-12-03 15:00:48 +080078#define CONFIG_SPL_MAX_SIZE 0x1a000
79#define CONFIG_SPL_STACK 0x1001d000
80#define CONFIG_SPL_PAD_TO 0x1c000
Alison Wang8415bb62014-12-03 15:00:48 +080081
Tang Yuantian99e1bd42015-05-14 17:20:28 +080082#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
83 CONFIG_SYS_MONITOR_LEN)
Alison Wang8415bb62014-12-03 15:00:48 +080084#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
85#define CONFIG_SPL_BSS_START_ADDR 0x80100000
86#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
Sumit Garge7e720c2016-06-14 13:52:40 -040087
88#ifdef CONFIG_U_BOOT_HDR_SIZE
89/*
90 * HDR would be appended at end of image and copied to DDR along
91 * with U-Boot image. Here u-boot max. size is 512K. So if binary
92 * size increases then increase this size in case of secure boot as
93 * it uses raw u-boot image instead of fit image.
94 */
Vinitha Pillai9b6639f2017-02-01 18:28:53 +053095#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
Sumit Garge7e720c2016-06-14 13:52:40 -040096#else
Vinitha Pillai9b6639f2017-02-01 18:28:53 +053097#define CONFIG_SYS_MONITOR_LEN 0x100000
Sumit Garge7e720c2016-06-14 13:52:40 -040098#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
Alison Wang8415bb62014-12-03 15:00:48 +080099#endif
100
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800101#define PHYS_SDRAM 0x80000000
102#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
103
104#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
105#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
106
Alison Wang15809702019-03-06 14:49:14 +0800107#define CONFIG_CHIP_SELECTS_PER_CTRL 4
108
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800109/*
110 * IFC Definitions
111 */
Alison Wang947cee12015-10-15 17:54:40 +0800112#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800113#define CONFIG_FSL_IFC
114#define CONFIG_SYS_FLASH_BASE 0x60000000
115#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
116
117#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
118#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
119 CSPR_PORT_SIZE_16 | \
120 CSPR_MSEL_NOR | \
121 CSPR_V)
122#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
123
124/* NOR Flash Timing Params */
125#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
126 CSOR_NOR_TRHZ_80)
127#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
128 FTIM0_NOR_TEADC(0x5) | \
129 FTIM0_NOR_TAVDS(0x0) | \
130 FTIM0_NOR_TEAHC(0x5))
131#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
132 FTIM1_NOR_TRAD_NOR(0x1A) | \
133 FTIM1_NOR_TSEQRAD_NOR(0x13))
134#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
135 FTIM2_NOR_TCH(0x4) | \
136 FTIM2_NOR_TWP(0x1c) | \
137 FTIM2_NOR_TWPH(0x0e))
138#define CONFIG_SYS_NOR_FTIM3 0
139
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800140#define CONFIG_SYS_FLASH_QUIET_TEST
141#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
142
143#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
144#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
145#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
146#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
147
148#define CONFIG_SYS_FLASH_EMPTY_INFO
149#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
150
151#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
Yuan Yao272c5262014-10-17 15:26:34 +0800152#define CONFIG_SYS_WRITE_SWAPPED_DATA
Alison Wangd612f0a2014-12-09 17:38:02 +0800153#endif
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800154
155/* CPLD */
156
157#define CONFIG_SYS_CPLD_BASE 0x7fb00000
158#define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
159
160#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
161#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
162 CSPR_PORT_SIZE_8 | \
163 CSPR_MSEL_GPCM | \
164 CSPR_V)
165#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
166#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
167 CSOR_NOR_NOR_MODE_AVD_NOR | \
168 CSOR_NOR_TRHZ_80)
169
170/* CPLD Timing parameters for IFC GPCM */
171#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \
172 FTIM0_GPCM_TEADC(0xf) | \
173 FTIM0_GPCM_TEAHC(0xf))
174#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
175 FTIM1_GPCM_TRAD(0x3f))
176#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
177 FTIM2_GPCM_TCH(0xf) | \
178 FTIM2_GPCM_TWP(0xff))
179#define CONFIG_SYS_FPGA_FTIM3 0x0
180#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
181#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
182#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
183#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
184#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
185#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
186#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
187#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
188#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT
189#define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR
190#define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK
191#define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR
192#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0
193#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1
194#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2
195#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3
196
197/*
198 * Serial Port
199 */
Alison Wang55d53ab2015-01-04 15:30:59 +0800200#ifdef CONFIG_LPUART
Alison Wang55d53ab2015-01-04 15:30:59 +0800201#define CONFIG_LPUART_32B_REG
202#else
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800203#define CONFIG_SYS_NS16550_SERIAL
Bin Mengf833cd62016-01-13 19:38:59 -0800204#ifndef CONFIG_DM_SERIAL
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800205#define CONFIG_SYS_NS16550_REG_SIZE 1
Bin Mengf833cd62016-01-13 19:38:59 -0800206#endif
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800207#define CONFIG_SYS_NS16550_CLK get_serial_clock()
Alison Wang55d53ab2015-01-04 15:30:59 +0800208#endif
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800209
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800210/*
211 * I2C
212 */
Biwen Li9ebde882019-12-31 15:33:44 +0800213#ifndef CONFIG_DM_I2C
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800214#define CONFIG_SYS_I2C
Biwen Li9ebde882019-12-31 15:33:44 +0800215#else
216#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
217#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
218#endif
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800219#define CONFIG_SYS_I2C_MXC
Albert ARIBAUD \\(3ADEV\\)03544c62015-09-21 22:43:38 +0200220#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
221#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
York Sunf8cb1012015-03-20 10:20:40 -0700222#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800223
Alison Wang5175a282014-10-17 15:26:35 +0800224/* EEPROM */
Alison Wang5175a282014-10-17 15:26:35 +0800225#define CONFIG_ID_EEPROM
226#define CONFIG_SYS_I2C_EEPROM_NXID
227#define CONFIG_SYS_EEPROM_BUS_NUM 1
228#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
229#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
230#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
231#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
Alison Wang5175a282014-10-17 15:26:35 +0800232
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800233/*
234 * MMC
235 */
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800236
237/*
Wang Huanb4ecc8c2014-09-05 13:52:50 +0800238 * Video
239 */
Sanchayan Maityb215fb32017-04-11 11:12:09 +0530240#ifdef CONFIG_VIDEO_FSL_DCU_FB
Wang Huanb4ecc8c2014-09-05 13:52:50 +0800241#define CONFIG_VIDEO_LOGO
242#define CONFIG_VIDEO_BMP_LOGO
243
244#define CONFIG_FSL_DCU_SII9022A
245#define CONFIG_SYS_I2C_DVI_BUS_NUM 1
246#define CONFIG_SYS_I2C_DVI_ADDR 0x39
247#endif
248
249/*
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800250 * eTSEC
251 */
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800252
253#ifdef CONFIG_TSEC_ENET
Bin Mengf588b4d2019-07-19 00:29:59 +0300254#define CONFIG_ETHPRIME "ethernet@2d10000"
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800255#endif
256
Minghuan Lianda419022014-10-31 13:43:44 +0800257/* PCIe */
Robert P. J. Dayb38eaec2016-05-03 19:52:49 -0400258#define CONFIG_PCIE1 /* PCIE controller 1 */
259#define CONFIG_PCIE2 /* PCIE controller 2 */
Minghuan Lianda419022014-10-31 13:43:44 +0800260
Minghuan Lian180b8682015-01-21 17:29:19 +0800261#ifdef CONFIG_PCI
Minghuan Lian180b8682015-01-21 17:29:19 +0800262#define CONFIG_PCI_SCAN_SHOW
Minghuan Lian180b8682015-01-21 17:29:19 +0800263#endif
264
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800265#define CONFIG_CMDLINE_TAG
Alison Wang8415bb62014-12-03 15:00:48 +0800266
Xiubo Li1a2826f2014-11-21 17:40:57 +0800267#define CONFIG_PEN_ADDR_BIG_ENDIAN
Mingkai Hu435acd82015-10-26 19:47:41 +0800268#define CONFIG_LAYERSCAPE_NS_ACCESS
Xiubo Li1a2826f2014-11-21 17:40:57 +0800269#define CONFIG_SMP_PEN_ADDR 0x01ee0200
Andre Przywarae4916e82017-02-16 01:20:19 +0000270#define COUNTER_FREQUENCY 12500000
Xiubo Li1a2826f2014-11-21 17:40:57 +0800271
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800272#define CONFIG_HWCONFIG
Zhuoyu Zhang03c22442015-08-17 18:55:12 +0800273#define HWCONFIG_BUFFER_SIZE 256
274
275#define CONFIG_FSL_DEVICE_DISABLE
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800276
Alison Wanga65d7402017-05-26 15:46:15 +0800277#define BOOT_TARGET_DEVICES(func) \
278 func(MMC, mmc, 0) \
Yunfeng Dingd2c49aa2019-02-19 14:44:04 +0800279 func(USB, usb, 0) \
280 func(DHCP, dhcp, na)
Alison Wanga65d7402017-05-26 15:46:15 +0800281#include <config_distro_bootcmd.h>
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800282
Alison Wang55d53ab2015-01-04 15:30:59 +0800283#ifdef CONFIG_LPUART
284#define CONFIG_EXTRA_ENV_SETTINGS \
Alison Wang33c3dfd2020-04-23 22:37:34 +0800285 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200 " \
286 "cma=64M@0x0-0xb0000000\0" \
Alison Wang7ff71662015-10-26 14:08:28 +0800287 "initrd_high=0xffffffff\0" \
Alison Wanga65d7402017-05-26 15:46:15 +0800288 "fdt_addr=0x64f00000\0" \
289 "kernel_addr=0x65000000\0" \
290 "scriptaddr=0x80000000\0" \
Sumit Gargb8ae6792017-06-06 20:51:31 +0530291 "scripthdraddr=0x80080000\0" \
Alison Wanga65d7402017-05-26 15:46:15 +0800292 "fdtheader_addr_r=0x80100000\0" \
293 "kernelheader_addr_r=0x80200000\0" \
294 "kernel_addr_r=0x81000000\0" \
295 "fdt_addr_r=0x90000000\0" \
296 "ramdisk_addr_r=0xa0000000\0" \
297 "load_addr=0xa0000000\0" \
298 "kernel_size=0x2800000\0" \
Shengzhou Liu397a1732017-11-09 17:57:57 +0800299 "kernel_addr_sd=0x8000\0" \
300 "kernel_size_sd=0x14000\0" \
Alison Wangfeb8fa22020-01-21 07:33:01 +0000301 "othbootargs=cma=64M@0x0-0xb0000000\0" \
Alison Wanga65d7402017-05-26 15:46:15 +0800302 BOOTENV \
303 "boot_scripts=ls1021atwr_boot.scr\0" \
Sumit Gargb8ae6792017-06-06 20:51:31 +0530304 "boot_script_hdr=hdr_ls1021atwr_bs.out\0" \
Alison Wanga65d7402017-05-26 15:46:15 +0800305 "scan_dev_for_boot_part=" \
306 "part list ${devtype} ${devnum} devplist; " \
307 "env exists devplist || setenv devplist 1; " \
308 "for distro_bootpart in ${devplist}; do " \
309 "if fstype ${devtype} " \
310 "${devnum}:${distro_bootpart} " \
311 "bootfstype; then " \
312 "run scan_dev_for_boot; " \
313 "fi; " \
314 "done\0" \
Sumit Gargb8ae6792017-06-06 20:51:31 +0530315 "scan_dev_for_boot=" \
316 "echo Scanning ${devtype} " \
317 "${devnum}:${distro_bootpart}...; " \
318 "for prefix in ${boot_prefixes}; do " \
319 "run scan_dev_for_scripts; " \
320 "done;" \
321 "\0" \
322 "boot_a_script=" \
323 "load ${devtype} ${devnum}:${distro_bootpart} " \
324 "${scriptaddr} ${prefix}${script}; " \
325 "env exists secureboot && load ${devtype} " \
326 "${devnum}:${distro_bootpart} " \
Vinitha V Pillai78c58082019-04-23 05:52:17 +0000327 "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
328 "env exists secureboot " \
Sumit Gargb8ae6792017-06-06 20:51:31 +0530329 "&& esbc_validate ${scripthdraddr};" \
330 "source ${scriptaddr}\0" \
Alison Wanga65d7402017-05-26 15:46:15 +0800331 "installer=load mmc 0:2 $load_addr " \
332 "/flex_installer_arm32.itb; " \
333 "bootm $load_addr#ls1021atwr\0" \
334 "qspi_bootcmd=echo Trying load from qspi..;" \
335 "sf probe && sf read $load_addr " \
336 "$kernel_addr $kernel_size && bootm $load_addr#$board\0" \
337 "nor_bootcmd=echo Trying load from nor..;" \
338 "cp.b $kernel_addr $load_addr " \
339 "$kernel_size && bootm $load_addr#$board\0"
Alison Wang55d53ab2015-01-04 15:30:59 +0800340#else
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800341#define CONFIG_EXTRA_ENV_SETTINGS \
Alison Wang33c3dfd2020-04-23 22:37:34 +0800342 "bootargs=root=/dev/ram0 rw console=ttyS0,115200 " \
343 "cma=64M@0x0-0xb0000000\0" \
Alison Wang7ff71662015-10-26 14:08:28 +0800344 "initrd_high=0xffffffff\0" \
Alison Wanga65d7402017-05-26 15:46:15 +0800345 "fdt_addr=0x64f00000\0" \
Vinitha Pillai-B572239b457cc2017-11-22 10:38:35 +0530346 "kernel_addr=0x61000000\0" \
347 "kernelheader_addr=0x60800000\0" \
Alison Wanga65d7402017-05-26 15:46:15 +0800348 "scriptaddr=0x80000000\0" \
Sumit Gargb8ae6792017-06-06 20:51:31 +0530349 "scripthdraddr=0x80080000\0" \
Alison Wanga65d7402017-05-26 15:46:15 +0800350 "fdtheader_addr_r=0x80100000\0" \
351 "kernelheader_addr_r=0x80200000\0" \
352 "kernel_addr_r=0x81000000\0" \
Vinitha Pillai-B572239b457cc2017-11-22 10:38:35 +0530353 "kernelheader_size=0x40000\0" \
Alison Wanga65d7402017-05-26 15:46:15 +0800354 "fdt_addr_r=0x90000000\0" \
355 "ramdisk_addr_r=0xa0000000\0" \
356 "load_addr=0xa0000000\0" \
357 "kernel_size=0x2800000\0" \
Vinitha Pillai-B572239b457cc2017-11-22 10:38:35 +0530358 "kernel_addr_sd=0x8000\0" \
359 "kernel_size_sd=0x14000\0" \
360 "kernelhdr_addr_sd=0x4000\0" \
361 "kernelhdr_size_sd=0x10\0" \
Alison Wangfeb8fa22020-01-21 07:33:01 +0000362 "othbootargs=cma=64M@0x0-0xb0000000\0" \
Alison Wanga65d7402017-05-26 15:46:15 +0800363 BOOTENV \
364 "boot_scripts=ls1021atwr_boot.scr\0" \
Sumit Gargb8ae6792017-06-06 20:51:31 +0530365 "boot_script_hdr=hdr_ls1021atwr_bs.out\0" \
Alison Wanga65d7402017-05-26 15:46:15 +0800366 "scan_dev_for_boot_part=" \
367 "part list ${devtype} ${devnum} devplist; " \
368 "env exists devplist || setenv devplist 1; " \
369 "for distro_bootpart in ${devplist}; do " \
370 "if fstype ${devtype} " \
371 "${devnum}:${distro_bootpart} " \
372 "bootfstype; then " \
373 "run scan_dev_for_boot; " \
374 "fi; " \
375 "done\0" \
Sumit Gargb8ae6792017-06-06 20:51:31 +0530376 "scan_dev_for_boot=" \
377 "echo Scanning ${devtype} " \
378 "${devnum}:${distro_bootpart}...; " \
379 "for prefix in ${boot_prefixes}; do " \
380 "run scan_dev_for_scripts; " \
381 "done;" \
382 "\0" \
383 "boot_a_script=" \
384 "load ${devtype} ${devnum}:${distro_bootpart} " \
385 "${scriptaddr} ${prefix}${script}; " \
386 "env exists secureboot && load ${devtype} " \
387 "${devnum}:${distro_bootpart} " \
388 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
389 "&& esbc_validate ${scripthdraddr};" \
390 "source ${scriptaddr}\0" \
Alison Wanga65d7402017-05-26 15:46:15 +0800391 "qspi_bootcmd=echo Trying load from qspi..;" \
392 "sf probe && sf read $load_addr " \
Vinitha Pillai-B572239b457cc2017-11-22 10:38:35 +0530393 "$kernel_addr $kernel_size; env exists secureboot " \
394 "&& sf read $kernelheader_addr_r $kernelheader_addr " \
395 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
396 "bootm $load_addr#$board\0" \
Alison Wanga65d7402017-05-26 15:46:15 +0800397 "nor_bootcmd=echo Trying load from nor..;" \
398 "cp.b $kernel_addr $load_addr " \
Vinitha Pillai-B572239b457cc2017-11-22 10:38:35 +0530399 "$kernel_size; env exists secureboot " \
400 "&& cp.b $kernelheader_addr $kernelheader_addr_r " \
401 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
402 "bootm $load_addr#$board\0" \
Shengzhou Liu397a1732017-11-09 17:57:57 +0800403 "sd_bootcmd=echo Trying load from SD ..;" \
404 "mmcinfo && mmc read $load_addr " \
405 "$kernel_addr_sd $kernel_size_sd && " \
Vinitha Pillai-B572239b457cc2017-11-22 10:38:35 +0530406 "env exists secureboot && mmc read $kernelheader_addr_r " \
407 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
408 " && esbc_validate ${kernelheader_addr_r};" \
Shengzhou Liu397a1732017-11-09 17:57:57 +0800409 "bootm $load_addr#$board\0"
Alison Wang55d53ab2015-01-04 15:30:59 +0800410#endif
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800411
Alison Wanga65d7402017-05-26 15:46:15 +0800412#undef CONFIG_BOOTCOMMAND
413#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
Vladimir Olteanc40e65e2019-07-19 00:30:00 +0300414#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
Vinitha Pillai-B572239b457cc2017-11-22 10:38:35 +0530415 "env exists secureboot && esbc_halt"
Shengzhou Liu397a1732017-11-09 17:57:57 +0800416#elif defined(CONFIG_SD_BOOT)
Vinitha Pillai-B572239b457cc2017-11-22 10:38:35 +0530417#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \
418 "env exists secureboot && esbc_halt;"
Alison Wanga65d7402017-05-26 15:46:15 +0800419#else
Vinitha Pillai-B572239b457cc2017-11-22 10:38:35 +0530420#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd;" \
421 "env exists secureboot && esbc_halt;"
Alison Wanga65d7402017-05-26 15:46:15 +0800422#endif
423
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800424/*
425 * Miscellaneous configurable options
426 */
Alison Wangc463eeb2020-02-03 15:25:19 +0800427#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800428
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800429#define CONFIG_SYS_LOAD_ADDR 0x82000000
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800430
Xiubo Li660673a2014-11-21 17:40:59 +0800431#define CONFIG_LS102XA_STREAM_ID
432
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800433#define CONFIG_SYS_INIT_SP_OFFSET \
434 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
435#define CONFIG_SYS_INIT_SP_ADDR \
436 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
437
Alison Wang8415bb62014-12-03 15:00:48 +0800438#ifdef CONFIG_SPL_BUILD
439#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
Biwen Li9ebde882019-12-31 15:33:44 +0800440#undef CONFIG_DM_I2C
Alison Wang8415bb62014-12-03 15:00:48 +0800441#else
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800442#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Alison Wang8415bb62014-12-03 15:00:48 +0800443#endif
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800444
Alison Wang615bfce2017-05-16 10:45:57 +0800445#define CONFIG_SYS_QE_FW_ADDR 0x60940000
Zhao Qiangeaa859e2014-09-26 16:25:33 +0800446
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800447/*
448 * Environment
449 */
450#define CONFIG_ENV_OVERWRITE
451
Alison Wang8415bb62014-12-03 15:00:48 +0800452#if defined(CONFIG_SD_BOOT)
Alison Wang8415bb62014-12-03 15:00:48 +0800453#define CONFIG_SYS_MMC_ENV_DEV 0
Alison Wang8415bb62014-12-03 15:00:48 +0800454#endif
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800455
Aneesh Bansalef6c55a2016-01-22 16:37:22 +0530456#include <asm/fsl_secure_boot.h>
Alison Wangcc7b8b92016-01-15 15:29:32 +0800457#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
Ruchika Gupta4ba4a092014-10-15 11:39:06 +0530458
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800459#endif