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wdenk0f8c9762002-08-19 11:57:05 +00001/*
2 * (C) Copyright 2000
3 * Murray Jensen <Murray.Jensen@cmst.csiro.au>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * Config header file for Cogent platform using an MPC8xx CPU module
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
37#define CONFIG_COGENT 1 /* using Cogent Modular Architecture */
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050038#define CONFIG_CPM2 1 /* Has a CPM2 */
wdenk0f8c9762002-08-19 11:57:05 +000039
Wolfgang Denk2ae18242010-10-06 09:05:45 +020040#define CONFIG_SYS_TEXT_BASE 0xfff00000
41
wdenkc837dcb2004-01-20 23:12:12 +000042#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
Peter Tyser3a8f28d2009-09-16 22:03:07 -050043#define CONFIG_MISC_INIT_R /* Use misc_init_r() */
wdenkc837dcb2004-01-20 23:12:12 +000044
wdenk0f8c9762002-08-19 11:57:05 +000045/* Cogent Modular Architecture options */
46#define CONFIG_CMA282 1 /* ...on a CMA282 CPU module */
47#define CONFIG_CMA111 1 /* ...on a CMA111 motherboard */
48
49/*
50 * select serial console configuration
51 *
52 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
53 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
54 * for SCC).
55 *
56 * if CONFIG_CONS_NONE is defined, then the serial console routines must
57 * defined elsewhere (for example, on the cogent platform, there are serial
58 * ports on the motherboard which are used for the serial console - see
59 * cogent/cma101/serial.[ch]).
60 */
61#define CONFIG_CONS_ON_SMC /* define if console on SMC */
62#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
63#undef CONFIG_CONS_NONE /* define if console on something else*/
64#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
65#undef CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */
66#define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */
67#define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/
68
69/*
70 * select ethernet configuration
71 *
72 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
73 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
74 * for FCC)
75 *
76 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
Jon Loeliger639221c2007-07-09 17:15:49 -050077 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
wdenk0f8c9762002-08-19 11:57:05 +000078 */
79#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
80#undef CONFIG_ETHER_ON_FCC /* define if ether on FCC */
81#define CONFIG_ETHER_NONE /* define if ether on something else */
82#define CONFIG_ETHER_INDEX 1 /* which channel for ether */
83
84/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
85#define CONFIG_8260_CLKIN 66666666 /* in Hz */
86
87#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
88#define CONFIG_BAUDRATE 230400
89#else
90#define CONFIG_BAUDRATE 9600
91#endif
92
wdenk0f8c9762002-08-19 11:57:05 +000093
Jon Loeliger37e4f242007-07-04 22:31:56 -050094/*
Jon Loeliger80ff4f92007-07-10 09:29:01 -050095 * BOOTP options
96 */
97#define CONFIG_BOOTP_BOOTFILESIZE
98#define CONFIG_BOOTP_BOOTPATH
99#define CONFIG_BOOTP_GATEWAY
100#define CONFIG_BOOTP_HOSTNAME
101
102
103/*
Jon Loeliger37e4f242007-07-04 22:31:56 -0500104 * Command line configuration.
105 */
106#include <config_cmd_default.h>
107
108#define CONFIG_CMD_KGDB
109
110#undef CONFIG_CMD_NET
111
wdenk0f8c9762002-08-19 11:57:05 +0000112
113#ifdef DEBUG
114#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
115#else
116#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
117#endif
118#define CONFIG_BOOTCOMMAND "bootm 04080000 04200000" /* autoboot command*/
119
120#define CONFIG_BOOTARGS "root=/dev/ram rw"
121
Jon Loeliger37e4f242007-07-04 22:31:56 -0500122#if defined(CONFIG_CMD_KGDB)
wdenk0f8c9762002-08-19 11:57:05 +0000123#define CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
124#undef CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
125#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
126#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
127#define CONFIG_KGDB_USE_EXTC /* SMC/SCC use ext clock not brg_clk */
128#define CONFIG_KGDB_EXTC_RATE 3686400 /* serial ext clk rate in Hz */
129#define CONFIG_KGDB_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/
130# if defined(CONFIG_KGDB_NONE) || defined(CONFIG_KGDB_USE_EXTC)
131#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port at */
132# else
133#define CONFIG_KGDB_BAUDRATE 9600 /* speed to run kgdb serial port at */
134# endif
135#endif
136
137#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
138
139/*
140 * Miscellaneous configurable options
141 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142#define CONFIG_SYS_LONGHELP /* undef to save memory */
143#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger37e4f242007-07-04 22:31:56 -0500144#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200145#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk0f8c9762002-08-19 11:57:05 +0000146#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk0f8c9762002-08-19 11:57:05 +0000148#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200149#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
150#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
151#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk0f8c9762002-08-19 11:57:05 +0000152
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
154#define CONFIG_SYS_MEMTEST_END 0x01c00000 /* 4 ... 28 MB in DRAM */
wdenk0f8c9762002-08-19 11:57:05 +0000155
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenk0f8c9762002-08-19 11:57:05 +0000157
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenk0f8c9762002-08-19 11:57:05 +0000159
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200160#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
wdenk0f8c9762002-08-19 11:57:05 +0000161
162/*
163 * Low Level Configuration Settings
164 * (address mappings, register initial values, etc.)
165 * You should know what you are doing if you make changes here.
166 */
167
168/*-----------------------------------------------------------------------
169 * Low Level Cogent settings
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170 * if CONFIG_SYS_CMA_CONS_SERIAL is defined, make sure the 8260 CPM serial is not.
wdenk0f8c9762002-08-19 11:57:05 +0000171 * also, make sure CONFIG_CONS_INDEX is still defined - the index will be
172 * 1 for serialA, 2 for serialB, 3 for ser2A, 4 for ser2B
173 * (second 2 for CMA120 only)
174 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175#define CONFIG_SYS_CMA_MB_BASE 0x00000000 /* base of m/b address space */
wdenk0f8c9762002-08-19 11:57:05 +0000176
177#include <configs/cogent_common.h>
178
179#ifdef CONFIG_CONS_NONE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180#define CONFIG_SYS_CMA_CONS_SERIAL /* use Cogent motherboard serial for console */
wdenk0f8c9762002-08-19 11:57:05 +0000181#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182#define CONFIG_SYS_CMA_LCD_HEARTBEAT /* define for sec rotator in lcd corner */
wdenka8c7c702003-12-06 19:49:23 +0000183#define CONFIG_SHOW_ACTIVITY
wdenk0f8c9762002-08-19 11:57:05 +0000184
185#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)
186/*
187 * flash exists on the motherboard
188 * set these four according to TOP dipsw:
189 * TOP on => ..._FLLOW_... (boot EPROM space is high so FLASH is low )
190 * TOP off => ..._FLHIGH_... (boot EPROM space is low so FLASH is high)
191 */
192#define CMA_MB_FLASH_EXEC_BASE CMA_MB_FLLOW_EXEC_BASE
193#define CMA_MB_FLASH_EXEC_SIZE CMA_MB_FLLOW_EXEC_SIZE
194#define CMA_MB_FLASH_RDWR_BASE CMA_MB_FLLOW_RDWR_BASE
195#define CMA_MB_FLASH_RDWR_SIZE CMA_MB_FLLOW_RDWR_SIZE
196#endif
197#define CMA_MB_FLASH_BASE CMA_MB_FLASH_EXEC_BASE
198#define CMA_MB_FLASH_SIZE CMA_MB_FLASH_EXEC_SIZE
199
200/*-----------------------------------------------------------------------
201 * Hard Reset Configuration Words
202 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203 * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
wdenk0f8c9762002-08-19 11:57:05 +0000204 * defines for the various registers affected by the HRCW e.g. changing
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205 * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
wdenk0f8c9762002-08-19 11:57:05 +0000206 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207#define CONFIG_SYS_HRCW_MASTER (HRCW_EBM|HRCW_BPS10|HRCW_L2CPC10|HRCW_DPPC11|\
wdenk0f8c9762002-08-19 11:57:05 +0000208 HRCW_ISB100|HRCW_MMR11|HRCW_MODCK_H0101)
209/* no slaves so just duplicate the master hrcw */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210#define CONFIG_SYS_HRCW_SLAVE1 CONFIG_SYS_HRCW_MASTER
211#define CONFIG_SYS_HRCW_SLAVE2 CONFIG_SYS_HRCW_MASTER
212#define CONFIG_SYS_HRCW_SLAVE3 CONFIG_SYS_HRCW_MASTER
213#define CONFIG_SYS_HRCW_SLAVE4 CONFIG_SYS_HRCW_MASTER
214#define CONFIG_SYS_HRCW_SLAVE5 CONFIG_SYS_HRCW_MASTER
215#define CONFIG_SYS_HRCW_SLAVE6 CONFIG_SYS_HRCW_MASTER
216#define CONFIG_SYS_HRCW_SLAVE7 CONFIG_SYS_HRCW_MASTER
wdenk0f8c9762002-08-19 11:57:05 +0000217
218/*-----------------------------------------------------------------------
219 * Internal Memory Mapped Register
220 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#define CONFIG_SYS_IMMR 0xF0000000
wdenk0f8c9762002-08-19 11:57:05 +0000222
223/*-----------------------------------------------------------------------
224 * Definitions for initial stack pointer and data area (in DPRAM)
225 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200226#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
227#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
228#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
229#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
230#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk0f8c9762002-08-19 11:57:05 +0000231
232/*-----------------------------------------------------------------------
233 * Start addresses for the final memory configuration
234 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200235 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenk0f8c9762002-08-19 11:57:05 +0000236 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200237#define CONFIG_SYS_SDRAM_BASE CMA_MB_RAM_BASE
wdenk0f8c9762002-08-19 11:57:05 +0000238#ifdef CONFIG_CMA302
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200239#define CONFIG_SYS_FLASH_BASE CMA_MB_SLOT2_BASE /* cma302 in slot 2 */
wdenk0f8c9762002-08-19 11:57:05 +0000240#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241#define CONFIG_SYS_FLASH_BASE CMA_MB_FLASH_BASE /* flash on m/b */
wdenk0f8c9762002-08-19 11:57:05 +0000242#endif
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200243#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200244#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
245#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
wdenk0f8c9762002-08-19 11:57:05 +0000246
247/*
248 * For booting Linux, the board info and command line data
249 * have to be in the first 8 MB of memory, since this is
250 * the maximum mapped by the Linux kernel during initialization.
251 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200252#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/
wdenk0f8c9762002-08-19 11:57:05 +0000253
254/*-----------------------------------------------------------------------
255 * FLASH organization
256 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200257#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of memory banks */
258#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max num of sects on one chip */
wdenk0f8c9762002-08-19 11:57:05 +0000259
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200260#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Flash Erase Timeout (in ms) */
261#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
wdenk0f8c9762002-08-19 11:57:05 +0000262
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200263#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264#define CONFIG_ENV_ADDR CONFIG_SYS_FLASH_BASE /* Addr of Environment Sector */
wdenk0f8c9762002-08-19 11:57:05 +0000265#ifdef CONFIG_CMA302
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200266#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
267#define CONFIG_ENV_SECT_SIZE (512*1024) /* see README - env sect real size */
wdenk0f8c9762002-08-19 11:57:05 +0000268#else
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200269#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
wdenk0f8c9762002-08-19 11:57:05 +0000270#endif
271
272/*-----------------------------------------------------------------------
273 * Cache Configuration
274 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200275#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
Jon Loeliger37e4f242007-07-04 22:31:56 -0500276#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200277# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value*/
wdenk0f8c9762002-08-19 11:57:05 +0000278#endif
279
280/*-----------------------------------------------------------------------
281 * HIDx - Hardware Implementation-dependent Registers 2-11
282 *-----------------------------------------------------------------------
283 * HID0 also contains cache control - initially enable both caches and
284 * invalidate contents, then the final state leaves only the instruction
285 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
286 * but Soft reset does not.
287 *
288 * HID1 has only read-only information - nothing to set.
289 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200290#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
wdenk0f8c9762002-08-19 11:57:05 +0000291 HID0_IFEM|HID0_ABE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200292#define CONFIG_SYS_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE)
293#define CONFIG_SYS_HID2 0
wdenk0f8c9762002-08-19 11:57:05 +0000294
295/*-----------------------------------------------------------------------
296 * RMR - Reset Mode Register 5-5
297 *-----------------------------------------------------------------------
298 * turn on Checkstop Reset Enable
299 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200300#define CONFIG_SYS_RMR RMR_CSRE
wdenk0f8c9762002-08-19 11:57:05 +0000301
302/*-----------------------------------------------------------------------
303 * BCR - Bus Configuration 4-25
304 *-----------------------------------------------------------------------
305 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200306#define CONFIG_SYS_BCR BCR_EBM
wdenk0f8c9762002-08-19 11:57:05 +0000307
308/*-----------------------------------------------------------------------
309 * SIUMCR - SIU Module Configuration 4-31
310 *-----------------------------------------------------------------------
311 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200312#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC11|SIUMCR_L2CPC10|SIUMCR_MMR11)
wdenk0f8c9762002-08-19 11:57:05 +0000313
314/*-----------------------------------------------------------------------
315 * SYPCR - System Protection Control 4-35
316 * SYPCR can only be written once after reset!
317 *-----------------------------------------------------------------------
318 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
319 */
320#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200321#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
wdenk0f8c9762002-08-19 11:57:05 +0000322 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
323#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200324#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
wdenk0f8c9762002-08-19 11:57:05 +0000325 SYPCR_SWRI|SYPCR_SWP)
326#endif /* CONFIG_WATCHDOG */
327
328/*-----------------------------------------------------------------------
329 * TMCNTSC - Time Counter Status and Control 4-40
330 *-----------------------------------------------------------------------
331 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
332 * and enable Time Counter
333 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200334#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
wdenk0f8c9762002-08-19 11:57:05 +0000335
336/*-----------------------------------------------------------------------
337 * PISCR - Periodic Interrupt Status and Control 4-42
338 *-----------------------------------------------------------------------
339 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
340 * Periodic timer
341 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200342#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
wdenk0f8c9762002-08-19 11:57:05 +0000343
344/*-----------------------------------------------------------------------
345 * SCCR - System Clock Control 9-8
346 *-----------------------------------------------------------------------
347 * Ensure DFBRG is Divide by 16
348 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200349#define CONFIG_SYS_SCCR (SCCR_DFBRG01)
wdenk0f8c9762002-08-19 11:57:05 +0000350
351/*-----------------------------------------------------------------------
352 * RCCR - RISC Controller Configuration 13-7
353 *-----------------------------------------------------------------------
354 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200355#define CONFIG_SYS_RCCR 0
wdenk0f8c9762002-08-19 11:57:05 +0000356
357#if defined(CONFIG_CMA282)
358
359/*
360 * Init Memory Controller:
361 *
362 * According to the Cogent manual, only CS0 and CS2 are used - CS0 for EPROM
363 * and CS2 for (optional) local bus RAM on the CPU module.
364 *
365 * Note the motherboard address space (256 Mbyte in size) is connected
366 * to the 60x Bus and is located starting at address 0. The Hard Reset
367 * Configuration Word should put the 60x Bus into External Bus Mode, since
368 * we dont set up any memory controller maps for it (see BCR[EBM], 4-26).
369 *
370 * (the *_SIZE vars must be a power of 2)
371 */
372
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200373#define CONFIG_SYS_CMA_CS0_BASE CONFIG_SYS_TEXT_BASE /* EPROM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200374#define CONFIG_SYS_CMA_CS0_SIZE (1 << 20)
wdenk0f8c9762002-08-19 11:57:05 +0000375#if 0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200376#define CONFIG_SYS_CMA_CS2_BASE 0x10000000 /* Local Bus SDRAM */
377#define CONFIG_SYS_CMA_CS2_SIZE (16 << 20)
wdenk0f8c9762002-08-19 11:57:05 +0000378#endif
379
380/*
381 * CS0 maps the EPROM on the cpu module
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200382 * Set it for 10 wait states, address CONFIG_SYS_MONITOR_BASE and size 1M
wdenk0f8c9762002-08-19 11:57:05 +0000383 *
384 * Note: We must have already transferred control to the final location
385 * of the EPROM before these are used, because when BR0/OR0 are set, the
386 * mirror of the eprom at any other addresses will disappear.
387 */
388
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200389/* base address = CONFIG_SYS_CMA_CS0_BASE, 16-bit, no parity, r/o, gpcm (60x bus) */
390#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_CMA_CS0_BASE&BRx_BA_MSK)|BRx_PS_16|BRx_WP|BRx_V)
391/* mask size CONFIG_SYS_CMA_CS0_SIZE, csneg 1/4 early, adr-to-cs 1/2, 10-wait states */
392#define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_CMA_CS0_SIZE)|\
wdenk0f8c9762002-08-19 11:57:05 +0000393 ORxG_CSNT|ORxG_ACS_DIV2|ORxG_SCY_10_CLK)
394
395/*
396 * CS2 enables the Local Bus SDRAM on the CPU Module
397 *
398 * Will leave this unset for the moment, because a) my CPU module has no
399 * SDRAM installed (it is optional); and b) it will require programming
400 * one of the UPMs in SDRAM mode - not a trivial job, and hard to get right
401 * if you can't test it.
402 */
403
404#if 0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200405/* base address = CONFIG_SYS_CMA_CS2_BASE, 32-bit, no parity, ??? */
406#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_CMA_CS2_BASE&BRx_BA_MSK)|BRx_PS_32|/*???*/|BRx_V)
407/* mask size CONFIG_SYS_CMA_CS2_SIZE, CS time normal, ??? */
408#define CONFIG_SYS_OR2_PRELIM ((~(CONFIG_SYS_CMA_CS2_SIZE-1)&ORx_AM_MSK)|/*???*/)
wdenk0f8c9762002-08-19 11:57:05 +0000409#endif
410
411#endif
wdenk0f8c9762002-08-19 11:57:05 +0000412#endif /* __CONFIG_H */