Keerthy | 0bfc701 | 2022-01-27 13:16:57 +0100 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ |
| 4 | */ |
| 5 | |
| 6 | / { |
| 7 | chosen { |
| 8 | firmware-loader = &fs_loader0; |
| 9 | }; |
| 10 | |
| 11 | fs_loader0: fs_loader@0 { |
| 12 | u-boot,dm-pre-reloc; |
| 13 | compatible = "u-boot,fs-loader"; |
| 14 | phandlepart = <&mmc1 1>; |
| 15 | }; |
| 16 | |
| 17 | reserved-memory { |
| 18 | #address-cells = <2>; |
| 19 | #size-cells = <2>; |
| 20 | ranges; |
| 21 | u-boot,dm-spl; |
| 22 | |
| 23 | ipu2_memory_region: ipu2-memory@95800000 { |
| 24 | compatible = "shared-dma-pool"; |
| 25 | reg = <0x0 0x95800000 0x0 0x3800000>; |
| 26 | reusable; |
| 27 | status = "okay"; |
| 28 | u-boot,dm-spl; |
| 29 | }; |
| 30 | |
| 31 | ipu1_memory_region: ipu1-memory@9d000000 { |
| 32 | compatible = "shared-dma-pool"; |
| 33 | reg = <0x0 0x9d000000 0x0 0x2000000>; |
| 34 | reusable; |
| 35 | status = "okay"; |
| 36 | u-boot,dm-spl; |
| 37 | }; |
| 38 | |
| 39 | ipu1_pgtbl: ipu1-pgtbl@95700000 { |
| 40 | reg = <0x0 0x95700000 0x0 0x40000>; |
| 41 | no-map; |
| 42 | u-boot,dm-spl; |
| 43 | }; |
| 44 | |
| 45 | ipu2_pgtbl: ipu2-pgtbl@95740000 { |
| 46 | reg = <0x0 0x95740000 0x0 0x40000>; |
| 47 | no-map; |
| 48 | u-boot,dm-spl; |
| 49 | }; |
| 50 | }; |
| 51 | }; |
| 52 | |
| 53 | &timer3 { |
| 54 | u-boot,dm-spl; |
| 55 | }; |
| 56 | |
| 57 | &timer4 { |
| 58 | u-boot,dm-spl; |
| 59 | }; |
| 60 | |
| 61 | &timer7 { |
| 62 | u-boot,dm-spl; |
| 63 | }; |
| 64 | |
| 65 | &timer8 { |
| 66 | u-boot,dm-spl; |
| 67 | }; |
| 68 | |
| 69 | &timer9 { |
| 70 | u-boot,dm-spl; |
| 71 | }; |
| 72 | |
| 73 | &timer11 { |
| 74 | u-boot,dm-spl; |
| 75 | }; |
| 76 | |
| 77 | &mmu_ipu1 { |
| 78 | u-boot,dm-spl; |
| 79 | }; |
| 80 | |
| 81 | &mmu_ipu2 { |
| 82 | u-boot,dm-spl; |
| 83 | }; |
| 84 | |
| 85 | &ipu1 { |
| 86 | status = "okay"; |
| 87 | memory-region = <&ipu1_memory_region>; |
| 88 | pg-tbl = <&ipu1_pgtbl>; |
| 89 | u-boot,dm-spl; |
| 90 | }; |
| 91 | |
| 92 | &ipu2 { |
| 93 | status = "okay"; |
| 94 | memory-region = <&ipu2_memory_region>; |
| 95 | pg-tbl = <&ipu2_pgtbl>; |
| 96 | u-boot,dm-spl; |
| 97 | }; |
| 98 | |
| 99 | &l4_wkup { |
| 100 | u-boot,dm-spl; |
| 101 | }; |
| 102 | |
| 103 | &prm { |
| 104 | u-boot,dm-spl; |
| 105 | }; |
| 106 | |
| 107 | &ipu1_rst { |
| 108 | u-boot,dm-spl; |
| 109 | }; |
| 110 | |
| 111 | &ipu2_rst { |
| 112 | u-boot,dm-spl; |
| 113 | }; |