blob: 26140a79ebecb284cd56bb297ada759c7c42840e [file] [log] [blame]
Marcel Ziswiler2bc2f812022-02-07 11:54:13 +01001// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2/*
3 * Copyright 2022 Toradex
4 */
5
6#include "imx8mp-u-boot.dtsi"
7
8/ {
9 firmware {
10 optee {
11 compatible = "linaro,optee-tz";
12 method = "smc";
13 };
14 };
15
16 wdt-reboot {
17 compatible = "wdt-reboot";
18 u-boot,dm-spl;
19 wdt = <&wdog1>;
20 };
21};
22
23&clk {
24 u-boot,dm-pre-reloc;
25 u-boot,dm-spl;
26 /delete-property/ assigned-clocks;
27 /delete-property/ assigned-clock-parents;
28 /delete-property/ assigned-clock-rates;
29
30};
31
32&eqos {
Marcel Ziswiler2bc2f812022-02-07 11:54:13 +010033 /delete-property/ assigned-clocks;
34 /delete-property/ assigned-clock-parents;
35 /delete-property/ assigned-clock-rates;
36};
37
38&gpio1 {
39 u-boot,dm-spl;
40};
41
42&gpio2 {
43 u-boot,dm-spl;
44};
45
46&gpio3 {
47 u-boot,dm-spl;
48};
49
50&gpio4 {
51 u-boot,dm-spl;
52};
53
54&gpio5 {
55 u-boot,dm-spl;
56};
57
58&i2c1 {
59 u-boot,dm-spl;
60};
61
62&i2c2 {
63 u-boot,dm-spl;
64};
65
66&i2c3 {
67 u-boot,dm-spl;
68};
69
70&pinctrl_i2c1 {
71 u-boot,dm-spl;
72};
73
74&pinctrl_reg_usdhc2_vmmc {
75 u-boot,dm-spl;
76 u-boot,off-on-delay-us = <20000>;
77};
78
79&pinctrl_uart3 {
80 u-boot,dm-spl;
81};
82
83&pinctrl_usdhc2_gpio {
84 u-boot,dm-spl;
85};
86
87&pinctrl_usdhc2 {
88 u-boot,dm-spl;
89};
90
91&pinctrl_usdhc3 {
92 u-boot,dm-spl;
93};
94
95&pinctrl_wdog {
96 u-boot,dm-spl;
97};
98
99&pmic {
100 u-boot,dm-spl;
101};
102
103&reg_usdhc2_vmmc {
104 u-boot,dm-spl;
105};
106
107&uart3 {
108 u-boot,dm-spl;
109};
110
111&usdhc2 {
112 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
113 assigned-clock-rates = <400000000>;
114 assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
115 sd-uhs-ddr50;
116 sd-uhs-sdr104;
117 u-boot,dm-spl;
118};
119
120&usdhc3 {
121 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
122 assigned-clock-rates = <400000000>;
123 assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
124 mmc-hs400-1_8v;
125 mmc-hs400-enhanced-strobe;
126 u-boot,dm-spl;
127};
128
129&wdog1 {
130 u-boot,dm-spl;
131};