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Masahiro Yamada7865f4b2015-04-21 20:38:20 +09001if ARCH_SOCFPGA
2
Dalon Westergreenf0fb4fa2017-02-10 17:15:34 -08003config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
4 default 0xa2
5
Marek Vasutcd9b7312015-08-02 21:57:57 +02006config TARGET_SOCFPGA_ARRIA5
7 bool
Dinh Nguyened77aeb2015-12-02 13:31:25 -06008 select TARGET_SOCFPGA_GEN5
Marek Vasutcd9b7312015-08-02 21:57:57 +02009
Ley Foon Tand89e9792017-04-26 02:44:48 +080010config TARGET_SOCFPGA_ARRIA10
11 bool
Tien Fong Chee901af3e2017-12-05 15:58:03 +080012 select ALTERA_SDRAM
Michal Simek58008cb2018-07-23 15:55:15 +020013 select SPL_BOARD_INIT if SPL
Ley Foon Tand89e9792017-04-26 02:44:48 +080014
Marek Vasutcd9b7312015-08-02 21:57:57 +020015config TARGET_SOCFPGA_CYCLONE5
16 bool
Dinh Nguyened77aeb2015-12-02 13:31:25 -060017 select TARGET_SOCFPGA_GEN5
18
19config TARGET_SOCFPGA_GEN5
20 bool
Ley Foon Tan707cd012017-04-05 17:32:51 +080021 select ALTERA_SDRAM
Marek Vasutcd9b7312015-08-02 21:57:57 +020022
Ley Foon Tana6847292018-05-24 00:17:32 +080023config TARGET_SOCFPGA_STRATIX10
24 bool
25 select ARMV8_MULTIENTRY
Ley Foon Tana6847292018-05-24 00:17:32 +080026 select ARMV8_SET_SMPEN
Michal Simek58008cb2018-07-23 15:55:15 +020027 select ARMV8_SPIN_TABLE
Ley Foon Tana6847292018-05-24 00:17:32 +080028
Masahiro Yamada7865f4b2015-04-21 20:38:20 +090029choice
30 prompt "Altera SOCFPGA board select"
Joe Hershbergera26cd042015-05-12 14:46:23 -050031 optional
Masahiro Yamada7865f4b2015-04-21 20:38:20 +090032
Ley Foon Tand89e9792017-04-26 02:44:48 +080033config TARGET_SOCFPGA_ARRIA10_SOCDK
34 bool "Altera SOCFPGA SoCDK (Arria 10)"
35 select TARGET_SOCFPGA_ARRIA10
36
Marek Vasutcd9b7312015-08-02 21:57:57 +020037config TARGET_SOCFPGA_ARRIA5_SOCDK
38 bool "Altera SOCFPGA SoCDK (Arria V)"
39 select TARGET_SOCFPGA_ARRIA5
Masahiro Yamada7865f4b2015-04-21 20:38:20 +090040
Marek Vasutcd9b7312015-08-02 21:57:57 +020041config TARGET_SOCFPGA_CYCLONE5_SOCDK
42 bool "Altera SOCFPGA SoCDK (Cyclone V)"
43 select TARGET_SOCFPGA_CYCLONE5
Masahiro Yamada7865f4b2015-04-21 20:38:20 +090044
Marek Vasut7fb46432018-02-24 23:34:00 +010045config TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
46 bool "Devboards DBM-SoC1 (Cyclone V)"
47 select TARGET_SOCFPGA_CYCLONE5
48
Marek Vasut856b30d2015-11-23 17:06:27 +010049config TARGET_SOCFPGA_EBV_SOCRATES
50 bool "EBV SoCrates (Cyclone V)"
51 select TARGET_SOCFPGA_CYCLONE5
52
Pavel Machek35546f62016-06-07 12:37:23 +020053config TARGET_SOCFPGA_IS1
54 bool "IS1 (Cyclone V)"
55 select TARGET_SOCFPGA_CYCLONE5
56
Marek Vasut569a1912015-12-01 18:09:52 +010057config TARGET_SOCFPGA_SAMTEC_VINING_FPGA
58 bool "samtec VIN|ING FPGA (Cyclone V)"
Tom Rinie5ec4812017-01-22 19:43:11 -050059 select BOARD_LATE_INIT
Marek Vasut569a1912015-12-01 18:09:52 +010060 select TARGET_SOCFPGA_CYCLONE5
61
Marek Vasutcf0a8da2016-06-08 02:57:05 +020062config TARGET_SOCFPGA_SR1500
63 bool "SR1500 (Cyclone V)"
64 select TARGET_SOCFPGA_CYCLONE5
65
Ley Foon Tana6847292018-05-24 00:17:32 +080066config TARGET_SOCFPGA_STRATIX10_SOCDK
67 bool "Intel SOCFPGA SoCDK (Stratix 10)"
68 select TARGET_SOCFPGA_STRATIX10
69
Dinh Nguyen55c7a762015-09-01 17:41:52 -050070config TARGET_SOCFPGA_TERASIC_DE0_NANO
71 bool "Terasic DE0-Nano-Atlas (Cyclone V)"
72 select TARGET_SOCFPGA_CYCLONE5
73
Dalon Westergreen6bd041f2017-04-18 08:11:16 -070074config TARGET_SOCFPGA_TERASIC_DE10_NANO
75 bool "Terasic DE10-Nano (Cyclone V)"
76 select TARGET_SOCFPGA_CYCLONE5
77
Anatolij Gustschine9c847c2016-11-14 16:07:10 +010078config TARGET_SOCFPGA_TERASIC_DE1_SOC
79 bool "Terasic DE1-SoC (Cyclone V)"
80 select TARGET_SOCFPGA_CYCLONE5
81
Marek Vasut952caa22015-06-21 17:28:53 +020082config TARGET_SOCFPGA_TERASIC_SOCKIT
83 bool "Terasic SoCkit (Cyclone V)"
84 select TARGET_SOCFPGA_CYCLONE5
85
Masahiro Yamada7865f4b2015-04-21 20:38:20 +090086endchoice
87
88config SYS_BOARD
Marek Vasutf0892402015-08-10 21:24:53 +020089 default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
Ley Foon Tand89e9792017-04-26 02:44:48 +080090 default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
Marek Vasutf0892402015-08-10 21:24:53 +020091 default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Marek Vasut7fb46432018-02-24 23:34:00 +010092 default "dbm-soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
Dinh Nguyen55c7a762015-09-01 17:41:52 -050093 default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Anatolij Gustschine9c847c2016-11-14 16:07:10 +010094 default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
Dalon Westergreen6bd041f2017-04-18 08:11:16 -070095 default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
Pavel Machek35546f62016-06-07 12:37:23 +020096 default "is1" if TARGET_SOCFPGA_IS1
Marek Vasut952caa22015-06-21 17:28:53 +020097 default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
Marek Vasut856b30d2015-11-23 17:06:27 +010098 default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
Stefan Roeseae9996c2015-11-18 11:06:09 +010099 default "sr1500" if TARGET_SOCFPGA_SR1500
Ley Foon Tana6847292018-05-24 00:17:32 +0800100 default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
Marek Vasut569a1912015-12-01 18:09:52 +0100101 default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
Masahiro Yamada7865f4b2015-04-21 20:38:20 +0900102
103config SYS_VENDOR
Marek Vasutcd9b7312015-08-02 21:57:57 +0200104 default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
Ley Foon Tand89e9792017-04-26 02:44:48 +0800105 default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
Marek Vasutcd9b7312015-08-02 21:57:57 +0200106 default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Ley Foon Tana6847292018-05-24 00:17:32 +0800107 default "altera" if TARGET_SOCFPGA_STRATIX10_SOCDK
Marek Vasut7fb46432018-02-24 23:34:00 +0100108 default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
Marek Vasut856b30d2015-11-23 17:06:27 +0100109 default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
Marek Vasut569a1912015-12-01 18:09:52 +0100110 default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
Dinh Nguyen55c7a762015-09-01 17:41:52 -0500111 default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Anatolij Gustschine9c847c2016-11-14 16:07:10 +0100112 default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC
Dalon Westergreen6bd041f2017-04-18 08:11:16 -0700113 default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO
Marek Vasut952caa22015-06-21 17:28:53 +0200114 default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
Masahiro Yamada7865f4b2015-04-21 20:38:20 +0900115
116config SYS_SOC
117 default "socfpga"
118
119config SYS_CONFIG_NAME
Dinh Nguyen3cbc7b82015-09-22 17:01:32 -0500120 default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
Ley Foon Tand89e9792017-04-26 02:44:48 +0800121 default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
Dinh Nguyen3cbc7b82015-09-22 17:01:32 -0500122 default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Marek Vasut7fb46432018-02-24 23:34:00 +0100123 default "socfpga_dbm_soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
Dinh Nguyen55c7a762015-09-01 17:41:52 -0500124 default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Anatolij Gustschine9c847c2016-11-14 16:07:10 +0100125 default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
Dalon Westergreen6bd041f2017-04-18 08:11:16 -0700126 default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
Pavel Machek35546f62016-06-07 12:37:23 +0200127 default "socfpga_is1" if TARGET_SOCFPGA_IS1
Marek Vasut952caa22015-06-21 17:28:53 +0200128 default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
Marek Vasut856b30d2015-11-23 17:06:27 +0100129 default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
Stefan Roeseae9996c2015-11-18 11:06:09 +0100130 default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
Ley Foon Tana6847292018-05-24 00:17:32 +0800131 default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
Marek Vasut569a1912015-12-01 18:09:52 +0100132 default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
Masahiro Yamada7865f4b2015-04-21 20:38:20 +0900133
134endif